/openbmc/linux/drivers/spi/ |
H A D | spi-cadence-quadspi.c | 422 void __iomem *reg_base = cqspi->iobase; in cqspi_exec_flash_cmd() local 449 void __iomem *reg_base = cqspi->iobase; in cqspi_setup_opcode_ext() local 471 void __iomem *reg_base = cqspi->iobase; in cqspi_enable_dtr() local 503 void __iomem *reg_base = cqspi->iobase; in cqspi_command_read() local 586 void __iomem *reg_base = cqspi->iobase; in cqspi_command_write() local 655 void __iomem *reg_base = cqspi->iobase; in cqspi_read_setup() local 686 reg = readl(reg_base + CQSPI_REG_SIZE); in cqspi_read_setup() 689 writel(reg, reg_base + CQSPI_REG_SIZE); in cqspi_read_setup() 699 void __iomem *reg_base = cqspi->iobase; in cqspi_indirect_read_execute() local 808 void __iomem *reg_base = cqspi->iobase; in cqspi_controller_enable() local [all …]
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H A D | spi-pci1xxxx.c | 79 void __iomem *reg_base; member 189 regval = readl(par->reg_base + in pci1xxxx_spi_transfer_one() 202 writel(regval, par->reg_base + in pci1xxxx_spi_transfer_one() 204 regval = readl(par->reg_base + in pci1xxxx_spi_transfer_one() 207 writel(regval, par->reg_base + in pci1xxxx_spi_transfer_one() 298 if (!spi_bus->reg_base) { in pci1xxxx_spi_probe() 312 regval = readl(spi_bus->reg_base + in pci1xxxx_spi_probe() 392 regval = readl(spi_ptr->reg_base + in store_restore_config() 396 regval = readl(spi_ptr->reg_base + in store_restore_config() 421 writel(regval, spi_ptr->reg_base + in pci1xxxx_spi_resume() [all …]
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/openbmc/linux/drivers/clk/samsung/ |
H A D | clk-exynos-audss.c | 21 static void __iomem *reg_base; variable 139 if (IS_ERR(reg_base)) in exynos_audss_clk_probe() 140 return PTR_ERR(reg_base); in exynos_audss_clk_probe() 186 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); in exynos_audss_clk_probe() 197 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); in exynos_audss_clk_probe() 213 reg_base + ASS_CLK_GATE, 0, 0, &lock); in exynos_audss_clk_probe() 217 reg_base + ASS_CLK_GATE, 2, 0, &lock); in exynos_audss_clk_probe() 221 reg_base + ASS_CLK_GATE, 3, 0, &lock); in exynos_audss_clk_probe() 225 reg_base + ASS_CLK_GATE, 4, 0, &lock); in exynos_audss_clk_probe() 232 reg_base + ASS_CLK_GATE, 5, 0, &lock); in exynos_audss_clk_probe() [all …]
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H A D | clk-exynos-arm64.c | 52 void __iomem *reg_base; in exynos_arm64_init_clocks() local 55 reg_base = of_iomap(np, 0); in exynos_arm64_init_clocks() 56 if (!reg_base) in exynos_arm64_init_clocks() 60 void __iomem *reg = reg_base + reg_offs[i]; in exynos_arm64_init_clocks() 73 iounmap(reg_base); in exynos_arm64_init_clocks() 202 void __iomem *reg_base; in exynos_arm64_register_cmu_pm() local 229 reg_base = devm_platform_ioremap_resource(pdev, 0); in exynos_arm64_register_cmu_pm() 230 if (IS_ERR(reg_base)) in exynos_arm64_register_cmu_pm() 231 return PTR_ERR(reg_base); in exynos_arm64_register_cmu_pm() 257 samsung_clk_save(data->ctx->reg_base, data->clk_save, in exynos_arm64_cmu_suspend() [all …]
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/openbmc/linux/drivers/fpga/ |
H A D | altera-pr-ip-core.c | 29 void __iomem *reg_base; member 39 val = readl(priv->reg_base + ALT_PR_CSR_OFST); in alt_pr_fpga_state() 90 val = readl(priv->reg_base + ALT_PR_CSR_OFST); in alt_pr_fpga_write_init() 99 writel(val | ALT_PR_CSR_PR_START, priv->reg_base + ALT_PR_CSR_OFST); in alt_pr_fpga_write_init() 116 writel(buffer_32[i++], priv->reg_base); in alt_pr_fpga_write() 123 writel(buffer_32[i++] & 0x00ffffff, priv->reg_base); in alt_pr_fpga_write() 126 writel(buffer_32[i++] & 0x0000ffff, priv->reg_base); in alt_pr_fpga_write() 129 writel(buffer_32[i++] & 0x000000ff, priv->reg_base); in alt_pr_fpga_write() 176 int alt_pr_register(struct device *dev, void __iomem *reg_base) in alt_pr_register() argument 186 priv->reg_base = reg_base; in alt_pr_register() [all …]
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/openbmc/u-boot/drivers/net/pfe_eth/ |
H A D | pfe_mdio.c | 19 void *reg_base = bus->priv; in pfe_write_addr() local 30 writel(reg_data, reg_base + EMAC_MII_DATA_REG); in pfe_write_addr() 45 writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG); in pfe_write_addr() 53 void *reg_base = bus->priv; in pfe_phy_read() local 78 writel(reg_data, reg_base + EMAC_MII_DATA_REG); in pfe_phy_read() 93 writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG); in pfe_phy_read() 98 val = (u16)readl(reg_base + EMAC_MII_DATA_REG); in pfe_phy_read() 108 void *reg_base = bus->priv; in pfe_phy_write() local 133 writel(reg_data, reg_base + EMAC_MII_DATA_REG); in pfe_phy_write() 148 writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG); in pfe_phy_write() [all …]
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/openbmc/linux/drivers/ata/ |
H A D | ahci_sunxi.c | 92 writel(0, reg_base + AHCI_RWCR); in ahci_sunxi_phy_init() 95 sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19)); in ahci_sunxi_phy_init() 96 sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, in ahci_sunxi_phy_init() 99 sunxi_clrsetbits(reg_base + AHCI_PHYCS1R, in ahci_sunxi_phy_init() 102 sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15)); in ahci_sunxi_phy_init() 103 sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19)); in ahci_sunxi_phy_init() 104 sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, in ahci_sunxi_phy_init() 106 sunxi_clrsetbits(reg_base + AHCI_PHYCS2R, in ahci_sunxi_phy_init() 110 sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19)); in ahci_sunxi_phy_init() 125 sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24)); in ahci_sunxi_phy_init() [all …]
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/openbmc/u-boot/arch/arm/mach-uniphier/clk/ |
H A D | pll-base-ld20.c | 31 int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq, in uniphier_ld20_sscpll_init() argument 37 base = ioremap(reg_base, SZ_16); in uniphier_ld20_sscpll_init() 68 int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base) in uniphier_ld20_sscpll_ssc_en() argument 73 base = ioremap(reg_base, SZ_16); in uniphier_ld20_sscpll_ssc_en() 86 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument 91 base = ioremap(reg_base, SZ_16); in uniphier_ld20_sscpll_set_regi() 105 int uniphier_ld20_vpll27_init(unsigned long reg_base) in uniphier_ld20_vpll27_init() argument 110 base = ioremap(reg_base, SZ_16); in uniphier_ld20_vpll27_init() 131 int uniphier_ld20_dspll_init(unsigned long reg_base) in uniphier_ld20_dspll_init() argument 136 base = ioremap(reg_base, SZ_16); in uniphier_ld20_dspll_init()
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H A D | pll.h | 14 int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq, 16 int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base); 17 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi); 18 int uniphier_ld20_vpll27_init(unsigned long reg_base); 19 int uniphier_ld20_dspll_init(unsigned long reg_base);
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/openbmc/linux/drivers/gpio/ |
H A D | gpio-menz127.c | 34 void __iomem *reg_base; member 69 db_en = readl(priv->reg_base + MEN_Z127_DBER); in men_z127_debounce() 79 writel(db_en, priv->reg_base + MEN_Z127_DBER); in men_z127_debounce() 95 od_en = readl(priv->reg_base + MEN_Z127_ODER); in men_z127_set_single_ended() 103 writel(od_en, priv->reg_base + MEN_Z127_ODER); in men_z127_set_single_ended() 150 if (men_z127_gpio->reg_base == NULL) { in men_z127_probe() 158 men_z127_gpio->reg_base + MEN_Z127_PSR, in men_z127_probe() 159 men_z127_gpio->reg_base + MEN_Z127_CTRL, in men_z127_probe() 161 men_z127_gpio->reg_base + MEN_Z127_GPIODR, in men_z127_probe() 179 iounmap(men_z127_gpio->reg_base); in men_z127_probe() [all …]
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/openbmc/linux/drivers/crypto/marvell/octeontx2/ |
H A D | otx2_cptpf_main.c | 24 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_enable_vfpf_mbox_intr() 26 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_enable_vfpf_mbox_intr() 31 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_enable_vfpf_mbox_intr() 38 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_enable_vfpf_mbox_intr() 50 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_disable_vfpf_mbox_intr() 52 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_disable_vfpf_mbox_intr() 55 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_disable_vfpf_mbox_intr() 77 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_enable_vf_flr_me_intrs() 83 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_enable_vf_flr_me_intrs() 166 otx2_cpt_write64(pf->reg_base, BLKADDR_RVUM, 0, in cptpf_flr_wq_handler() [all …]
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/openbmc/linux/drivers/input/keyboard/ |
H A D | nspire-keypad.c | 32 void __iomem *reg_base; member 91 writel(0x3, keypad->reg_base + KEYPAD_INT); in nspire_keypad_irq() 121 writel(val, keypad->reg_base + KEYPAD_SCAN_MODE); in nspire_keypad_open() 124 writel(val, keypad->reg_base + KEYPAD_CNTL); in nspire_keypad_open() 138 writel(0, keypad->reg_base + KEYPAD_INTMSK); in nspire_keypad_close() 140 writel(~0, keypad->reg_base + KEYPAD_INT); in nspire_keypad_close() 190 if (IS_ERR(keypad->reg_base)) in nspire_keypad_probe() 191 return PTR_ERR(keypad->reg_base); in nspire_keypad_probe() 206 writel(0, keypad->reg_base + KEYPAD_INTMSK); in nspire_keypad_probe() 208 writel(~0, keypad->reg_base + KEYPAD_INT); in nspire_keypad_probe() [all …]
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/openbmc/linux/arch/sparc/kernel/ |
H A D | sbus.c | 224 imap += reg_base; in sbus_build_irq() 239 iclr = reg_base + SYSIO_ICLR_SLOT0; in sbus_build_irq() 242 iclr = reg_base + SYSIO_ICLR_SLOT1; in sbus_build_irq() 245 iclr = reg_base + SYSIO_ICLR_SLOT2; in sbus_build_irq() 249 iclr = reg_base + SYSIO_ICLR_SLOT3; in sbus_build_irq() 281 afsr_reg = reg_base + SYSIO_UE_AFSR; in sysio_ue_handler() 282 afar_reg = reg_base + SYSIO_UE_AFAR; in sysio_ue_handler() 355 afsr_reg = reg_base + SYSIO_CE_AFSR; in sysio_ce_handler() 356 afar_reg = reg_base + SYSIO_CE_AFAR; in sysio_ce_handler() 533 reg_base + ECC_CONTROL); in sysio_register_error_handlers() [all …]
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/openbmc/linux/drivers/watchdog/ |
H A D | meson_gxbb_wdt.c | 42 void __iomem *reg_base; member 56 data->reg_base + GXBB_WDT_CTRL_REG); in meson_gxbb_wdt_start() 66 data->reg_base + GXBB_WDT_CTRL_REG); in meson_gxbb_wdt_stop() 75 writel(0, data->reg_base + GXBB_WDT_RSET_REG); in meson_gxbb_wdt_ping() 93 writel(tcnt, data->reg_base + GXBB_WDT_TCNT_REG); in meson_gxbb_wdt_set_timeout() 103 reg = readl(data->reg_base + GXBB_WDT_TCNT_REG); in meson_gxbb_wdt_get_timeleft() 172 data->reg_base = devm_platform_ioremap_resource(pdev, 0); in meson_gxbb_wdt_probe() 173 if (IS_ERR(data->reg_base)) in meson_gxbb_wdt_probe() 174 return PTR_ERR(data->reg_base); in meson_gxbb_wdt_probe() 194 ctrl_reg = readl(data->reg_base + GXBB_WDT_CTRL_REG) & in meson_gxbb_wdt_probe() [all …]
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/openbmc/linux/drivers/char/hw_random/ |
H A D | cn10k-rng.c | 31 void __iomem *reg_base; member 84 if (!rng->reg_base) in check_rng_health() 87 status = readq(rng->reg_base + RNM_PF_EBG_HEALTH); in check_rng_health() 110 *value = readq(rng->reg_base + RNM_PF_TRNG_DAT); in cn10k_read_trng() 119 *value = readq(rng->reg_base + RNM_PF_RANDOM); in cn10k_read_trng() 125 upper = readq(rng->reg_base + RNM_PF_RANDOM); in cn10k_read_trng() 126 lower = readq(rng->reg_base + RNM_PF_RANDOM); in cn10k_read_trng() 128 upper = readq(rng->reg_base + RNM_PF_RANDOM); in cn10k_read_trng() 130 lower = readq(rng->reg_base + RNM_PF_RANDOM); in cn10k_read_trng() 189 rng->reg_base = pcim_iomap(pdev, 0, 0); in cn10k_rng_probe() [all …]
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/openbmc/linux/drivers/input/joystick/ |
H A D | n64joy.c | 51 u32 __iomem *reg_base; member 87 writel(value, reg_base + reg); in n64joy_write_reg() 92 return readl(reg_base + reg); in n64joy_read_reg() 95 static void n64joy_wait_si_dma(u32 __iomem *reg_base) in n64joy_wait_si_dma() argument 97 while (n64joy_read_reg(reg_base, SI_STATUS_REG) & in n64joy_wait_si_dma() 111 n64joy_wait_si_dma(priv->reg_base); in n64joy_exec_pif() 119 n64joy_wait_si_dma(priv->reg_base); in n64joy_exec_pif() 124 n64joy_write_reg(priv->reg_base, SI_READ_REG, PIF_RAM); in n64joy_exec_pif() 127 n64joy_wait_si_dma(priv->reg_base); in n64joy_exec_pif() 255 if (IS_ERR(priv->reg_base)) { in n64joy_probe() [all …]
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/openbmc/linux/drivers/clk/rockchip/ |
H A D | clk-pll.c | 34 void __iomem *reg_base; member 218 pll->reg_base + RK3036_PLLCON(0)); in rockchip_rk3036_pll_set_params() 226 pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_set_params() 273 pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_enable() 285 pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_disable() 448 pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_set_params() 455 pll->reg_base + RK3066_PLLCON(0)); in rockchip_rk3066_pll_set_params() 466 pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_set_params() 508 pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_enable() 520 pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_disable() [all …]
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/openbmc/linux/drivers/crypto/cavium/cpt/ |
H A D | cptpf_mbox.c | 12 cpt_write_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 1), in cpt_send_msg_to_vf() 14 cpt_write_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 0), mbx->msg); in cpt_send_msg_to_vf() 31 cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_INTX(0, 0), (1 << vf)); in cpt_clear_mbox_intr() 41 pf_qx_ctl.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf)); in cpt_cfg_qlen_for_vf() 44 cpt_write_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf), pf_qx_ctl.u); in cpt_cfg_qlen_for_vf() 54 pf_qx_ctl.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf)); in cpt_cfg_vq_priority() 56 cpt_write_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf), pf_qx_ctl.u); in cpt_cfg_vq_priority() 77 pf_qx_ctl.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, q)); in cpt_bind_vq_to_grp() 79 cpt_write_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, q), pf_qx_ctl.u); in cpt_bind_vq_to_grp() 96 mbx.msg = cpt_read_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 0)); in cpt_handle_mbox_intr() [all …]
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H A D | cptvf_main.c | 375 vqx_dbell.u = cpt_read_csr64(cptvf->reg_base, in cptvf_write_vq_doorbell() 395 vqx_dwait.u = cpt_read_csr64(cptvf->reg_base, in cptvf_write_vq_done_numwait() 406 vqx_dwait.u = cpt_read_csr64(cptvf->reg_base, in cptvf_write_vq_done_timewait() 417 vqx_misc_ena.u = cpt_read_csr64(cptvf->reg_base, in cptvf_enable_swerr_interrupts() 429 vqx_misc_ena.u = cpt_read_csr64(cptvf->reg_base, in cptvf_enable_mbox_interrupts() 441 vqx_done_ena.u = cpt_read_csr64(cptvf->reg_base, in cptvf_enable_done_interrupts() 453 vqx_misc_int.u = cpt_read_csr64(cptvf->reg_base, in cptvf_clear_dovf_intr() 465 vqx_misc_int.u = cpt_read_csr64(cptvf->reg_base, in cptvf_clear_irde_intr() 481 cpt_write_csr64(cptvf->reg_base, in cptvf_clear_nwrp_intr() 694 cptvf->reg_base = pcim_iomap(pdev, 0, 0); in cptvf_probe() [all …]
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/openbmc/linux/drivers/crypto/cavium/zip/ |
H A D | zip_main.c | 144 zip_reg_read(zip->reg_base + ZIP_CMD_CTL)); in zip_init_hw() 165 (zip->reg_base + ZIP_QUEX_SBUF_CTL(q))); in zip_init_hw() 197 (zip->reg_base + ZIP_QUEX_SBUF_ADDR(q))); in zip_init_hw() 220 zip_reg_read(zip->reg_base + ZIP_QUE_ENA)); in zip_init_hw() 227 (zip->reg_base + ZIP_QUEX_MAP(q))); in zip_init_hw() 288 if (!zip->reg_base) { in zip_probe() 315 if (zip->reg_base) in zip_probe() 316 iounmap(zip->reg_base); in zip_probe() 344 if (zip->reg_base) { in zip_remove() 346 iounmap(zip->reg_base); in zip_remove() [all …]
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/openbmc/linux/drivers/clk/mvebu/ |
H A D | clk-cpu.c | 38 void __iomem *reg_base; member 54 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); in clk_cpu_recalc_rate() 83 reg = (readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET) in clk_cpu_off_set_rate() 86 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); in clk_cpu_off_set_rate() 90 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET) in clk_cpu_off_set_rate() 92 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); in clk_cpu_off_set_rate() 95 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET) in clk_cpu_off_set_rate() 97 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); in clk_cpu_off_set_rate() 102 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); in clk_cpu_off_set_rate() 143 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); in clk_cpu_on_set_rate() [all …]
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/openbmc/linux/drivers/video/fbdev/ |
H A D | pxa168fb.c | 287 writel(x, fbi->reg_base + LCD_CFG_SCLK_DIV); in set_clock_divider() 297 x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0); in set_dma_control0() 322 writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL0); in set_dma_control0() 425 fbi->reg_base + LCD_SPU_V_H_ACTIVE); in pxa168fb_set_par() 446 fbi->reg_base + LCD_SPU_GRA_HPXL_VLN); in pxa168fb_set_par() 448 fbi->reg_base + LCD_SPU_GZM_HPXL_VLN); in pxa168fb_set_par() 457 fbi->reg_base + LCD_SPU_H_PORCH); in pxa168fb_set_par() 459 fbi->reg_base + LCD_SPU_V_PORCH); in pxa168fb_set_par() 537 fbi->reg_base + SPU_IRQ_ISR); in pxa168fb_handle_irq() 658 if (fbi->reg_base == NULL) { in pxa168fb_probe() [all …]
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/openbmc/linux/drivers/cpufreq/ |
H A D | apple-soc-cpufreq.c | 65 void __iomem *reg_base; member 112 u64 reg = readq_relaxed(priv->reg_base + APPLE_DVFS_STATUS); in apple_soc_cpufreq_get_rate() 120 u64 reg = readq_relaxed(priv->reg_base + APPLE_DVFS_CMD); in apple_soc_cpufreq_get_rate() 156 writeq_relaxed(reg, priv->reg_base + APPLE_DVFS_CMD); in apple_soc_cpufreq_set_target() 171 void __iomem **reg_base, in apple_soc_cpufreq_find_cluster() argument 191 *reg_base = of_iomap(args.np, 0); in apple_soc_cpufreq_find_cluster() 192 if (!*reg_base) in apple_soc_cpufreq_find_cluster() 208 void __iomem *reg_base; in apple_soc_cpufreq_init() local 271 priv->reg_base = reg_base; in apple_soc_cpufreq_init() 304 iounmap(reg_base); in apple_soc_cpufreq_init() [all …]
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/openbmc/linux/drivers/rtc/ |
H A D | rtc-sunplus.c | 61 void __iomem *reg_base; member 69 *secs = (unsigned long)readl(sp_rtc->reg_base + RTC_TIMER_OUT); in sp_get_seconds() 76 writel((u32)secs, sp_rtc->reg_base + RTC_TIMER_SET); in sp_set_seconds() 107 writel((u32)alarm_time, sp_rtc->reg_base + RTC_ALARM_SET); in sp_rtc_set_alarm() 117 alarm_time = readl(sp_rtc->reg_base + RTC_ALARM_SET); in sp_rtc_read_alarm() 139 sp_rtc->reg_base + RTC_CTRL); in sp_rtc_alarm_irq_enable() 142 0x0, sp_rtc->reg_base + RTC_CTRL); in sp_rtc_alarm_irq_enable() 215 sp_rtc->reg_base + RTC_BATT_CHARGE_CTRL); in sp_rtc_set_trickle_charger() 219 sp_rtc->reg_base + RTC_BATT_CHARGE_CTRL); in sp_rtc_set_trickle_charger() 239 if (IS_ERR(sp_rtc->reg_base)) in sp_rtc_probe() [all …]
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/openbmc/linux/drivers/i2c/busses/ |
H A D | i2c-mv64xxx.c | 128 void __iomem *reg_base; member 215 writel(0, drv_data->reg_base + in mv64xxx_i2c_hw_init() 217 writel(0, drv_data->reg_base + in mv64xxx_i2c_hw_init() 223 drv_data->reg_base + drv_data->reg_offsets.clock); in mv64xxx_i2c_hw_init() 387 drv_data->reg_base + drv_data->reg_offsets.data); in mv64xxx_i2c_do_action() 394 drv_data->reg_base + drv_data->reg_offsets.data); in mv64xxx_i2c_do_action() 462 cause = readl(drv_data->reg_base + in mv64xxx_i2c_intr_offload() 467 status = readl(drv_data->reg_base + in mv64xxx_i2c_intr_offload() 500 writel(0, drv_data->reg_base + in mv64xxx_i2c_intr_offload() 1000 if (IS_ERR(drv_data->reg_base)) in mv64xxx_i2c_probe() [all …]
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