1cfe238e4SDavid Virag // SPDX-License-Identifier: GPL-2.0-only
2cfe238e4SDavid Virag /*
3cfe238e4SDavid Virag * Copyright (C) 2021 Linaro Ltd.
4cfe238e4SDavid Virag * Copyright (C) 2021 Dávid Virág <virag.david003@gmail.com>
5cfe238e4SDavid Virag * Author: Sam Protsenko <semen.protsenko@linaro.org>
6cfe238e4SDavid Virag * Author: Dávid Virág <virag.david003@gmail.com>
7cfe238e4SDavid Virag *
8cfe238e4SDavid Virag * This file contains shared functions used by some arm64 Exynos SoCs,
9cfe238e4SDavid Virag * such as Exynos7885 or Exynos850 to register and init CMUs.
10cfe238e4SDavid Virag */
11cfe238e4SDavid Virag #include <linux/clk.h>
12cfe238e4SDavid Virag #include <linux/of_address.h>
13*a96cbb14SRob Herring #include <linux/of.h>
14*a96cbb14SRob Herring #include <linux/platform_device.h>
15f05dc202SSam Protsenko #include <linux/pm_runtime.h>
16f05dc202SSam Protsenko #include <linux/slab.h>
17cfe238e4SDavid Virag
18cfe238e4SDavid Virag #include "clk-exynos-arm64.h"
19cfe238e4SDavid Virag
20cfe238e4SDavid Virag /* Gate register bits */
21cfe238e4SDavid Virag #define GATE_MANUAL BIT(20)
22cfe238e4SDavid Virag #define GATE_ENABLE_HWACG BIT(28)
23cfe238e4SDavid Virag
24cfe238e4SDavid Virag /* Gate register offsets range */
25cfe238e4SDavid Virag #define GATE_OFF_START 0x2000
26cfe238e4SDavid Virag #define GATE_OFF_END 0x2fff
27cfe238e4SDavid Virag
28f05dc202SSam Protsenko struct exynos_arm64_cmu_data {
29f05dc202SSam Protsenko struct samsung_clk_reg_dump *clk_save;
30f05dc202SSam Protsenko unsigned int nr_clk_save;
31f05dc202SSam Protsenko const struct samsung_clk_reg_dump *clk_suspend;
32f05dc202SSam Protsenko unsigned int nr_clk_suspend;
33f05dc202SSam Protsenko
34f05dc202SSam Protsenko struct clk *clk;
35f05dc202SSam Protsenko struct clk **pclks;
36f05dc202SSam Protsenko int nr_pclks;
37f05dc202SSam Protsenko
38f05dc202SSam Protsenko struct samsung_clk_provider *ctx;
39f05dc202SSam Protsenko };
40f05dc202SSam Protsenko
41cfe238e4SDavid Virag /**
42cfe238e4SDavid Virag * exynos_arm64_init_clocks - Set clocks initial configuration
43cfe238e4SDavid Virag * @np: CMU device tree node with "reg" property (CMU addr)
44cfe238e4SDavid Virag * @reg_offs: Register offsets array for clocks to init
45cfe238e4SDavid Virag * @reg_offs_len: Number of register offsets in reg_offs array
46cfe238e4SDavid Virag *
47cfe238e4SDavid Virag * Set manual control mode for all gate clocks.
48cfe238e4SDavid Virag */
exynos_arm64_init_clocks(struct device_node * np,const unsigned long * reg_offs,size_t reg_offs_len)49cfe238e4SDavid Virag static void __init exynos_arm64_init_clocks(struct device_node *np,
50cfe238e4SDavid Virag const unsigned long *reg_offs, size_t reg_offs_len)
51cfe238e4SDavid Virag {
52cfe238e4SDavid Virag void __iomem *reg_base;
53cfe238e4SDavid Virag size_t i;
54cfe238e4SDavid Virag
55cfe238e4SDavid Virag reg_base = of_iomap(np, 0);
56cfe238e4SDavid Virag if (!reg_base)
57cfe238e4SDavid Virag panic("%s: failed to map registers\n", __func__);
58cfe238e4SDavid Virag
59cfe238e4SDavid Virag for (i = 0; i < reg_offs_len; ++i) {
60cfe238e4SDavid Virag void __iomem *reg = reg_base + reg_offs[i];
61cfe238e4SDavid Virag u32 val;
62cfe238e4SDavid Virag
63cfe238e4SDavid Virag /* Modify only gate clock registers */
64cfe238e4SDavid Virag if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END)
65cfe238e4SDavid Virag continue;
66cfe238e4SDavid Virag
67cfe238e4SDavid Virag val = readl(reg);
68cfe238e4SDavid Virag val |= GATE_MANUAL;
69cfe238e4SDavid Virag val &= ~GATE_ENABLE_HWACG;
70cfe238e4SDavid Virag writel(val, reg);
71cfe238e4SDavid Virag }
72cfe238e4SDavid Virag
73cfe238e4SDavid Virag iounmap(reg_base);
74cfe238e4SDavid Virag }
75cfe238e4SDavid Virag
76cfe238e4SDavid Virag /**
77454e8d29SSam Protsenko * exynos_arm64_enable_bus_clk - Enable parent clock of specified CMU
78454e8d29SSam Protsenko *
79454e8d29SSam Protsenko * @dev: Device object; may be NULL if this function is not being
80454e8d29SSam Protsenko * called from platform driver probe function
81454e8d29SSam Protsenko * @np: CMU device tree node
82454e8d29SSam Protsenko * @cmu: CMU data
83454e8d29SSam Protsenko *
84454e8d29SSam Protsenko * Keep CMU parent clock running (needed for CMU registers access).
85454e8d29SSam Protsenko *
86454e8d29SSam Protsenko * Return: 0 on success or a negative error code on failure.
87454e8d29SSam Protsenko */
exynos_arm64_enable_bus_clk(struct device * dev,struct device_node * np,const struct samsung_cmu_info * cmu)88454e8d29SSam Protsenko static int __init exynos_arm64_enable_bus_clk(struct device *dev,
89454e8d29SSam Protsenko struct device_node *np, const struct samsung_cmu_info *cmu)
90454e8d29SSam Protsenko {
91454e8d29SSam Protsenko struct clk *parent_clk;
92454e8d29SSam Protsenko
93454e8d29SSam Protsenko if (!cmu->clk_name)
94454e8d29SSam Protsenko return 0;
95454e8d29SSam Protsenko
96f05dc202SSam Protsenko if (dev) {
97f05dc202SSam Protsenko struct exynos_arm64_cmu_data *data;
98f05dc202SSam Protsenko
99454e8d29SSam Protsenko parent_clk = clk_get(dev, cmu->clk_name);
100f05dc202SSam Protsenko data = dev_get_drvdata(dev);
101f05dc202SSam Protsenko if (data)
102f05dc202SSam Protsenko data->clk = parent_clk;
103f05dc202SSam Protsenko } else {
104454e8d29SSam Protsenko parent_clk = of_clk_get_by_name(np, cmu->clk_name);
105f05dc202SSam Protsenko }
106454e8d29SSam Protsenko
107454e8d29SSam Protsenko if (IS_ERR(parent_clk))
108454e8d29SSam Protsenko return PTR_ERR(parent_clk);
109454e8d29SSam Protsenko
110454e8d29SSam Protsenko return clk_prepare_enable(parent_clk);
111454e8d29SSam Protsenko }
112454e8d29SSam Protsenko
exynos_arm64_cmu_prepare_pm(struct device * dev,const struct samsung_cmu_info * cmu)113f05dc202SSam Protsenko static int __init exynos_arm64_cmu_prepare_pm(struct device *dev,
114f05dc202SSam Protsenko const struct samsung_cmu_info *cmu)
115f05dc202SSam Protsenko {
116f05dc202SSam Protsenko struct exynos_arm64_cmu_data *data = dev_get_drvdata(dev);
117f05dc202SSam Protsenko int i;
118f05dc202SSam Protsenko
119f05dc202SSam Protsenko data->clk_save = samsung_clk_alloc_reg_dump(cmu->clk_regs,
120f05dc202SSam Protsenko cmu->nr_clk_regs);
121f05dc202SSam Protsenko if (!data->clk_save)
122f05dc202SSam Protsenko return -ENOMEM;
123f05dc202SSam Protsenko
124f05dc202SSam Protsenko data->nr_clk_save = cmu->nr_clk_regs;
125f05dc202SSam Protsenko data->clk_suspend = cmu->suspend_regs;
126f05dc202SSam Protsenko data->nr_clk_suspend = cmu->nr_suspend_regs;
127f05dc202SSam Protsenko data->nr_pclks = of_clk_get_parent_count(dev->of_node);
128f05dc202SSam Protsenko if (!data->nr_pclks)
129f05dc202SSam Protsenko return 0;
130f05dc202SSam Protsenko
131f05dc202SSam Protsenko data->pclks = devm_kcalloc(dev, sizeof(struct clk *), data->nr_pclks,
132f05dc202SSam Protsenko GFP_KERNEL);
133f05dc202SSam Protsenko if (!data->pclks) {
134f05dc202SSam Protsenko kfree(data->clk_save);
135f05dc202SSam Protsenko return -ENOMEM;
136f05dc202SSam Protsenko }
137f05dc202SSam Protsenko
138f05dc202SSam Protsenko for (i = 0; i < data->nr_pclks; i++) {
139f05dc202SSam Protsenko struct clk *clk = of_clk_get(dev->of_node, i);
140f05dc202SSam Protsenko
141f05dc202SSam Protsenko if (IS_ERR(clk)) {
142f05dc202SSam Protsenko kfree(data->clk_save);
143f05dc202SSam Protsenko while (--i >= 0)
144f05dc202SSam Protsenko clk_put(data->pclks[i]);
145f05dc202SSam Protsenko return PTR_ERR(clk);
146f05dc202SSam Protsenko }
147f05dc202SSam Protsenko data->pclks[i] = clk;
148f05dc202SSam Protsenko }
149f05dc202SSam Protsenko
150f05dc202SSam Protsenko return 0;
151f05dc202SSam Protsenko }
152f05dc202SSam Protsenko
153454e8d29SSam Protsenko /**
154cfe238e4SDavid Virag * exynos_arm64_register_cmu - Register specified Exynos CMU domain
155cfe238e4SDavid Virag * @dev: Device object; may be NULL if this function is not being
156cfe238e4SDavid Virag * called from platform driver probe function
157cfe238e4SDavid Virag * @np: CMU device tree node
158cfe238e4SDavid Virag * @cmu: CMU data
159cfe238e4SDavid Virag *
160cfe238e4SDavid Virag * Register specified CMU domain, which includes next steps:
161cfe238e4SDavid Virag *
162cfe238e4SDavid Virag * 1. Enable parent clock of @cmu CMU
163cfe238e4SDavid Virag * 2. Set initial registers configuration for @cmu CMU clocks
164cfe238e4SDavid Virag * 3. Register @cmu CMU clocks using Samsung clock framework API
165cfe238e4SDavid Virag */
exynos_arm64_register_cmu(struct device * dev,struct device_node * np,const struct samsung_cmu_info * cmu)166cfe238e4SDavid Virag void __init exynos_arm64_register_cmu(struct device *dev,
167cfe238e4SDavid Virag struct device_node *np, const struct samsung_cmu_info *cmu)
168cfe238e4SDavid Virag {
169454e8d29SSam Protsenko int err;
170cfe238e4SDavid Virag
171454e8d29SSam Protsenko /*
172454e8d29SSam Protsenko * Try to boot even if the parent clock enablement fails, as it might be
173454e8d29SSam Protsenko * already enabled by bootloader.
174454e8d29SSam Protsenko */
175454e8d29SSam Protsenko err = exynos_arm64_enable_bus_clk(dev, np, cmu);
176454e8d29SSam Protsenko if (err)
177454e8d29SSam Protsenko pr_err("%s: could not enable bus clock %s; err = %d\n",
178454e8d29SSam Protsenko __func__, cmu->clk_name, err);
179cfe238e4SDavid Virag
180cfe238e4SDavid Virag exynos_arm64_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs);
181cfe238e4SDavid Virag samsung_cmu_register_one(np, cmu);
182cfe238e4SDavid Virag }
183f05dc202SSam Protsenko
184f05dc202SSam Protsenko /**
185f05dc202SSam Protsenko * exynos_arm64_register_cmu_pm - Register Exynos CMU domain with PM support
186f05dc202SSam Protsenko *
187f05dc202SSam Protsenko * @pdev: Platform device object
188f05dc202SSam Protsenko * @set_manual: If true, set gate clocks to manual mode
189f05dc202SSam Protsenko *
190f05dc202SSam Protsenko * It's a version of exynos_arm64_register_cmu() with PM support. Should be
191f05dc202SSam Protsenko * called from probe function of platform driver.
192f05dc202SSam Protsenko *
193f05dc202SSam Protsenko * Return: 0 on success, or negative error code on error.
194f05dc202SSam Protsenko */
exynos_arm64_register_cmu_pm(struct platform_device * pdev,bool set_manual)195f05dc202SSam Protsenko int __init exynos_arm64_register_cmu_pm(struct platform_device *pdev,
196f05dc202SSam Protsenko bool set_manual)
197f05dc202SSam Protsenko {
198f05dc202SSam Protsenko const struct samsung_cmu_info *cmu;
199f05dc202SSam Protsenko struct device *dev = &pdev->dev;
200f05dc202SSam Protsenko struct device_node *np = dev->of_node;
201f05dc202SSam Protsenko struct exynos_arm64_cmu_data *data;
202f05dc202SSam Protsenko void __iomem *reg_base;
203f05dc202SSam Protsenko int ret;
204f05dc202SSam Protsenko
205f05dc202SSam Protsenko cmu = of_device_get_match_data(dev);
206f05dc202SSam Protsenko
207f05dc202SSam Protsenko data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
208f05dc202SSam Protsenko if (!data)
209f05dc202SSam Protsenko return -ENOMEM;
210f05dc202SSam Protsenko
211f05dc202SSam Protsenko platform_set_drvdata(pdev, data);
212f05dc202SSam Protsenko
213f05dc202SSam Protsenko ret = exynos_arm64_cmu_prepare_pm(dev, cmu);
214f05dc202SSam Protsenko if (ret)
215f05dc202SSam Protsenko return ret;
216f05dc202SSam Protsenko
217f05dc202SSam Protsenko /*
218f05dc202SSam Protsenko * Try to boot even if the parent clock enablement fails, as it might be
219f05dc202SSam Protsenko * already enabled by bootloader.
220f05dc202SSam Protsenko */
221f05dc202SSam Protsenko ret = exynos_arm64_enable_bus_clk(dev, NULL, cmu);
222f05dc202SSam Protsenko if (ret)
223f05dc202SSam Protsenko dev_err(dev, "%s: could not enable bus clock %s; err = %d\n",
224f05dc202SSam Protsenko __func__, cmu->clk_name, ret);
225f05dc202SSam Protsenko
226f05dc202SSam Protsenko if (set_manual)
227f05dc202SSam Protsenko exynos_arm64_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs);
228f05dc202SSam Protsenko
229f05dc202SSam Protsenko reg_base = devm_platform_ioremap_resource(pdev, 0);
230f05dc202SSam Protsenko if (IS_ERR(reg_base))
231f05dc202SSam Protsenko return PTR_ERR(reg_base);
232f05dc202SSam Protsenko
233f05dc202SSam Protsenko data->ctx = samsung_clk_init(dev, reg_base, cmu->nr_clk_ids);
234f05dc202SSam Protsenko
235f05dc202SSam Protsenko /*
236f05dc202SSam Protsenko * Enable runtime PM here to allow the clock core using runtime PM
237f05dc202SSam Protsenko * for the registered clocks. Additionally, we increase the runtime
238f05dc202SSam Protsenko * PM usage count before registering the clocks, to prevent the
239f05dc202SSam Protsenko * clock core from runtime suspending the device.
240f05dc202SSam Protsenko */
241f05dc202SSam Protsenko pm_runtime_get_noresume(dev);
242f05dc202SSam Protsenko pm_runtime_set_active(dev);
243f05dc202SSam Protsenko pm_runtime_enable(dev);
244f05dc202SSam Protsenko
245f05dc202SSam Protsenko samsung_cmu_register_clocks(data->ctx, cmu);
246f05dc202SSam Protsenko samsung_clk_of_add_provider(dev->of_node, data->ctx);
247f05dc202SSam Protsenko pm_runtime_put_sync(dev);
248f05dc202SSam Protsenko
249f05dc202SSam Protsenko return 0;
250f05dc202SSam Protsenko }
251f05dc202SSam Protsenko
exynos_arm64_cmu_suspend(struct device * dev)252f05dc202SSam Protsenko int exynos_arm64_cmu_suspend(struct device *dev)
253f05dc202SSam Protsenko {
254f05dc202SSam Protsenko struct exynos_arm64_cmu_data *data = dev_get_drvdata(dev);
255f05dc202SSam Protsenko int i;
256f05dc202SSam Protsenko
257f05dc202SSam Protsenko samsung_clk_save(data->ctx->reg_base, data->clk_save,
258f05dc202SSam Protsenko data->nr_clk_save);
259f05dc202SSam Protsenko
260f05dc202SSam Protsenko for (i = 0; i < data->nr_pclks; i++)
261f05dc202SSam Protsenko clk_prepare_enable(data->pclks[i]);
262f05dc202SSam Protsenko
263f05dc202SSam Protsenko /* For suspend some registers have to be set to certain values */
264f05dc202SSam Protsenko samsung_clk_restore(data->ctx->reg_base, data->clk_suspend,
265f05dc202SSam Protsenko data->nr_clk_suspend);
266f05dc202SSam Protsenko
267f05dc202SSam Protsenko for (i = 0; i < data->nr_pclks; i++)
268f05dc202SSam Protsenko clk_disable_unprepare(data->pclks[i]);
269f05dc202SSam Protsenko
270f05dc202SSam Protsenko clk_disable_unprepare(data->clk);
271f05dc202SSam Protsenko
272f05dc202SSam Protsenko return 0;
273f05dc202SSam Protsenko }
274f05dc202SSam Protsenko
exynos_arm64_cmu_resume(struct device * dev)275f05dc202SSam Protsenko int exynos_arm64_cmu_resume(struct device *dev)
276f05dc202SSam Protsenko {
277f05dc202SSam Protsenko struct exynos_arm64_cmu_data *data = dev_get_drvdata(dev);
278f05dc202SSam Protsenko int i;
279f05dc202SSam Protsenko
280f05dc202SSam Protsenko clk_prepare_enable(data->clk);
281f05dc202SSam Protsenko
282f05dc202SSam Protsenko for (i = 0; i < data->nr_pclks; i++)
283f05dc202SSam Protsenko clk_prepare_enable(data->pclks[i]);
284f05dc202SSam Protsenko
285f05dc202SSam Protsenko samsung_clk_restore(data->ctx->reg_base, data->clk_save,
286f05dc202SSam Protsenko data->nr_clk_save);
287f05dc202SSam Protsenko
288f05dc202SSam Protsenko for (i = 0; i < data->nr_pclks; i++)
289f05dc202SSam Protsenko clk_disable_unprepare(data->pclks[i]);
290f05dc202SSam Protsenko
291f05dc202SSam Protsenko return 0;
292f05dc202SSam Protsenko }
293