131fb632bSRamuthevar Vadivel Murugan // SPDX-License-Identifier: GPL-2.0-only
231fb632bSRamuthevar Vadivel Murugan //
331fb632bSRamuthevar Vadivel Murugan // Driver for Cadence QSPI Controller
431fb632bSRamuthevar Vadivel Murugan //
531fb632bSRamuthevar Vadivel Murugan // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
631fb632bSRamuthevar Vadivel Murugan // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
731fb632bSRamuthevar Vadivel Murugan // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
831fb632bSRamuthevar Vadivel Murugan
931fb632bSRamuthevar Vadivel Murugan #include <linux/clk.h>
1031fb632bSRamuthevar Vadivel Murugan #include <linux/completion.h>
1131fb632bSRamuthevar Vadivel Murugan #include <linux/delay.h>
1231fb632bSRamuthevar Vadivel Murugan #include <linux/dma-mapping.h>
1331fb632bSRamuthevar Vadivel Murugan #include <linux/dmaengine.h>
1431fb632bSRamuthevar Vadivel Murugan #include <linux/err.h>
1531fb632bSRamuthevar Vadivel Murugan #include <linux/errno.h>
1609e393e3SSai Krishna Potthuri #include <linux/firmware/xlnx-zynqmp.h>
1731fb632bSRamuthevar Vadivel Murugan #include <linux/interrupt.h>
1831fb632bSRamuthevar Vadivel Murugan #include <linux/io.h>
1931fb632bSRamuthevar Vadivel Murugan #include <linux/iopoll.h>
2031fb632bSRamuthevar Vadivel Murugan #include <linux/jiffies.h>
2131fb632bSRamuthevar Vadivel Murugan #include <linux/kernel.h>
2297e4827dSMatthias Schiffer #include <linux/log2.h>
2331fb632bSRamuthevar Vadivel Murugan #include <linux/module.h>
2431fb632bSRamuthevar Vadivel Murugan #include <linux/of.h>
2531fb632bSRamuthevar Vadivel Murugan #include <linux/platform_device.h>
2631fb632bSRamuthevar Vadivel Murugan #include <linux/pm_runtime.h>
2731fb632bSRamuthevar Vadivel Murugan #include <linux/reset.h>
2831fb632bSRamuthevar Vadivel Murugan #include <linux/sched.h>
2931fb632bSRamuthevar Vadivel Murugan #include <linux/spi/spi.h>
3031fb632bSRamuthevar Vadivel Murugan #include <linux/spi/spi-mem.h>
3131fb632bSRamuthevar Vadivel Murugan #include <linux/timer.h>
3231fb632bSRamuthevar Vadivel Murugan
3331fb632bSRamuthevar Vadivel Murugan #define CQSPI_NAME "cadence-qspi"
3431fb632bSRamuthevar Vadivel Murugan #define CQSPI_MAX_CHIPSELECT 16
3531fb632bSRamuthevar Vadivel Murugan
3631fb632bSRamuthevar Vadivel Murugan /* Quirks */
3731fb632bSRamuthevar Vadivel Murugan #define CQSPI_NEEDS_WR_DELAY BIT(0)
3831fb632bSRamuthevar Vadivel Murugan #define CQSPI_DISABLE_DAC_MODE BIT(1)
391a6f854fSSai Krishna Potthuri #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2)
4098d948ebSDinh Nguyen #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3)
419ee5b6d5SNiravkumar L Rabara #define CQSPI_SLOW_SRAM BIT(4)
42f5c2f9f9SBrad Larson #define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5)
4331fb632bSRamuthevar Vadivel Murugan
4431fb632bSRamuthevar Vadivel Murugan /* Capabilities */
4531fb632bSRamuthevar Vadivel Murugan #define CQSPI_SUPPORTS_OCTAL BIT(0)
4631fb632bSRamuthevar Vadivel Murugan
4728ac902aSMatthias Schiffer #define CQSPI_OP_WIDTH(part) ((part).nbytes ? ilog2((part).buswidth) : 0)
4828ac902aSMatthias Schiffer
4933f1ef6dSWilliam Qiu enum {
5033f1ef6dSWilliam Qiu CLK_QSPI_APB = 0,
5133f1ef6dSWilliam Qiu CLK_QSPI_AHB,
5233f1ef6dSWilliam Qiu CLK_QSPI_NUM,
5333f1ef6dSWilliam Qiu };
5433f1ef6dSWilliam Qiu
5531fb632bSRamuthevar Vadivel Murugan struct cqspi_st;
5631fb632bSRamuthevar Vadivel Murugan
5731fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata {
5831fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi;
5931fb632bSRamuthevar Vadivel Murugan u32 clk_rate;
6031fb632bSRamuthevar Vadivel Murugan u32 read_delay;
6131fb632bSRamuthevar Vadivel Murugan u32 tshsl_ns;
6231fb632bSRamuthevar Vadivel Murugan u32 tsd2d_ns;
6331fb632bSRamuthevar Vadivel Murugan u32 tchsh_ns;
6431fb632bSRamuthevar Vadivel Murugan u32 tslch_ns;
6531fb632bSRamuthevar Vadivel Murugan u8 cs;
6631fb632bSRamuthevar Vadivel Murugan };
6731fb632bSRamuthevar Vadivel Murugan
6831fb632bSRamuthevar Vadivel Murugan struct cqspi_st {
6931fb632bSRamuthevar Vadivel Murugan struct platform_device *pdev;
701c75d749SYang Yingliang struct spi_controller *host;
7131fb632bSRamuthevar Vadivel Murugan struct clk *clk;
7233f1ef6dSWilliam Qiu struct clk *clks[CLK_QSPI_NUM];
7331fb632bSRamuthevar Vadivel Murugan unsigned int sclk;
7431fb632bSRamuthevar Vadivel Murugan
7531fb632bSRamuthevar Vadivel Murugan void __iomem *iobase;
7631fb632bSRamuthevar Vadivel Murugan void __iomem *ahb_base;
7731fb632bSRamuthevar Vadivel Murugan resource_size_t ahb_size;
7831fb632bSRamuthevar Vadivel Murugan struct completion transfer_complete;
7931fb632bSRamuthevar Vadivel Murugan
8031fb632bSRamuthevar Vadivel Murugan struct dma_chan *rx_chan;
8131fb632bSRamuthevar Vadivel Murugan struct completion rx_dma_complete;
8231fb632bSRamuthevar Vadivel Murugan dma_addr_t mmap_phys_base;
8331fb632bSRamuthevar Vadivel Murugan
8431fb632bSRamuthevar Vadivel Murugan int current_cs;
8531fb632bSRamuthevar Vadivel Murugan unsigned long master_ref_clk_hz;
8631fb632bSRamuthevar Vadivel Murugan bool is_decoded_cs;
8731fb632bSRamuthevar Vadivel Murugan u32 fifo_depth;
8831fb632bSRamuthevar Vadivel Murugan u32 fifo_width;
89b436fb7dSRamuthevar Vadivel Murugan u32 num_chipselect;
9031fb632bSRamuthevar Vadivel Murugan bool rclk_en;
9131fb632bSRamuthevar Vadivel Murugan u32 trigger_address;
9231fb632bSRamuthevar Vadivel Murugan u32 wr_delay;
9331fb632bSRamuthevar Vadivel Murugan bool use_direct_mode;
94e8c51b16SDhruva Gole bool use_direct_mode_wr;
9531fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
961a6f854fSSai Krishna Potthuri bool use_dma_read;
9709e393e3SSai Krishna Potthuri u32 pd_dev_id;
9898d948ebSDinh Nguyen bool wr_completion;
999ee5b6d5SNiravkumar L Rabara bool slow_sram;
100f5c2f9f9SBrad Larson bool apb_ahb_hazard;
10133f1ef6dSWilliam Qiu
10233f1ef6dSWilliam Qiu bool is_jh7110; /* Flag for StarFive JH7110 SoC */
10331fb632bSRamuthevar Vadivel Murugan };
10431fb632bSRamuthevar Vadivel Murugan
10531fb632bSRamuthevar Vadivel Murugan struct cqspi_driver_platdata {
10631fb632bSRamuthevar Vadivel Murugan u32 hwcaps_mask;
10731fb632bSRamuthevar Vadivel Murugan u8 quirks;
1081a6f854fSSai Krishna Potthuri int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata,
1091a6f854fSSai Krishna Potthuri u_char *rxbuf, loff_t from_addr, size_t n_rx);
1101a6f854fSSai Krishna Potthuri u32 (*get_dma_status)(struct cqspi_st *cqspi);
11133f1ef6dSWilliam Qiu int (*jh7110_clk_init)(struct platform_device *pdev,
11233f1ef6dSWilliam Qiu struct cqspi_st *cqspi);
11331fb632bSRamuthevar Vadivel Murugan };
11431fb632bSRamuthevar Vadivel Murugan
11531fb632bSRamuthevar Vadivel Murugan /* Operation timeout value */
11631fb632bSRamuthevar Vadivel Murugan #define CQSPI_TIMEOUT_MS 500
11731fb632bSRamuthevar Vadivel Murugan #define CQSPI_READ_TIMEOUT_MS 10
11831fb632bSRamuthevar Vadivel Murugan
11931fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_CLKS_PER_BYTE 8
12031fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_BYTES_MAX 4
12131fb632bSRamuthevar Vadivel Murugan #define CQSPI_DUMMY_CLKS_MAX 31
12231fb632bSRamuthevar Vadivel Murugan
12331fb632bSRamuthevar Vadivel Murugan #define CQSPI_STIG_DATA_LEN_MAX 8
12431fb632bSRamuthevar Vadivel Murugan
12531fb632bSRamuthevar Vadivel Murugan /* Register map */
12631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG 0x00
12731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0)
12831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7)
12931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9)
13031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
13131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_DMA_MASK BIT(15)
13231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_BAUD_LSB 19
133f453f293SPratyush Yadav #define CQSPI_REG_CONFIG_DTR_PROTO BIT(24)
134f453f293SPratyush Yadav #define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30)
13531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_IDLE_LSB 31
13631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
13731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CONFIG_BAUD_MASK 0xF
13831fb632bSRamuthevar Vadivel Murugan
13931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR 0x04
14031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
14131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8
14231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12
14331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
14431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
14531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
14631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
14731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
14831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
14931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
15031fb632bSRamuthevar Vadivel Murugan
15131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR 0x08
15231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
15331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12
15431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16
15531fb632bSRamuthevar Vadivel Murugan
15631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY 0x0C
15731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSLCH_LSB 0
15831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TCHSH_LSB 8
15931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSD2D_LSB 16
16031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSHSL_LSB 24
16131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
16231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
16331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
16431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
16531fb632bSRamuthevar Vadivel Murugan
16631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE 0x10
16731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0
16831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_DELAY_LSB 1
16931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF
17031fb632bSRamuthevar Vadivel Murugan
17131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE 0x14
17231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_ADDRESS_LSB 0
17331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_PAGE_LSB 4
17431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_BLOCK_LSB 16
17531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
17631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
17731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
17831fb632bSRamuthevar Vadivel Murugan
17931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SRAMPARTITION 0x18
18031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTTRIGGER 0x1C
18131fb632bSRamuthevar Vadivel Murugan
18231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA 0x20
18331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_SINGLE_LSB 0
18431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_BURST_LSB 8
18531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_SINGLE_MASK 0xFF
18631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_DMA_BURST_MASK 0xFF
18731fb632bSRamuthevar Vadivel Murugan
18831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_REMAP 0x24
18931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_MODE_BIT 0x28
19031fb632bSRamuthevar Vadivel Murugan
19131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL 0x2C
19231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
19331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
19431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
19531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
19631fb632bSRamuthevar Vadivel Murugan
197f453f293SPratyush Yadav #define CQSPI_REG_WR_COMPLETION_CTRL 0x38
198f453f293SPratyush Yadav #define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14)
199f453f293SPratyush Yadav
20031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQSTATUS 0x40
20131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQMASK 0x44
20231fb632bSRamuthevar Vadivel Murugan
20331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD 0x60
20431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0)
20531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1)
20631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5)
20731fb632bSRamuthevar Vadivel Murugan
20831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDWATERMARK 0x64
20931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
21031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTRDBYTES 0x6C
21131fb632bSRamuthevar Vadivel Murugan
21231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL 0x90
21331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0)
21431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1)
215888d517bSPratyush Yadav #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7
21631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
21731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
21831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
21931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19
22031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
22131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
22231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
22331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
22431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
22531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
226888d517bSPratyush Yadav #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F
22731fb632bSRamuthevar Vadivel Murugan
22831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR 0x70
22931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0)
23031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1)
23131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5)
23231fb632bSRamuthevar Vadivel Murugan
23331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRWATERMARK 0x74
23431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
23531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_INDIRECTWRBYTES 0x7C
23631fb632bSRamuthevar Vadivel Murugan
2371a6f854fSSai Krishna Potthuri #define CQSPI_REG_INDTRIG_ADDRRANGE 0x80
2381a6f854fSSai Krishna Potthuri
23931fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDADDRESS 0x94
24031fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDREADDATALOWER 0xA0
24131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDREADDATAUPPER 0xA4
24231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDWRITEDATALOWER 0xA8
24331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
24431fb632bSRamuthevar Vadivel Murugan
245f453f293SPratyush Yadav #define CQSPI_REG_POLLING_STATUS 0xB0
246f453f293SPratyush Yadav #define CQSPI_REG_POLLING_STATUS_DUMMY_LSB 16
247f453f293SPratyush Yadav
248f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_LOWER 0xE0
249f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_READ_LSB 24
250f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_WRITE_LSB 16
251f453f293SPratyush Yadav #define CQSPI_REG_OP_EXT_STIG_LSB 0
252f453f293SPratyush Yadav
2531a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_SRC_ADDR 0x1000
2541a6f854fSSai Krishna Potthuri
2551a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_ADDR 0x1800
2561a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_SIZE 0x1804
2571a6f854fSSai Krishna Potthuri
2581a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_CTRL 0x180C
2591a6f854fSSai Krishna Potthuri
2601a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_I_STS 0x1814
2611a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_I_EN 0x1818
2621a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_I_DIS 0x181C
2631a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_DONE_MASK BIT(1)
2641a6f854fSSai Krishna Potthuri
2651a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB 0x1828
2661a6f854fSSai Krishna Potthuri
2671a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL 0xF43FFA00
2681a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL 0x6
2691a6f854fSSai Krishna Potthuri
27031fb632bSRamuthevar Vadivel Murugan /* Interrupt status bits */
27131fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_MODE_ERR BIT(0)
27231fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_UNDERFLOW BIT(1)
27331fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_COMP BIT(2)
27431fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3)
27531fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4)
27631fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5)
27731fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_WATERMARK BIT(6)
27831fb632bSRamuthevar Vadivel Murugan #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12)
27931fb632bSRamuthevar Vadivel Murugan
28031fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \
28131fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_IND_SRAM_FULL | \
28231fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_IND_COMP)
28331fb632bSRamuthevar Vadivel Murugan
28431fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \
28531fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_WATERMARK | \
28631fb632bSRamuthevar Vadivel Murugan CQSPI_REG_IRQ_UNDERFLOW)
28731fb632bSRamuthevar Vadivel Murugan
28831fb632bSRamuthevar Vadivel Murugan #define CQSPI_IRQ_STATUS_MASK 0x1FFFF
2891a6f854fSSai Krishna Potthuri #define CQSPI_DMA_UNALIGN 0x3
2901a6f854fSSai Krishna Potthuri
2911a6f854fSSai Krishna Potthuri #define CQSPI_REG_VERSAL_DMA_VAL 0x602
29231fb632bSRamuthevar Vadivel Murugan
cqspi_wait_for_bit(void __iomem * reg,const u32 mask,bool clr)29331fb632bSRamuthevar Vadivel Murugan static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr)
29431fb632bSRamuthevar Vadivel Murugan {
29531fb632bSRamuthevar Vadivel Murugan u32 val;
29631fb632bSRamuthevar Vadivel Murugan
29731fb632bSRamuthevar Vadivel Murugan return readl_relaxed_poll_timeout(reg, val,
29831fb632bSRamuthevar Vadivel Murugan (((clr ? ~val : val) & mask) == mask),
29931fb632bSRamuthevar Vadivel Murugan 10, CQSPI_TIMEOUT_MS * 1000);
30031fb632bSRamuthevar Vadivel Murugan }
30131fb632bSRamuthevar Vadivel Murugan
cqspi_is_idle(struct cqspi_st * cqspi)30231fb632bSRamuthevar Vadivel Murugan static bool cqspi_is_idle(struct cqspi_st *cqspi)
30331fb632bSRamuthevar Vadivel Murugan {
30431fb632bSRamuthevar Vadivel Murugan u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
30531fb632bSRamuthevar Vadivel Murugan
30631890269SJay Fang return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB);
30731fb632bSRamuthevar Vadivel Murugan }
30831fb632bSRamuthevar Vadivel Murugan
cqspi_get_rd_sram_level(struct cqspi_st * cqspi)30931fb632bSRamuthevar Vadivel Murugan static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
31031fb632bSRamuthevar Vadivel Murugan {
31131fb632bSRamuthevar Vadivel Murugan u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
31231fb632bSRamuthevar Vadivel Murugan
31331fb632bSRamuthevar Vadivel Murugan reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
31431fb632bSRamuthevar Vadivel Murugan return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
31531fb632bSRamuthevar Vadivel Murugan }
31631fb632bSRamuthevar Vadivel Murugan
cqspi_get_versal_dma_status(struct cqspi_st * cqspi)3171a6f854fSSai Krishna Potthuri static u32 cqspi_get_versal_dma_status(struct cqspi_st *cqspi)
3181a6f854fSSai Krishna Potthuri {
3191a6f854fSSai Krishna Potthuri u32 dma_status;
3201a6f854fSSai Krishna Potthuri
3211a6f854fSSai Krishna Potthuri dma_status = readl(cqspi->iobase +
3221a6f854fSSai Krishna Potthuri CQSPI_REG_VERSAL_DMA_DST_I_STS);
3231a6f854fSSai Krishna Potthuri writel(dma_status, cqspi->iobase +
3241a6f854fSSai Krishna Potthuri CQSPI_REG_VERSAL_DMA_DST_I_STS);
3251a6f854fSSai Krishna Potthuri
3261a6f854fSSai Krishna Potthuri return dma_status & CQSPI_REG_VERSAL_DMA_DST_DONE_MASK;
3271a6f854fSSai Krishna Potthuri }
3281a6f854fSSai Krishna Potthuri
cqspi_irq_handler(int this_irq,void * dev)32931fb632bSRamuthevar Vadivel Murugan static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
33031fb632bSRamuthevar Vadivel Murugan {
33131fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev;
33231fb632bSRamuthevar Vadivel Murugan unsigned int irq_status;
3331a6f854fSSai Krishna Potthuri struct device *device = &cqspi->pdev->dev;
3341a6f854fSSai Krishna Potthuri const struct cqspi_driver_platdata *ddata;
3351a6f854fSSai Krishna Potthuri
3361a6f854fSSai Krishna Potthuri ddata = of_device_get_match_data(device);
33731fb632bSRamuthevar Vadivel Murugan
33831fb632bSRamuthevar Vadivel Murugan /* Read interrupt status */
33931fb632bSRamuthevar Vadivel Murugan irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
34031fb632bSRamuthevar Vadivel Murugan
34131fb632bSRamuthevar Vadivel Murugan /* Clear interrupt */
34231fb632bSRamuthevar Vadivel Murugan writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
34331fb632bSRamuthevar Vadivel Murugan
3441a6f854fSSai Krishna Potthuri if (cqspi->use_dma_read && ddata && ddata->get_dma_status) {
3451a6f854fSSai Krishna Potthuri if (ddata->get_dma_status(cqspi)) {
3461a6f854fSSai Krishna Potthuri complete(&cqspi->transfer_complete);
3471a6f854fSSai Krishna Potthuri return IRQ_HANDLED;
3481a6f854fSSai Krishna Potthuri }
3491a6f854fSSai Krishna Potthuri }
3501a6f854fSSai Krishna Potthuri
3519ee5b6d5SNiravkumar L Rabara else if (!cqspi->slow_sram)
35231fb632bSRamuthevar Vadivel Murugan irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
3539ee5b6d5SNiravkumar L Rabara else
3549ee5b6d5SNiravkumar L Rabara irq_status &= CQSPI_REG_IRQ_WATERMARK | CQSPI_IRQ_MASK_WR;
35531fb632bSRamuthevar Vadivel Murugan
35631fb632bSRamuthevar Vadivel Murugan if (irq_status)
35731fb632bSRamuthevar Vadivel Murugan complete(&cqspi->transfer_complete);
35831fb632bSRamuthevar Vadivel Murugan
35931fb632bSRamuthevar Vadivel Murugan return IRQ_HANDLED;
36031fb632bSRamuthevar Vadivel Murugan }
36131fb632bSRamuthevar Vadivel Murugan
cqspi_calc_rdreg(const struct spi_mem_op * op)36228ac902aSMatthias Schiffer static unsigned int cqspi_calc_rdreg(const struct spi_mem_op *op)
36331fb632bSRamuthevar Vadivel Murugan {
36431fb632bSRamuthevar Vadivel Murugan u32 rdreg = 0;
36531fb632bSRamuthevar Vadivel Murugan
36628ac902aSMatthias Schiffer rdreg |= CQSPI_OP_WIDTH(op->cmd) << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
36728ac902aSMatthias Schiffer rdreg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
36828ac902aSMatthias Schiffer rdreg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
36931fb632bSRamuthevar Vadivel Murugan
37031fb632bSRamuthevar Vadivel Murugan return rdreg;
37131fb632bSRamuthevar Vadivel Murugan }
37231fb632bSRamuthevar Vadivel Murugan
cqspi_calc_dummy(const struct spi_mem_op * op)37328ac902aSMatthias Schiffer static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op)
374888d517bSPratyush Yadav {
3750ccfd1baSYoshitaka Ikeda unsigned int dummy_clk;
376888d517bSPratyush Yadav
3770e85ee89SYoshitaka Ikeda if (!op->dummy.nbytes)
3780e85ee89SYoshitaka Ikeda return 0;
3790e85ee89SYoshitaka Ikeda
3807512eaf5SPratyush Yadav dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth);
38128ac902aSMatthias Schiffer if (op->cmd.dtr)
382f453f293SPratyush Yadav dummy_clk /= 2;
383888d517bSPratyush Yadav
384888d517bSPratyush Yadav return dummy_clk;
385888d517bSPratyush Yadav }
386888d517bSPratyush Yadav
cqspi_wait_idle(struct cqspi_st * cqspi)38731fb632bSRamuthevar Vadivel Murugan static int cqspi_wait_idle(struct cqspi_st *cqspi)
38831fb632bSRamuthevar Vadivel Murugan {
38931fb632bSRamuthevar Vadivel Murugan const unsigned int poll_idle_retry = 3;
39031fb632bSRamuthevar Vadivel Murugan unsigned int count = 0;
39131fb632bSRamuthevar Vadivel Murugan unsigned long timeout;
39231fb632bSRamuthevar Vadivel Murugan
39331fb632bSRamuthevar Vadivel Murugan timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
39431fb632bSRamuthevar Vadivel Murugan while (1) {
39531fb632bSRamuthevar Vadivel Murugan /*
39631fb632bSRamuthevar Vadivel Murugan * Read few times in succession to ensure the controller
39731fb632bSRamuthevar Vadivel Murugan * is indeed idle, that is, the bit does not transition
39831fb632bSRamuthevar Vadivel Murugan * low again.
39931fb632bSRamuthevar Vadivel Murugan */
40031fb632bSRamuthevar Vadivel Murugan if (cqspi_is_idle(cqspi))
40131fb632bSRamuthevar Vadivel Murugan count++;
40231fb632bSRamuthevar Vadivel Murugan else
40331fb632bSRamuthevar Vadivel Murugan count = 0;
40431fb632bSRamuthevar Vadivel Murugan
40531fb632bSRamuthevar Vadivel Murugan if (count >= poll_idle_retry)
40631fb632bSRamuthevar Vadivel Murugan return 0;
40731fb632bSRamuthevar Vadivel Murugan
40831fb632bSRamuthevar Vadivel Murugan if (time_after(jiffies, timeout)) {
40931fb632bSRamuthevar Vadivel Murugan /* Timeout, in busy mode. */
41031fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev,
41131fb632bSRamuthevar Vadivel Murugan "QSPI is still busy after %dms timeout.\n",
41231fb632bSRamuthevar Vadivel Murugan CQSPI_TIMEOUT_MS);
41331fb632bSRamuthevar Vadivel Murugan return -ETIMEDOUT;
41431fb632bSRamuthevar Vadivel Murugan }
41531fb632bSRamuthevar Vadivel Murugan
41631fb632bSRamuthevar Vadivel Murugan cpu_relax();
41731fb632bSRamuthevar Vadivel Murugan }
41831fb632bSRamuthevar Vadivel Murugan }
41931fb632bSRamuthevar Vadivel Murugan
cqspi_exec_flash_cmd(struct cqspi_st * cqspi,unsigned int reg)42031fb632bSRamuthevar Vadivel Murugan static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
42131fb632bSRamuthevar Vadivel Murugan {
42231fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase;
42331fb632bSRamuthevar Vadivel Murugan int ret;
42431fb632bSRamuthevar Vadivel Murugan
42531fb632bSRamuthevar Vadivel Murugan /* Write the CMDCTRL without start execution. */
42631fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CMDCTRL);
42731fb632bSRamuthevar Vadivel Murugan /* Start execute */
42831fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
42931fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CMDCTRL);
43031fb632bSRamuthevar Vadivel Murugan
43131fb632bSRamuthevar Vadivel Murugan /* Polling for completion. */
43231fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
43331fb632bSRamuthevar Vadivel Murugan CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
43431fb632bSRamuthevar Vadivel Murugan if (ret) {
43531fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev,
43631fb632bSRamuthevar Vadivel Murugan "Flash command execution timed out.\n");
43731fb632bSRamuthevar Vadivel Murugan return ret;
43831fb632bSRamuthevar Vadivel Murugan }
43931fb632bSRamuthevar Vadivel Murugan
44031fb632bSRamuthevar Vadivel Murugan /* Polling QSPI idle status. */
44131fb632bSRamuthevar Vadivel Murugan return cqspi_wait_idle(cqspi);
44231fb632bSRamuthevar Vadivel Murugan }
44331fb632bSRamuthevar Vadivel Murugan
cqspi_setup_opcode_ext(struct cqspi_flash_pdata * f_pdata,const struct spi_mem_op * op,unsigned int shift)444f453f293SPratyush Yadav static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata,
445f453f293SPratyush Yadav const struct spi_mem_op *op,
446f453f293SPratyush Yadav unsigned int shift)
447f453f293SPratyush Yadav {
448f453f293SPratyush Yadav struct cqspi_st *cqspi = f_pdata->cqspi;
449f453f293SPratyush Yadav void __iomem *reg_base = cqspi->iobase;
450f453f293SPratyush Yadav unsigned int reg;
451f453f293SPratyush Yadav u8 ext;
452f453f293SPratyush Yadav
453f453f293SPratyush Yadav if (op->cmd.nbytes != 2)
454f453f293SPratyush Yadav return -EINVAL;
455f453f293SPratyush Yadav
456f453f293SPratyush Yadav /* Opcode extension is the LSB. */
457f453f293SPratyush Yadav ext = op->cmd.opcode & 0xff;
458f453f293SPratyush Yadav
459f453f293SPratyush Yadav reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER);
460f453f293SPratyush Yadav reg &= ~(0xff << shift);
461f453f293SPratyush Yadav reg |= ext << shift;
462f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER);
463f453f293SPratyush Yadav
464f453f293SPratyush Yadav return 0;
465f453f293SPratyush Yadav }
466f453f293SPratyush Yadav
cqspi_enable_dtr(struct cqspi_flash_pdata * f_pdata,const struct spi_mem_op * op,unsigned int shift)467f453f293SPratyush Yadav static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata,
46828ac902aSMatthias Schiffer const struct spi_mem_op *op, unsigned int shift)
469f453f293SPratyush Yadav {
470f453f293SPratyush Yadav struct cqspi_st *cqspi = f_pdata->cqspi;
471f453f293SPratyush Yadav void __iomem *reg_base = cqspi->iobase;
472f453f293SPratyush Yadav unsigned int reg;
473f453f293SPratyush Yadav int ret;
474f453f293SPratyush Yadav
475f453f293SPratyush Yadav reg = readl(reg_base + CQSPI_REG_CONFIG);
476f453f293SPratyush Yadav
477f453f293SPratyush Yadav /*
478f453f293SPratyush Yadav * We enable dual byte opcode here. The callers have to set up the
479f453f293SPratyush Yadav * extension opcode based on which type of operation it is.
480f453f293SPratyush Yadav */
48128ac902aSMatthias Schiffer if (op->cmd.dtr) {
482f453f293SPratyush Yadav reg |= CQSPI_REG_CONFIG_DTR_PROTO;
483f453f293SPratyush Yadav reg |= CQSPI_REG_CONFIG_DUAL_OPCODE;
484f453f293SPratyush Yadav
485f453f293SPratyush Yadav /* Set up command opcode extension. */
486f453f293SPratyush Yadav ret = cqspi_setup_opcode_ext(f_pdata, op, shift);
487f453f293SPratyush Yadav if (ret)
488f453f293SPratyush Yadav return ret;
489f453f293SPratyush Yadav } else {
490f453f293SPratyush Yadav reg &= ~CQSPI_REG_CONFIG_DTR_PROTO;
491f453f293SPratyush Yadav reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE;
492f453f293SPratyush Yadav }
493f453f293SPratyush Yadav
494f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_CONFIG);
495f453f293SPratyush Yadav
496f453f293SPratyush Yadav return cqspi_wait_idle(cqspi);
497f453f293SPratyush Yadav }
498f453f293SPratyush Yadav
cqspi_command_read(struct cqspi_flash_pdata * f_pdata,const struct spi_mem_op * op)49931fb632bSRamuthevar Vadivel Murugan static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata,
50031fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op)
50131fb632bSRamuthevar Vadivel Murugan {
50231fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi;
50331fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase;
50431fb632bSRamuthevar Vadivel Murugan u8 *rxbuf = op->data.buf.in;
505f453f293SPratyush Yadav u8 opcode;
50631fb632bSRamuthevar Vadivel Murugan size_t n_rx = op->data.nbytes;
50731fb632bSRamuthevar Vadivel Murugan unsigned int rdreg;
50831fb632bSRamuthevar Vadivel Murugan unsigned int reg;
509888d517bSPratyush Yadav unsigned int dummy_clk;
51031fb632bSRamuthevar Vadivel Murugan size_t read_len;
51131fb632bSRamuthevar Vadivel Murugan int status;
51231fb632bSRamuthevar Vadivel Murugan
51328ac902aSMatthias Schiffer status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB);
514f453f293SPratyush Yadav if (status)
515f453f293SPratyush Yadav return status;
516f453f293SPratyush Yadav
51731fb632bSRamuthevar Vadivel Murugan if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
51831fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev,
51931fb632bSRamuthevar Vadivel Murugan "Invalid input argument, len %zu rxbuf 0x%p\n",
52031fb632bSRamuthevar Vadivel Murugan n_rx, rxbuf);
52131fb632bSRamuthevar Vadivel Murugan return -EINVAL;
52231fb632bSRamuthevar Vadivel Murugan }
52331fb632bSRamuthevar Vadivel Murugan
52428ac902aSMatthias Schiffer if (op->cmd.dtr)
525f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8;
526f453f293SPratyush Yadav else
527f453f293SPratyush Yadav opcode = op->cmd.opcode;
528f453f293SPratyush Yadav
52931fb632bSRamuthevar Vadivel Murugan reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
53031fb632bSRamuthevar Vadivel Murugan
53128ac902aSMatthias Schiffer rdreg = cqspi_calc_rdreg(op);
53231fb632bSRamuthevar Vadivel Murugan writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
53331fb632bSRamuthevar Vadivel Murugan
53428ac902aSMatthias Schiffer dummy_clk = cqspi_calc_dummy(op);
535888d517bSPratyush Yadav if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
536888d517bSPratyush Yadav return -EOPNOTSUPP;
537888d517bSPratyush Yadav
538888d517bSPratyush Yadav if (dummy_clk)
539888d517bSPratyush Yadav reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK)
540888d517bSPratyush Yadav << CQSPI_REG_CMDCTRL_DUMMY_LSB;
541888d517bSPratyush Yadav
54231fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
54331fb632bSRamuthevar Vadivel Murugan
54431fb632bSRamuthevar Vadivel Murugan /* 0 means 1 byte. */
54531fb632bSRamuthevar Vadivel Murugan reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
54631fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
547a8674ae0SDhruva Gole
548a8674ae0SDhruva Gole /* setup ADDR BIT field */
549a8674ae0SDhruva Gole if (op->addr.nbytes) {
550a8674ae0SDhruva Gole reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
551a8674ae0SDhruva Gole reg |= ((op->addr.nbytes - 1) &
552a8674ae0SDhruva Gole CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
553a8674ae0SDhruva Gole << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
554a8674ae0SDhruva Gole
555a8674ae0SDhruva Gole writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);
556a8674ae0SDhruva Gole }
557a8674ae0SDhruva Gole
55831fb632bSRamuthevar Vadivel Murugan status = cqspi_exec_flash_cmd(cqspi, reg);
55931fb632bSRamuthevar Vadivel Murugan if (status)
56031fb632bSRamuthevar Vadivel Murugan return status;
56131fb632bSRamuthevar Vadivel Murugan
56231fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
56331fb632bSRamuthevar Vadivel Murugan
56431fb632bSRamuthevar Vadivel Murugan /* Put the read value into rx_buf */
56531fb632bSRamuthevar Vadivel Murugan read_len = (n_rx > 4) ? 4 : n_rx;
56631fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, ®, read_len);
56731fb632bSRamuthevar Vadivel Murugan rxbuf += read_len;
56831fb632bSRamuthevar Vadivel Murugan
56931fb632bSRamuthevar Vadivel Murugan if (n_rx > 4) {
57031fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
57131fb632bSRamuthevar Vadivel Murugan
57231fb632bSRamuthevar Vadivel Murugan read_len = n_rx - read_len;
57331fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, ®, read_len);
57431fb632bSRamuthevar Vadivel Murugan }
57531fb632bSRamuthevar Vadivel Murugan
576d4f43a2dSDhruva Gole /* Reset CMD_CTRL Reg once command read completes */
577d4f43a2dSDhruva Gole writel(0, reg_base + CQSPI_REG_CMDCTRL);
578d4f43a2dSDhruva Gole
57931fb632bSRamuthevar Vadivel Murugan return 0;
58031fb632bSRamuthevar Vadivel Murugan }
58131fb632bSRamuthevar Vadivel Murugan
cqspi_command_write(struct cqspi_flash_pdata * f_pdata,const struct spi_mem_op * op)58231fb632bSRamuthevar Vadivel Murugan static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata,
58331fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op)
58431fb632bSRamuthevar Vadivel Murugan {
58531fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi;
58631fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase;
587f453f293SPratyush Yadav u8 opcode;
58831fb632bSRamuthevar Vadivel Murugan const u8 *txbuf = op->data.buf.out;
58931fb632bSRamuthevar Vadivel Murugan size_t n_tx = op->data.nbytes;
59031fb632bSRamuthevar Vadivel Murugan unsigned int reg;
59131fb632bSRamuthevar Vadivel Murugan unsigned int data;
59231fb632bSRamuthevar Vadivel Murugan size_t write_len;
593f453f293SPratyush Yadav int ret;
594f453f293SPratyush Yadav
59528ac902aSMatthias Schiffer ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB);
596f453f293SPratyush Yadav if (ret)
597f453f293SPratyush Yadav return ret;
59831fb632bSRamuthevar Vadivel Murugan
59931fb632bSRamuthevar Vadivel Murugan if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) {
60031fb632bSRamuthevar Vadivel Murugan dev_err(&cqspi->pdev->dev,
60131fb632bSRamuthevar Vadivel Murugan "Invalid input argument, cmdlen %zu txbuf 0x%p\n",
60231fb632bSRamuthevar Vadivel Murugan n_tx, txbuf);
60331fb632bSRamuthevar Vadivel Murugan return -EINVAL;
60431fb632bSRamuthevar Vadivel Murugan }
60531fb632bSRamuthevar Vadivel Murugan
60628ac902aSMatthias Schiffer reg = cqspi_calc_rdreg(op);
607f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_RD_INSTR);
608f453f293SPratyush Yadav
60928ac902aSMatthias Schiffer if (op->cmd.dtr)
610f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8;
611f453f293SPratyush Yadav else
612f453f293SPratyush Yadav opcode = op->cmd.opcode;
613f453f293SPratyush Yadav
61431fb632bSRamuthevar Vadivel Murugan reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
61531fb632bSRamuthevar Vadivel Murugan
61631fb632bSRamuthevar Vadivel Murugan if (op->addr.nbytes) {
61731fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
61831fb632bSRamuthevar Vadivel Murugan reg |= ((op->addr.nbytes - 1) &
61931fb632bSRamuthevar Vadivel Murugan CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
62031fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
62131fb632bSRamuthevar Vadivel Murugan
62231fb632bSRamuthevar Vadivel Murugan writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);
62331fb632bSRamuthevar Vadivel Murugan }
62431fb632bSRamuthevar Vadivel Murugan
62531fb632bSRamuthevar Vadivel Murugan if (n_tx) {
62631fb632bSRamuthevar Vadivel Murugan reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
62731fb632bSRamuthevar Vadivel Murugan reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
62831fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
62931fb632bSRamuthevar Vadivel Murugan data = 0;
63031fb632bSRamuthevar Vadivel Murugan write_len = (n_tx > 4) ? 4 : n_tx;
63131fb632bSRamuthevar Vadivel Murugan memcpy(&data, txbuf, write_len);
63231fb632bSRamuthevar Vadivel Murugan txbuf += write_len;
63331fb632bSRamuthevar Vadivel Murugan writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
63431fb632bSRamuthevar Vadivel Murugan
63531fb632bSRamuthevar Vadivel Murugan if (n_tx > 4) {
63631fb632bSRamuthevar Vadivel Murugan data = 0;
63731fb632bSRamuthevar Vadivel Murugan write_len = n_tx - 4;
63831fb632bSRamuthevar Vadivel Murugan memcpy(&data, txbuf, write_len);
63931fb632bSRamuthevar Vadivel Murugan writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);
64031fb632bSRamuthevar Vadivel Murugan }
64131fb632bSRamuthevar Vadivel Murugan }
64231fb632bSRamuthevar Vadivel Murugan
643d4f43a2dSDhruva Gole ret = cqspi_exec_flash_cmd(cqspi, reg);
644d4f43a2dSDhruva Gole
645d4f43a2dSDhruva Gole /* Reset CMD_CTRL Reg once command write completes */
646d4f43a2dSDhruva Gole writel(0, reg_base + CQSPI_REG_CMDCTRL);
647d4f43a2dSDhruva Gole
648d4f43a2dSDhruva Gole return ret;
64931fb632bSRamuthevar Vadivel Murugan }
65031fb632bSRamuthevar Vadivel Murugan
cqspi_read_setup(struct cqspi_flash_pdata * f_pdata,const struct spi_mem_op * op)65131fb632bSRamuthevar Vadivel Murugan static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata,
65231fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op)
65331fb632bSRamuthevar Vadivel Murugan {
65431fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi;
65531fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase;
65631fb632bSRamuthevar Vadivel Murugan unsigned int dummy_clk = 0;
65731fb632bSRamuthevar Vadivel Murugan unsigned int reg;
658f453f293SPratyush Yadav int ret;
659f453f293SPratyush Yadav u8 opcode;
66031fb632bSRamuthevar Vadivel Murugan
66128ac902aSMatthias Schiffer ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB);
662f453f293SPratyush Yadav if (ret)
663f453f293SPratyush Yadav return ret;
664f453f293SPratyush Yadav
66528ac902aSMatthias Schiffer if (op->cmd.dtr)
666f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8;
667f453f293SPratyush Yadav else
668f453f293SPratyush Yadav opcode = op->cmd.opcode;
669f453f293SPratyush Yadav
670f453f293SPratyush Yadav reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
67128ac902aSMatthias Schiffer reg |= cqspi_calc_rdreg(op);
67231fb632bSRamuthevar Vadivel Murugan
67331fb632bSRamuthevar Vadivel Murugan /* Setup dummy clock cycles */
67428ac902aSMatthias Schiffer dummy_clk = cqspi_calc_dummy(op);
675888d517bSPratyush Yadav
67631fb632bSRamuthevar Vadivel Murugan if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
677ceeda328SPratyush Yadav return -EOPNOTSUPP;
67831fb632bSRamuthevar Vadivel Murugan
67931fb632bSRamuthevar Vadivel Murugan if (dummy_clk)
68031fb632bSRamuthevar Vadivel Murugan reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
68131fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_RD_INSTR_DUMMY_LSB;
68231fb632bSRamuthevar Vadivel Murugan
68331fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_RD_INSTR);
68431fb632bSRamuthevar Vadivel Murugan
68531fb632bSRamuthevar Vadivel Murugan /* Set address width */
68631fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_SIZE);
68731fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
68831fb632bSRamuthevar Vadivel Murugan reg |= (op->addr.nbytes - 1);
68931fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_SIZE);
69031fb632bSRamuthevar Vadivel Murugan return 0;
69131fb632bSRamuthevar Vadivel Murugan }
69231fb632bSRamuthevar Vadivel Murugan
cqspi_indirect_read_execute(struct cqspi_flash_pdata * f_pdata,u8 * rxbuf,loff_t from_addr,const size_t n_rx)69331fb632bSRamuthevar Vadivel Murugan static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
69431fb632bSRamuthevar Vadivel Murugan u8 *rxbuf, loff_t from_addr,
69531fb632bSRamuthevar Vadivel Murugan const size_t n_rx)
69631fb632bSRamuthevar Vadivel Murugan {
69731fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi;
69831fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev;
69931fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase;
70031fb632bSRamuthevar Vadivel Murugan void __iomem *ahb_base = cqspi->ahb_base;
70131fb632bSRamuthevar Vadivel Murugan unsigned int remaining = n_rx;
70231fb632bSRamuthevar Vadivel Murugan unsigned int mod_bytes = n_rx % 4;
70331fb632bSRamuthevar Vadivel Murugan unsigned int bytes_to_read = 0;
70431fb632bSRamuthevar Vadivel Murugan u8 *rxbuf_end = rxbuf + n_rx;
70531fb632bSRamuthevar Vadivel Murugan int ret = 0;
70631fb632bSRamuthevar Vadivel Murugan
70731fb632bSRamuthevar Vadivel Murugan writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
70831fb632bSRamuthevar Vadivel Murugan writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
70931fb632bSRamuthevar Vadivel Murugan
71031fb632bSRamuthevar Vadivel Murugan /* Clear all interrupts. */
71131fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
71231fb632bSRamuthevar Vadivel Murugan
7139ee5b6d5SNiravkumar L Rabara /*
7149ee5b6d5SNiravkumar L Rabara * On SoCFPGA platform reading the SRAM is slow due to
7159ee5b6d5SNiravkumar L Rabara * hardware limitation and causing read interrupt storm to CPU,
7169ee5b6d5SNiravkumar L Rabara * so enabling only watermark interrupt to disable all read
7179ee5b6d5SNiravkumar L Rabara * interrupts later as we want to run "bytes to read" loop with
7189ee5b6d5SNiravkumar L Rabara * all the read interrupts disabled for max performance.
7199ee5b6d5SNiravkumar L Rabara */
7209ee5b6d5SNiravkumar L Rabara
7219ee5b6d5SNiravkumar L Rabara if (!cqspi->slow_sram)
72231fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
7239ee5b6d5SNiravkumar L Rabara else
7249ee5b6d5SNiravkumar L Rabara writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK);
72531fb632bSRamuthevar Vadivel Murugan
72631fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete);
72731fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTRD_START_MASK,
72831fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTRD);
72931fb632bSRamuthevar Vadivel Murugan
73031fb632bSRamuthevar Vadivel Murugan while (remaining > 0) {
73131fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->transfer_complete,
73231fb632bSRamuthevar Vadivel Murugan msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS)))
73331fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT;
73431fb632bSRamuthevar Vadivel Murugan
7359ee5b6d5SNiravkumar L Rabara /*
7369ee5b6d5SNiravkumar L Rabara * Disable all read interrupts until
7379ee5b6d5SNiravkumar L Rabara * we are out of "bytes to read"
7389ee5b6d5SNiravkumar L Rabara */
7399ee5b6d5SNiravkumar L Rabara if (cqspi->slow_sram)
7409ee5b6d5SNiravkumar L Rabara writel(0x0, reg_base + CQSPI_REG_IRQMASK);
7419ee5b6d5SNiravkumar L Rabara
74231fb632bSRamuthevar Vadivel Murugan bytes_to_read = cqspi_get_rd_sram_level(cqspi);
74331fb632bSRamuthevar Vadivel Murugan
74431fb632bSRamuthevar Vadivel Murugan if (ret && bytes_to_read == 0) {
74531fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect read timeout, no bytes\n");
74631fb632bSRamuthevar Vadivel Murugan goto failrd;
74731fb632bSRamuthevar Vadivel Murugan }
74831fb632bSRamuthevar Vadivel Murugan
74931fb632bSRamuthevar Vadivel Murugan while (bytes_to_read != 0) {
75031fb632bSRamuthevar Vadivel Murugan unsigned int word_remain = round_down(remaining, 4);
75131fb632bSRamuthevar Vadivel Murugan
75231fb632bSRamuthevar Vadivel Murugan bytes_to_read *= cqspi->fifo_width;
75331fb632bSRamuthevar Vadivel Murugan bytes_to_read = bytes_to_read > remaining ?
75431fb632bSRamuthevar Vadivel Murugan remaining : bytes_to_read;
75531fb632bSRamuthevar Vadivel Murugan bytes_to_read = round_down(bytes_to_read, 4);
75631fb632bSRamuthevar Vadivel Murugan /* Read 4 byte word chunks then single bytes */
75731fb632bSRamuthevar Vadivel Murugan if (bytes_to_read) {
75831fb632bSRamuthevar Vadivel Murugan ioread32_rep(ahb_base, rxbuf,
75931fb632bSRamuthevar Vadivel Murugan (bytes_to_read / 4));
76031fb632bSRamuthevar Vadivel Murugan } else if (!word_remain && mod_bytes) {
76131fb632bSRamuthevar Vadivel Murugan unsigned int temp = ioread32(ahb_base);
76231fb632bSRamuthevar Vadivel Murugan
76331fb632bSRamuthevar Vadivel Murugan bytes_to_read = mod_bytes;
76431fb632bSRamuthevar Vadivel Murugan memcpy(rxbuf, &temp, min((unsigned int)
76531fb632bSRamuthevar Vadivel Murugan (rxbuf_end - rxbuf),
76631fb632bSRamuthevar Vadivel Murugan bytes_to_read));
76731fb632bSRamuthevar Vadivel Murugan }
76831fb632bSRamuthevar Vadivel Murugan rxbuf += bytes_to_read;
76931fb632bSRamuthevar Vadivel Murugan remaining -= bytes_to_read;
77031fb632bSRamuthevar Vadivel Murugan bytes_to_read = cqspi_get_rd_sram_level(cqspi);
77131fb632bSRamuthevar Vadivel Murugan }
77231fb632bSRamuthevar Vadivel Murugan
7739ee5b6d5SNiravkumar L Rabara if (remaining > 0) {
77431fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete);
7759ee5b6d5SNiravkumar L Rabara if (cqspi->slow_sram)
7769ee5b6d5SNiravkumar L Rabara writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK);
7779ee5b6d5SNiravkumar L Rabara }
77831fb632bSRamuthevar Vadivel Murugan }
77931fb632bSRamuthevar Vadivel Murugan
78031fb632bSRamuthevar Vadivel Murugan /* Check indirect done status */
78131fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
78231fb632bSRamuthevar Vadivel Murugan CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
78331fb632bSRamuthevar Vadivel Murugan if (ret) {
78431fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect read completion error (%i)\n", ret);
78531fb632bSRamuthevar Vadivel Murugan goto failrd;
78631fb632bSRamuthevar Vadivel Murugan }
78731fb632bSRamuthevar Vadivel Murugan
78831fb632bSRamuthevar Vadivel Murugan /* Disable interrupt */
78931fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK);
79031fb632bSRamuthevar Vadivel Murugan
79131fb632bSRamuthevar Vadivel Murugan /* Clear indirect completion status */
79231fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
79331fb632bSRamuthevar Vadivel Murugan
79431fb632bSRamuthevar Vadivel Murugan return 0;
79531fb632bSRamuthevar Vadivel Murugan
79631fb632bSRamuthevar Vadivel Murugan failrd:
79731fb632bSRamuthevar Vadivel Murugan /* Disable interrupt */
79831fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK);
79931fb632bSRamuthevar Vadivel Murugan
80031fb632bSRamuthevar Vadivel Murugan /* Cancel the indirect read */
801152ac606SHongbin Ji writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK,
80231fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTRD);
80331fb632bSRamuthevar Vadivel Murugan return ret;
80431fb632bSRamuthevar Vadivel Murugan }
80531fb632bSRamuthevar Vadivel Murugan
cqspi_controller_enable(struct cqspi_st * cqspi,bool enable)806c0b53f4eSSai Krishna Potthuri static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
807c0b53f4eSSai Krishna Potthuri {
808c0b53f4eSSai Krishna Potthuri void __iomem *reg_base = cqspi->iobase;
809c0b53f4eSSai Krishna Potthuri unsigned int reg;
810c0b53f4eSSai Krishna Potthuri
811c0b53f4eSSai Krishna Potthuri reg = readl(reg_base + CQSPI_REG_CONFIG);
812c0b53f4eSSai Krishna Potthuri
813c0b53f4eSSai Krishna Potthuri if (enable)
814c0b53f4eSSai Krishna Potthuri reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
815c0b53f4eSSai Krishna Potthuri else
816c0b53f4eSSai Krishna Potthuri reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
817c0b53f4eSSai Krishna Potthuri
818c0b53f4eSSai Krishna Potthuri writel(reg, reg_base + CQSPI_REG_CONFIG);
819c0b53f4eSSai Krishna Potthuri }
820c0b53f4eSSai Krishna Potthuri
cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata * f_pdata,u_char * rxbuf,loff_t from_addr,size_t n_rx)8211a6f854fSSai Krishna Potthuri static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata,
8221a6f854fSSai Krishna Potthuri u_char *rxbuf, loff_t from_addr,
8231a6f854fSSai Krishna Potthuri size_t n_rx)
8241a6f854fSSai Krishna Potthuri {
8251a6f854fSSai Krishna Potthuri struct cqspi_st *cqspi = f_pdata->cqspi;
8261a6f854fSSai Krishna Potthuri struct device *dev = &cqspi->pdev->dev;
8271a6f854fSSai Krishna Potthuri void __iomem *reg_base = cqspi->iobase;
8281a6f854fSSai Krishna Potthuri u32 reg, bytes_to_dma;
8291a6f854fSSai Krishna Potthuri loff_t addr = from_addr;
8301a6f854fSSai Krishna Potthuri void *buf = rxbuf;
8311a6f854fSSai Krishna Potthuri dma_addr_t dma_addr;
8321a6f854fSSai Krishna Potthuri u8 bytes_rem;
8331a6f854fSSai Krishna Potthuri int ret = 0;
8341a6f854fSSai Krishna Potthuri
8351a6f854fSSai Krishna Potthuri bytes_rem = n_rx % 4;
8361a6f854fSSai Krishna Potthuri bytes_to_dma = (n_rx - bytes_rem);
8371a6f854fSSai Krishna Potthuri
8381a6f854fSSai Krishna Potthuri if (!bytes_to_dma)
8391a6f854fSSai Krishna Potthuri goto nondmard;
8401a6f854fSSai Krishna Potthuri
8411a6f854fSSai Krishna Potthuri ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA);
8421a6f854fSSai Krishna Potthuri if (ret)
8431a6f854fSSai Krishna Potthuri return ret;
8441a6f854fSSai Krishna Potthuri
845c0b53f4eSSai Krishna Potthuri cqspi_controller_enable(cqspi, 0);
846c0b53f4eSSai Krishna Potthuri
8471a6f854fSSai Krishna Potthuri reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
8481a6f854fSSai Krishna Potthuri reg |= CQSPI_REG_CONFIG_DMA_MASK;
8491a6f854fSSai Krishna Potthuri writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
8501a6f854fSSai Krishna Potthuri
851c0b53f4eSSai Krishna Potthuri cqspi_controller_enable(cqspi, 1);
852c0b53f4eSSai Krishna Potthuri
8531a6f854fSSai Krishna Potthuri dma_addr = dma_map_single(dev, rxbuf, bytes_to_dma, DMA_FROM_DEVICE);
8541a6f854fSSai Krishna Potthuri if (dma_mapping_error(dev, dma_addr)) {
8551a6f854fSSai Krishna Potthuri dev_err(dev, "dma mapping failed\n");
8561a6f854fSSai Krishna Potthuri return -ENOMEM;
8571a6f854fSSai Krishna Potthuri }
8581a6f854fSSai Krishna Potthuri
8591a6f854fSSai Krishna Potthuri writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
8601a6f854fSSai Krishna Potthuri writel(bytes_to_dma, reg_base + CQSPI_REG_INDIRECTRDBYTES);
8611a6f854fSSai Krishna Potthuri writel(CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL,
8621a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_INDTRIG_ADDRRANGE);
8631a6f854fSSai Krishna Potthuri
8641a6f854fSSai Krishna Potthuri /* Clear all interrupts. */
8651a6f854fSSai Krishna Potthuri writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
8661a6f854fSSai Krishna Potthuri
8671a6f854fSSai Krishna Potthuri /* Enable DMA done interrupt */
8681a6f854fSSai Krishna Potthuri writel(CQSPI_REG_VERSAL_DMA_DST_DONE_MASK,
8691a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_VERSAL_DMA_DST_I_EN);
8701a6f854fSSai Krishna Potthuri
8711a6f854fSSai Krishna Potthuri /* Default DMA periph configuration */
8721a6f854fSSai Krishna Potthuri writel(CQSPI_REG_VERSAL_DMA_VAL, reg_base + CQSPI_REG_DMA);
8731a6f854fSSai Krishna Potthuri
8741a6f854fSSai Krishna Potthuri /* Configure DMA Dst address */
8751a6f854fSSai Krishna Potthuri writel(lower_32_bits(dma_addr),
8761a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR);
8771a6f854fSSai Krishna Potthuri writel(upper_32_bits(dma_addr),
8781a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB);
8791a6f854fSSai Krishna Potthuri
8801a6f854fSSai Krishna Potthuri /* Configure DMA Src address */
8811a6f854fSSai Krishna Potthuri writel(cqspi->trigger_address, reg_base +
8821a6f854fSSai Krishna Potthuri CQSPI_REG_VERSAL_DMA_SRC_ADDR);
8831a6f854fSSai Krishna Potthuri
8841a6f854fSSai Krishna Potthuri /* Set DMA destination size */
8851a6f854fSSai Krishna Potthuri writel(bytes_to_dma, reg_base + CQSPI_REG_VERSAL_DMA_DST_SIZE);
8861a6f854fSSai Krishna Potthuri
8871a6f854fSSai Krishna Potthuri /* Set DMA destination control */
8881a6f854fSSai Krishna Potthuri writel(CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL,
8891a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_VERSAL_DMA_DST_CTRL);
8901a6f854fSSai Krishna Potthuri
8911a6f854fSSai Krishna Potthuri writel(CQSPI_REG_INDIRECTRD_START_MASK,
8921a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_INDIRECTRD);
8931a6f854fSSai Krishna Potthuri
8941a6f854fSSai Krishna Potthuri reinit_completion(&cqspi->transfer_complete);
8951a6f854fSSai Krishna Potthuri
8961a6f854fSSai Krishna Potthuri if (!wait_for_completion_timeout(&cqspi->transfer_complete,
89722c8ce0aSSai Krishna Potthuri msecs_to_jiffies(max_t(size_t, bytes_to_dma, 500)))) {
8981a6f854fSSai Krishna Potthuri ret = -ETIMEDOUT;
8991a6f854fSSai Krishna Potthuri goto failrd;
9001a6f854fSSai Krishna Potthuri }
9011a6f854fSSai Krishna Potthuri
9021a6f854fSSai Krishna Potthuri /* Disable DMA interrupt */
9031a6f854fSSai Krishna Potthuri writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS);
9041a6f854fSSai Krishna Potthuri
9051a6f854fSSai Krishna Potthuri /* Clear indirect completion status */
9061a6f854fSSai Krishna Potthuri writel(CQSPI_REG_INDIRECTRD_DONE_MASK,
9071a6f854fSSai Krishna Potthuri cqspi->iobase + CQSPI_REG_INDIRECTRD);
9081a6f854fSSai Krishna Potthuri dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE);
9091a6f854fSSai Krishna Potthuri
910c0b53f4eSSai Krishna Potthuri cqspi_controller_enable(cqspi, 0);
911c0b53f4eSSai Krishna Potthuri
9121a6f854fSSai Krishna Potthuri reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
9131a6f854fSSai Krishna Potthuri reg &= ~CQSPI_REG_CONFIG_DMA_MASK;
9141a6f854fSSai Krishna Potthuri writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
9151a6f854fSSai Krishna Potthuri
916c0b53f4eSSai Krishna Potthuri cqspi_controller_enable(cqspi, 1);
917c0b53f4eSSai Krishna Potthuri
9181a6f854fSSai Krishna Potthuri ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id,
9191a6f854fSSai Krishna Potthuri PM_OSPI_MUX_SEL_LINEAR);
9201a6f854fSSai Krishna Potthuri if (ret)
9211a6f854fSSai Krishna Potthuri return ret;
9221a6f854fSSai Krishna Potthuri
9231a6f854fSSai Krishna Potthuri nondmard:
9241a6f854fSSai Krishna Potthuri if (bytes_rem) {
9251a6f854fSSai Krishna Potthuri addr += bytes_to_dma;
9261a6f854fSSai Krishna Potthuri buf += bytes_to_dma;
9271a6f854fSSai Krishna Potthuri ret = cqspi_indirect_read_execute(f_pdata, buf, addr,
9281a6f854fSSai Krishna Potthuri bytes_rem);
9291a6f854fSSai Krishna Potthuri if (ret)
9301a6f854fSSai Krishna Potthuri return ret;
9311a6f854fSSai Krishna Potthuri }
9321a6f854fSSai Krishna Potthuri
9331a6f854fSSai Krishna Potthuri return 0;
9341a6f854fSSai Krishna Potthuri
9351a6f854fSSai Krishna Potthuri failrd:
9361a6f854fSSai Krishna Potthuri /* Disable DMA interrupt */
9371a6f854fSSai Krishna Potthuri writel(0x0, reg_base + CQSPI_REG_VERSAL_DMA_DST_I_DIS);
9381a6f854fSSai Krishna Potthuri
9391a6f854fSSai Krishna Potthuri /* Cancel the indirect read */
9401a6f854fSSai Krishna Potthuri writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
9411a6f854fSSai Krishna Potthuri reg_base + CQSPI_REG_INDIRECTRD);
9421a6f854fSSai Krishna Potthuri
943d9c55c95SArnd Bergmann dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE);
9441a6f854fSSai Krishna Potthuri
9451a6f854fSSai Krishna Potthuri reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
9461a6f854fSSai Krishna Potthuri reg &= ~CQSPI_REG_CONFIG_DMA_MASK;
9471a6f854fSSai Krishna Potthuri writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
9481a6f854fSSai Krishna Potthuri
9491a6f854fSSai Krishna Potthuri zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR);
9501a6f854fSSai Krishna Potthuri
9511a6f854fSSai Krishna Potthuri return ret;
9521a6f854fSSai Krishna Potthuri }
9531a6f854fSSai Krishna Potthuri
cqspi_write_setup(struct cqspi_flash_pdata * f_pdata,const struct spi_mem_op * op)95431fb632bSRamuthevar Vadivel Murugan static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata,
95531fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op)
95631fb632bSRamuthevar Vadivel Murugan {
95731fb632bSRamuthevar Vadivel Murugan unsigned int reg;
958f453f293SPratyush Yadav int ret;
95931fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi;
96031fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase;
961f453f293SPratyush Yadav u8 opcode;
962f453f293SPratyush Yadav
96328ac902aSMatthias Schiffer ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB);
964f453f293SPratyush Yadav if (ret)
965f453f293SPratyush Yadav return ret;
966f453f293SPratyush Yadav
96728ac902aSMatthias Schiffer if (op->cmd.dtr)
968f453f293SPratyush Yadav opcode = op->cmd.opcode >> 8;
969f453f293SPratyush Yadav else
970f453f293SPratyush Yadav opcode = op->cmd.opcode;
97131fb632bSRamuthevar Vadivel Murugan
97231fb632bSRamuthevar Vadivel Murugan /* Set opcode. */
973f453f293SPratyush Yadav reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
97428ac902aSMatthias Schiffer reg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;
97528ac902aSMatthias Schiffer reg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB;
97631fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_WR_INSTR);
97728ac902aSMatthias Schiffer reg = cqspi_calc_rdreg(op);
97831fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_RD_INSTR);
97931fb632bSRamuthevar Vadivel Murugan
980f453f293SPratyush Yadav /*
9819cb2ff11SApurva Nandan * SPI NAND flashes require the address of the status register to be
9829cb2ff11SApurva Nandan * passed in the Read SR command. Also, some SPI NOR flashes like the
9839cb2ff11SApurva Nandan * cypress Semper flash expect a 4-byte dummy address in the Read SR
9849cb2ff11SApurva Nandan * command in DTR mode.
9859cb2ff11SApurva Nandan *
9869cb2ff11SApurva Nandan * But this controller does not support address phase in the Read SR
9879cb2ff11SApurva Nandan * command when doing auto-HW polling. So, disable write completion
9889cb2ff11SApurva Nandan * polling on the controller's side. spinand and spi-nor will take
9899cb2ff11SApurva Nandan * care of polling the status register.
990f453f293SPratyush Yadav */
99198d948ebSDinh Nguyen if (cqspi->wr_completion) {
992f453f293SPratyush Yadav reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
993f453f293SPratyush Yadav reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL;
994f453f293SPratyush Yadav writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
995e8c51b16SDhruva Gole /*
996e8c51b16SDhruva Gole * DAC mode require auto polling as flash needs to be polled
997e8c51b16SDhruva Gole * for write completion in case of bubble in SPI transaction
998e8c51b16SDhruva Gole * due to slow CPU/DMA master.
999e8c51b16SDhruva Gole */
1000e8c51b16SDhruva Gole cqspi->use_direct_mode_wr = false;
100198d948ebSDinh Nguyen }
1002f453f293SPratyush Yadav
100331fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_SIZE);
100431fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
100531fb632bSRamuthevar Vadivel Murugan reg |= (op->addr.nbytes - 1);
100631fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_SIZE);
100731fb632bSRamuthevar Vadivel Murugan return 0;
100831fb632bSRamuthevar Vadivel Murugan }
100931fb632bSRamuthevar Vadivel Murugan
cqspi_indirect_write_execute(struct cqspi_flash_pdata * f_pdata,loff_t to_addr,const u8 * txbuf,const size_t n_tx)101031fb632bSRamuthevar Vadivel Murugan static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata,
101131fb632bSRamuthevar Vadivel Murugan loff_t to_addr, const u8 *txbuf,
101231fb632bSRamuthevar Vadivel Murugan const size_t n_tx)
101331fb632bSRamuthevar Vadivel Murugan {
101431fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi;
101531fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev;
101631fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase;
101731fb632bSRamuthevar Vadivel Murugan unsigned int remaining = n_tx;
101831fb632bSRamuthevar Vadivel Murugan unsigned int write_bytes;
101931fb632bSRamuthevar Vadivel Murugan int ret;
102031fb632bSRamuthevar Vadivel Murugan
102131fb632bSRamuthevar Vadivel Murugan writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
102231fb632bSRamuthevar Vadivel Murugan writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
102331fb632bSRamuthevar Vadivel Murugan
102431fb632bSRamuthevar Vadivel Murugan /* Clear all interrupts. */
102531fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
102631fb632bSRamuthevar Vadivel Murugan
102731fb632bSRamuthevar Vadivel Murugan writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
102831fb632bSRamuthevar Vadivel Murugan
102931fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete);
103031fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_START_MASK,
103131fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTWR);
103231fb632bSRamuthevar Vadivel Murugan /*
103331fb632bSRamuthevar Vadivel Murugan * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
103431fb632bSRamuthevar Vadivel Murugan * Controller programming sequence, couple of cycles of
103531fb632bSRamuthevar Vadivel Murugan * QSPI_REF_CLK delay is required for the above bit to
103631fb632bSRamuthevar Vadivel Murugan * be internally synchronized by the QSPI module. Provide 5
103731fb632bSRamuthevar Vadivel Murugan * cycles of delay.
103831fb632bSRamuthevar Vadivel Murugan */
103931fb632bSRamuthevar Vadivel Murugan if (cqspi->wr_delay)
104031fb632bSRamuthevar Vadivel Murugan ndelay(cqspi->wr_delay);
104131fb632bSRamuthevar Vadivel Murugan
1042f5c2f9f9SBrad Larson /*
1043f5c2f9f9SBrad Larson * If a hazard exists between the APB and AHB interfaces, perform a
1044f5c2f9f9SBrad Larson * dummy readback from the controller to ensure synchronization.
1045f5c2f9f9SBrad Larson */
1046f5c2f9f9SBrad Larson if (cqspi->apb_ahb_hazard)
1047f5c2f9f9SBrad Larson readl(reg_base + CQSPI_REG_INDIRECTWR);
1048f5c2f9f9SBrad Larson
104931fb632bSRamuthevar Vadivel Murugan while (remaining > 0) {
105031fb632bSRamuthevar Vadivel Murugan size_t write_words, mod_bytes;
105131fb632bSRamuthevar Vadivel Murugan
105231fb632bSRamuthevar Vadivel Murugan write_bytes = remaining;
105331fb632bSRamuthevar Vadivel Murugan write_words = write_bytes / 4;
105431fb632bSRamuthevar Vadivel Murugan mod_bytes = write_bytes % 4;
105531fb632bSRamuthevar Vadivel Murugan /* Write 4 bytes at a time then single bytes. */
105631fb632bSRamuthevar Vadivel Murugan if (write_words) {
105731fb632bSRamuthevar Vadivel Murugan iowrite32_rep(cqspi->ahb_base, txbuf, write_words);
105831fb632bSRamuthevar Vadivel Murugan txbuf += (write_words * 4);
105931fb632bSRamuthevar Vadivel Murugan }
106031fb632bSRamuthevar Vadivel Murugan if (mod_bytes) {
106131fb632bSRamuthevar Vadivel Murugan unsigned int temp = 0xFFFFFFFF;
106231fb632bSRamuthevar Vadivel Murugan
106331fb632bSRamuthevar Vadivel Murugan memcpy(&temp, txbuf, mod_bytes);
106431fb632bSRamuthevar Vadivel Murugan iowrite32(temp, cqspi->ahb_base);
106531fb632bSRamuthevar Vadivel Murugan txbuf += mod_bytes;
106631fb632bSRamuthevar Vadivel Murugan }
106731fb632bSRamuthevar Vadivel Murugan
106831fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->transfer_complete,
106931fb632bSRamuthevar Vadivel Murugan msecs_to_jiffies(CQSPI_TIMEOUT_MS))) {
107031fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect write timeout\n");
107131fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT;
107231fb632bSRamuthevar Vadivel Murugan goto failwr;
107331fb632bSRamuthevar Vadivel Murugan }
107431fb632bSRamuthevar Vadivel Murugan
107531fb632bSRamuthevar Vadivel Murugan remaining -= write_bytes;
107631fb632bSRamuthevar Vadivel Murugan
107731fb632bSRamuthevar Vadivel Murugan if (remaining > 0)
107831fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->transfer_complete);
107931fb632bSRamuthevar Vadivel Murugan }
108031fb632bSRamuthevar Vadivel Murugan
108131fb632bSRamuthevar Vadivel Murugan /* Check indirect done status */
108231fb632bSRamuthevar Vadivel Murugan ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
108331fb632bSRamuthevar Vadivel Murugan CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
108431fb632bSRamuthevar Vadivel Murugan if (ret) {
108531fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Indirect write completion error (%i)\n", ret);
108631fb632bSRamuthevar Vadivel Murugan goto failwr;
108731fb632bSRamuthevar Vadivel Murugan }
108831fb632bSRamuthevar Vadivel Murugan
108931fb632bSRamuthevar Vadivel Murugan /* Disable interrupt. */
109031fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK);
109131fb632bSRamuthevar Vadivel Murugan
109231fb632bSRamuthevar Vadivel Murugan /* Clear indirect completion status */
109331fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
109431fb632bSRamuthevar Vadivel Murugan
109531fb632bSRamuthevar Vadivel Murugan cqspi_wait_idle(cqspi);
109631fb632bSRamuthevar Vadivel Murugan
109731fb632bSRamuthevar Vadivel Murugan return 0;
109831fb632bSRamuthevar Vadivel Murugan
109931fb632bSRamuthevar Vadivel Murugan failwr:
110031fb632bSRamuthevar Vadivel Murugan /* Disable interrupt. */
110131fb632bSRamuthevar Vadivel Murugan writel(0, reg_base + CQSPI_REG_IRQMASK);
110231fb632bSRamuthevar Vadivel Murugan
110331fb632bSRamuthevar Vadivel Murugan /* Cancel the indirect write */
110431fb632bSRamuthevar Vadivel Murugan writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
110531fb632bSRamuthevar Vadivel Murugan reg_base + CQSPI_REG_INDIRECTWR);
110631fb632bSRamuthevar Vadivel Murugan return ret;
110731fb632bSRamuthevar Vadivel Murugan }
110831fb632bSRamuthevar Vadivel Murugan
cqspi_chipselect(struct cqspi_flash_pdata * f_pdata)110931fb632bSRamuthevar Vadivel Murugan static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata)
111031fb632bSRamuthevar Vadivel Murugan {
111131fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi;
111231fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase;
111331fb632bSRamuthevar Vadivel Murugan unsigned int chip_select = f_pdata->cs;
111431fb632bSRamuthevar Vadivel Murugan unsigned int reg;
111531fb632bSRamuthevar Vadivel Murugan
111631fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG);
111731fb632bSRamuthevar Vadivel Murugan if (cqspi->is_decoded_cs) {
111831fb632bSRamuthevar Vadivel Murugan reg |= CQSPI_REG_CONFIG_DECODE_MASK;
111931fb632bSRamuthevar Vadivel Murugan } else {
112031fb632bSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
112131fb632bSRamuthevar Vadivel Murugan
112231fb632bSRamuthevar Vadivel Murugan /* Convert CS if without decoder.
112331fb632bSRamuthevar Vadivel Murugan * CS0 to 4b'1110
112431fb632bSRamuthevar Vadivel Murugan * CS1 to 4b'1101
112531fb632bSRamuthevar Vadivel Murugan * CS2 to 4b'1011
112631fb632bSRamuthevar Vadivel Murugan * CS3 to 4b'0111
112731fb632bSRamuthevar Vadivel Murugan */
112831fb632bSRamuthevar Vadivel Murugan chip_select = 0xF & ~(1 << chip_select);
112931fb632bSRamuthevar Vadivel Murugan }
113031fb632bSRamuthevar Vadivel Murugan
113131fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
113231fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
113331fb632bSRamuthevar Vadivel Murugan reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
113431fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
113531fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG);
113631fb632bSRamuthevar Vadivel Murugan }
113731fb632bSRamuthevar Vadivel Murugan
calculate_ticks_for_ns(const unsigned int ref_clk_hz,const unsigned int ns_val)113831fb632bSRamuthevar Vadivel Murugan static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
113931fb632bSRamuthevar Vadivel Murugan const unsigned int ns_val)
114031fb632bSRamuthevar Vadivel Murugan {
114131fb632bSRamuthevar Vadivel Murugan unsigned int ticks;
114231fb632bSRamuthevar Vadivel Murugan
114331fb632bSRamuthevar Vadivel Murugan ticks = ref_clk_hz / 1000; /* kHz */
114431fb632bSRamuthevar Vadivel Murugan ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
114531fb632bSRamuthevar Vadivel Murugan
114631fb632bSRamuthevar Vadivel Murugan return ticks;
114731fb632bSRamuthevar Vadivel Murugan }
114831fb632bSRamuthevar Vadivel Murugan
cqspi_delay(struct cqspi_flash_pdata * f_pdata)114931fb632bSRamuthevar Vadivel Murugan static void cqspi_delay(struct cqspi_flash_pdata *f_pdata)
115031fb632bSRamuthevar Vadivel Murugan {
115131fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi;
115231fb632bSRamuthevar Vadivel Murugan void __iomem *iobase = cqspi->iobase;
115331fb632bSRamuthevar Vadivel Murugan const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
115431fb632bSRamuthevar Vadivel Murugan unsigned int tshsl, tchsh, tslch, tsd2d;
115531fb632bSRamuthevar Vadivel Murugan unsigned int reg;
115631fb632bSRamuthevar Vadivel Murugan unsigned int tsclk;
115731fb632bSRamuthevar Vadivel Murugan
115831fb632bSRamuthevar Vadivel Murugan /* calculate the number of ref ticks for one sclk tick */
115931fb632bSRamuthevar Vadivel Murugan tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
116031fb632bSRamuthevar Vadivel Murugan
116131fb632bSRamuthevar Vadivel Murugan tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
116231fb632bSRamuthevar Vadivel Murugan /* this particular value must be at least one sclk */
116331fb632bSRamuthevar Vadivel Murugan if (tshsl < tsclk)
116431fb632bSRamuthevar Vadivel Murugan tshsl = tsclk;
116531fb632bSRamuthevar Vadivel Murugan
116631fb632bSRamuthevar Vadivel Murugan tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
116731fb632bSRamuthevar Vadivel Murugan tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
116831fb632bSRamuthevar Vadivel Murugan tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
116931fb632bSRamuthevar Vadivel Murugan
117031fb632bSRamuthevar Vadivel Murugan reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
117131fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSHSL_LSB;
117231fb632bSRamuthevar Vadivel Murugan reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
117331fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TCHSH_LSB;
117431fb632bSRamuthevar Vadivel Murugan reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
117531fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSLCH_LSB;
117631fb632bSRamuthevar Vadivel Murugan reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
117731fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_DELAY_TSD2D_LSB;
117831fb632bSRamuthevar Vadivel Murugan writel(reg, iobase + CQSPI_REG_DELAY);
117931fb632bSRamuthevar Vadivel Murugan }
118031fb632bSRamuthevar Vadivel Murugan
cqspi_config_baudrate_div(struct cqspi_st * cqspi)118131fb632bSRamuthevar Vadivel Murugan static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
118231fb632bSRamuthevar Vadivel Murugan {
118331fb632bSRamuthevar Vadivel Murugan const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
118431fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase;
118531fb632bSRamuthevar Vadivel Murugan u32 reg, div;
118631fb632bSRamuthevar Vadivel Murugan
118731fb632bSRamuthevar Vadivel Murugan /* Recalculate the baudrate divisor based on QSPI specification. */
118831fb632bSRamuthevar Vadivel Murugan div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
118931fb632bSRamuthevar Vadivel Murugan
1190f8fc65e5SNathan Barrett-Morrison /* Maximum baud divisor */
1191f8fc65e5SNathan Barrett-Morrison if (div > CQSPI_REG_CONFIG_BAUD_MASK) {
1192f8fc65e5SNathan Barrett-Morrison div = CQSPI_REG_CONFIG_BAUD_MASK;
1193f8fc65e5SNathan Barrett-Morrison dev_warn(&cqspi->pdev->dev,
1194f8fc65e5SNathan Barrett-Morrison "Unable to adjust clock <= %d hz. Reduced to %d hz\n",
1195f8fc65e5SNathan Barrett-Morrison cqspi->sclk, ref_clk_hz/((div+1)*2));
1196f8fc65e5SNathan Barrett-Morrison }
1197f8fc65e5SNathan Barrett-Morrison
119831fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_CONFIG);
119931fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
120031fb632bSRamuthevar Vadivel Murugan reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
120131fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_CONFIG);
120231fb632bSRamuthevar Vadivel Murugan }
120331fb632bSRamuthevar Vadivel Murugan
cqspi_readdata_capture(struct cqspi_st * cqspi,const bool bypass,const unsigned int delay)120431fb632bSRamuthevar Vadivel Murugan static void cqspi_readdata_capture(struct cqspi_st *cqspi,
120531fb632bSRamuthevar Vadivel Murugan const bool bypass,
120631fb632bSRamuthevar Vadivel Murugan const unsigned int delay)
120731fb632bSRamuthevar Vadivel Murugan {
120831fb632bSRamuthevar Vadivel Murugan void __iomem *reg_base = cqspi->iobase;
120931fb632bSRamuthevar Vadivel Murugan unsigned int reg;
121031fb632bSRamuthevar Vadivel Murugan
121131fb632bSRamuthevar Vadivel Murugan reg = readl(reg_base + CQSPI_REG_READCAPTURE);
121231fb632bSRamuthevar Vadivel Murugan
121331fb632bSRamuthevar Vadivel Murugan if (bypass)
121431fb632bSRamuthevar Vadivel Murugan reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
121531fb632bSRamuthevar Vadivel Murugan else
121631fb632bSRamuthevar Vadivel Murugan reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
121731fb632bSRamuthevar Vadivel Murugan
121831fb632bSRamuthevar Vadivel Murugan reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
121931fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_READCAPTURE_DELAY_LSB);
122031fb632bSRamuthevar Vadivel Murugan
122131fb632bSRamuthevar Vadivel Murugan reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
122231fb632bSRamuthevar Vadivel Murugan << CQSPI_REG_READCAPTURE_DELAY_LSB;
122331fb632bSRamuthevar Vadivel Murugan
122431fb632bSRamuthevar Vadivel Murugan writel(reg, reg_base + CQSPI_REG_READCAPTURE);
122531fb632bSRamuthevar Vadivel Murugan }
122631fb632bSRamuthevar Vadivel Murugan
cqspi_configure(struct cqspi_flash_pdata * f_pdata,unsigned long sclk)122731fb632bSRamuthevar Vadivel Murugan static void cqspi_configure(struct cqspi_flash_pdata *f_pdata,
122831fb632bSRamuthevar Vadivel Murugan unsigned long sclk)
122931fb632bSRamuthevar Vadivel Murugan {
123031fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi;
123131fb632bSRamuthevar Vadivel Murugan int switch_cs = (cqspi->current_cs != f_pdata->cs);
123231fb632bSRamuthevar Vadivel Murugan int switch_ck = (cqspi->sclk != sclk);
123331fb632bSRamuthevar Vadivel Murugan
123431fb632bSRamuthevar Vadivel Murugan if (switch_cs || switch_ck)
123531fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0);
123631fb632bSRamuthevar Vadivel Murugan
123731fb632bSRamuthevar Vadivel Murugan /* Switch chip select. */
123831fb632bSRamuthevar Vadivel Murugan if (switch_cs) {
123931fb632bSRamuthevar Vadivel Murugan cqspi->current_cs = f_pdata->cs;
124031fb632bSRamuthevar Vadivel Murugan cqspi_chipselect(f_pdata);
124131fb632bSRamuthevar Vadivel Murugan }
124231fb632bSRamuthevar Vadivel Murugan
124331fb632bSRamuthevar Vadivel Murugan /* Setup baudrate divisor and delays */
124431fb632bSRamuthevar Vadivel Murugan if (switch_ck) {
124531fb632bSRamuthevar Vadivel Murugan cqspi->sclk = sclk;
124631fb632bSRamuthevar Vadivel Murugan cqspi_config_baudrate_div(cqspi);
124731fb632bSRamuthevar Vadivel Murugan cqspi_delay(f_pdata);
124831fb632bSRamuthevar Vadivel Murugan cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
124931fb632bSRamuthevar Vadivel Murugan f_pdata->read_delay);
125031fb632bSRamuthevar Vadivel Murugan }
125131fb632bSRamuthevar Vadivel Murugan
125231fb632bSRamuthevar Vadivel Murugan if (switch_cs || switch_ck)
125331fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1);
125431fb632bSRamuthevar Vadivel Murugan }
125531fb632bSRamuthevar Vadivel Murugan
cqspi_write(struct cqspi_flash_pdata * f_pdata,const struct spi_mem_op * op)125631fb632bSRamuthevar Vadivel Murugan static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata,
125731fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op)
125831fb632bSRamuthevar Vadivel Murugan {
125931fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi;
126031fb632bSRamuthevar Vadivel Murugan loff_t to = op->addr.val;
126131fb632bSRamuthevar Vadivel Murugan size_t len = op->data.nbytes;
126231fb632bSRamuthevar Vadivel Murugan const u_char *buf = op->data.buf.out;
126331fb632bSRamuthevar Vadivel Murugan int ret;
126431fb632bSRamuthevar Vadivel Murugan
126531fb632bSRamuthevar Vadivel Murugan ret = cqspi_write_setup(f_pdata, op);
126631fb632bSRamuthevar Vadivel Murugan if (ret)
126731fb632bSRamuthevar Vadivel Murugan return ret;
126831fb632bSRamuthevar Vadivel Murugan
1269f453f293SPratyush Yadav /*
1270f453f293SPratyush Yadav * Some flashes like the Cypress Semper flash expect a dummy 4-byte
1271f453f293SPratyush Yadav * address (all 0s) with the read status register command in DTR mode.
1272f453f293SPratyush Yadav * But this controller does not support sending dummy address bytes to
1273f453f293SPratyush Yadav * the flash when it is polling the write completion register in DTR
1274f453f293SPratyush Yadav * mode. So, we can not use direct mode when in DTR mode for writing
1275f453f293SPratyush Yadav * data.
1276f453f293SPratyush Yadav */
127728ac902aSMatthias Schiffer if (!op->cmd.dtr && cqspi->use_direct_mode &&
1278e8c51b16SDhruva Gole cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) {
127931fb632bSRamuthevar Vadivel Murugan memcpy_toio(cqspi->ahb_base + to, buf, len);
128031fb632bSRamuthevar Vadivel Murugan return cqspi_wait_idle(cqspi);
128131fb632bSRamuthevar Vadivel Murugan }
128231fb632bSRamuthevar Vadivel Murugan
128331fb632bSRamuthevar Vadivel Murugan return cqspi_indirect_write_execute(f_pdata, to, buf, len);
128431fb632bSRamuthevar Vadivel Murugan }
128531fb632bSRamuthevar Vadivel Murugan
cqspi_rx_dma_callback(void * param)128631fb632bSRamuthevar Vadivel Murugan static void cqspi_rx_dma_callback(void *param)
128731fb632bSRamuthevar Vadivel Murugan {
128831fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = param;
128931fb632bSRamuthevar Vadivel Murugan
129031fb632bSRamuthevar Vadivel Murugan complete(&cqspi->rx_dma_complete);
129131fb632bSRamuthevar Vadivel Murugan }
129231fb632bSRamuthevar Vadivel Murugan
cqspi_direct_read_execute(struct cqspi_flash_pdata * f_pdata,u_char * buf,loff_t from,size_t len)129331fb632bSRamuthevar Vadivel Murugan static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata,
129431fb632bSRamuthevar Vadivel Murugan u_char *buf, loff_t from, size_t len)
129531fb632bSRamuthevar Vadivel Murugan {
129631fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi;
129731fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev;
129831fb632bSRamuthevar Vadivel Murugan enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
129931fb632bSRamuthevar Vadivel Murugan dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from;
130031fb632bSRamuthevar Vadivel Murugan int ret = 0;
130131fb632bSRamuthevar Vadivel Murugan struct dma_async_tx_descriptor *tx;
130231fb632bSRamuthevar Vadivel Murugan dma_cookie_t cookie;
130331fb632bSRamuthevar Vadivel Murugan dma_addr_t dma_dst;
130483048015SVignesh Raghavendra struct device *ddev;
130531fb632bSRamuthevar Vadivel Murugan
130631fb632bSRamuthevar Vadivel Murugan if (!cqspi->rx_chan || !virt_addr_valid(buf)) {
130731fb632bSRamuthevar Vadivel Murugan memcpy_fromio(buf, cqspi->ahb_base + from, len);
130831fb632bSRamuthevar Vadivel Murugan return 0;
130931fb632bSRamuthevar Vadivel Murugan }
131031fb632bSRamuthevar Vadivel Murugan
131183048015SVignesh Raghavendra ddev = cqspi->rx_chan->device->dev;
131283048015SVignesh Raghavendra dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE);
131383048015SVignesh Raghavendra if (dma_mapping_error(ddev, dma_dst)) {
131431fb632bSRamuthevar Vadivel Murugan dev_err(dev, "dma mapping failed\n");
131531fb632bSRamuthevar Vadivel Murugan return -ENOMEM;
131631fb632bSRamuthevar Vadivel Murugan }
131731fb632bSRamuthevar Vadivel Murugan tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src,
131831fb632bSRamuthevar Vadivel Murugan len, flags);
131931fb632bSRamuthevar Vadivel Murugan if (!tx) {
132031fb632bSRamuthevar Vadivel Murugan dev_err(dev, "device_prep_dma_memcpy error\n");
132131fb632bSRamuthevar Vadivel Murugan ret = -EIO;
132231fb632bSRamuthevar Vadivel Murugan goto err_unmap;
132331fb632bSRamuthevar Vadivel Murugan }
132431fb632bSRamuthevar Vadivel Murugan
132531fb632bSRamuthevar Vadivel Murugan tx->callback = cqspi_rx_dma_callback;
132631fb632bSRamuthevar Vadivel Murugan tx->callback_param = cqspi;
132731fb632bSRamuthevar Vadivel Murugan cookie = tx->tx_submit(tx);
132831fb632bSRamuthevar Vadivel Murugan reinit_completion(&cqspi->rx_dma_complete);
132931fb632bSRamuthevar Vadivel Murugan
133031fb632bSRamuthevar Vadivel Murugan ret = dma_submit_error(cookie);
133131fb632bSRamuthevar Vadivel Murugan if (ret) {
133231fb632bSRamuthevar Vadivel Murugan dev_err(dev, "dma_submit_error %d\n", cookie);
133331fb632bSRamuthevar Vadivel Murugan ret = -EIO;
133431fb632bSRamuthevar Vadivel Murugan goto err_unmap;
133531fb632bSRamuthevar Vadivel Murugan }
133631fb632bSRamuthevar Vadivel Murugan
133731fb632bSRamuthevar Vadivel Murugan dma_async_issue_pending(cqspi->rx_chan);
133831fb632bSRamuthevar Vadivel Murugan if (!wait_for_completion_timeout(&cqspi->rx_dma_complete,
13392ef0170eSPratyush Yadav msecs_to_jiffies(max_t(size_t, len, 500)))) {
134031fb632bSRamuthevar Vadivel Murugan dmaengine_terminate_sync(cqspi->rx_chan);
134131fb632bSRamuthevar Vadivel Murugan dev_err(dev, "DMA wait_for_completion_timeout\n");
134231fb632bSRamuthevar Vadivel Murugan ret = -ETIMEDOUT;
134331fb632bSRamuthevar Vadivel Murugan goto err_unmap;
134431fb632bSRamuthevar Vadivel Murugan }
134531fb632bSRamuthevar Vadivel Murugan
134631fb632bSRamuthevar Vadivel Murugan err_unmap:
134783048015SVignesh Raghavendra dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE);
134831fb632bSRamuthevar Vadivel Murugan
134931fb632bSRamuthevar Vadivel Murugan return ret;
135031fb632bSRamuthevar Vadivel Murugan }
135131fb632bSRamuthevar Vadivel Murugan
cqspi_read(struct cqspi_flash_pdata * f_pdata,const struct spi_mem_op * op)135231fb632bSRamuthevar Vadivel Murugan static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata,
135331fb632bSRamuthevar Vadivel Murugan const struct spi_mem_op *op)
135431fb632bSRamuthevar Vadivel Murugan {
135531fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = f_pdata->cqspi;
13561a6f854fSSai Krishna Potthuri struct device *dev = &cqspi->pdev->dev;
13571a6f854fSSai Krishna Potthuri const struct cqspi_driver_platdata *ddata;
135831fb632bSRamuthevar Vadivel Murugan loff_t from = op->addr.val;
135931fb632bSRamuthevar Vadivel Murugan size_t len = op->data.nbytes;
136031fb632bSRamuthevar Vadivel Murugan u_char *buf = op->data.buf.in;
13611a6f854fSSai Krishna Potthuri u64 dma_align = (u64)(uintptr_t)buf;
136231fb632bSRamuthevar Vadivel Murugan int ret;
136331fb632bSRamuthevar Vadivel Murugan
13641a6f854fSSai Krishna Potthuri ddata = of_device_get_match_data(dev);
136531fb632bSRamuthevar Vadivel Murugan
136631fb632bSRamuthevar Vadivel Murugan ret = cqspi_read_setup(f_pdata, op);
136731fb632bSRamuthevar Vadivel Murugan if (ret)
136831fb632bSRamuthevar Vadivel Murugan return ret;
136931fb632bSRamuthevar Vadivel Murugan
137031fb632bSRamuthevar Vadivel Murugan if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size))
137131fb632bSRamuthevar Vadivel Murugan return cqspi_direct_read_execute(f_pdata, buf, from, len);
137231fb632bSRamuthevar Vadivel Murugan
13731a6f854fSSai Krishna Potthuri if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma &&
13741a6f854fSSai Krishna Potthuri virt_addr_valid(buf) && ((dma_align & CQSPI_DMA_UNALIGN) == 0))
13751a6f854fSSai Krishna Potthuri return ddata->indirect_read_dma(f_pdata, buf, from, len);
13761a6f854fSSai Krishna Potthuri
137731fb632bSRamuthevar Vadivel Murugan return cqspi_indirect_read_execute(f_pdata, buf, from, len);
137831fb632bSRamuthevar Vadivel Murugan }
137931fb632bSRamuthevar Vadivel Murugan
cqspi_mem_process(struct spi_mem * mem,const struct spi_mem_op * op)138031fb632bSRamuthevar Vadivel Murugan static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op)
138131fb632bSRamuthevar Vadivel Murugan {
13821c75d749SYang Yingliang struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller);
138331fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata;
138431fb632bSRamuthevar Vadivel Murugan
13859e264f3fSAmit Kumar Mahapatra via Alsa-devel f_pdata = &cqspi->f_pdata[spi_get_chipselect(mem->spi, 0)];
138631fb632bSRamuthevar Vadivel Murugan cqspi_configure(f_pdata, mem->spi->max_speed_hz);
138731fb632bSRamuthevar Vadivel Murugan
138831fb632bSRamuthevar Vadivel Murugan if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
1389d403fb6eSDhruva Gole /*
1390d403fb6eSDhruva Gole * Performing reads in DAC mode forces to read minimum 4 bytes
1391d403fb6eSDhruva Gole * which is unsupported on some flash devices during register
1392d403fb6eSDhruva Gole * reads, prefer STIG mode for such small reads.
1393d403fb6eSDhruva Gole */
1394d403fb6eSDhruva Gole if (!op->addr.nbytes ||
1395d403fb6eSDhruva Gole op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
139631fb632bSRamuthevar Vadivel Murugan return cqspi_command_read(f_pdata, op);
139731fb632bSRamuthevar Vadivel Murugan
139831fb632bSRamuthevar Vadivel Murugan return cqspi_read(f_pdata, op);
139931fb632bSRamuthevar Vadivel Murugan }
140031fb632bSRamuthevar Vadivel Murugan
140131fb632bSRamuthevar Vadivel Murugan if (!op->addr.nbytes || !op->data.buf.out)
140231fb632bSRamuthevar Vadivel Murugan return cqspi_command_write(f_pdata, op);
140331fb632bSRamuthevar Vadivel Murugan
140431fb632bSRamuthevar Vadivel Murugan return cqspi_write(f_pdata, op);
140531fb632bSRamuthevar Vadivel Murugan }
140631fb632bSRamuthevar Vadivel Murugan
cqspi_exec_mem_op(struct spi_mem * mem,const struct spi_mem_op * op)140731fb632bSRamuthevar Vadivel Murugan static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
140831fb632bSRamuthevar Vadivel Murugan {
140931fb632bSRamuthevar Vadivel Murugan int ret;
141031fb632bSRamuthevar Vadivel Murugan
141131fb632bSRamuthevar Vadivel Murugan ret = cqspi_mem_process(mem, op);
141231fb632bSRamuthevar Vadivel Murugan if (ret)
141331fb632bSRamuthevar Vadivel Murugan dev_err(&mem->spi->dev, "operation failed with %d\n", ret);
141431fb632bSRamuthevar Vadivel Murugan
141531fb632bSRamuthevar Vadivel Murugan return ret;
141631fb632bSRamuthevar Vadivel Murugan }
141731fb632bSRamuthevar Vadivel Murugan
cqspi_supports_mem_op(struct spi_mem * mem,const struct spi_mem_op * op)1418a273596bSPratyush Yadav static bool cqspi_supports_mem_op(struct spi_mem *mem,
1419a273596bSPratyush Yadav const struct spi_mem_op *op)
1420a273596bSPratyush Yadav {
1421f453f293SPratyush Yadav bool all_true, all_false;
1422f453f293SPratyush Yadav
14230395be96SApurva Nandan /*
14240395be96SApurva Nandan * op->dummy.dtr is required for converting nbytes into ncycles.
14250395be96SApurva Nandan * Also, don't check the dtr field of the op phase having zero nbytes.
14260395be96SApurva Nandan */
14270395be96SApurva Nandan all_true = op->cmd.dtr &&
14280395be96SApurva Nandan (!op->addr.nbytes || op->addr.dtr) &&
14290395be96SApurva Nandan (!op->dummy.nbytes || op->dummy.dtr) &&
14300395be96SApurva Nandan (!op->data.nbytes || op->data.dtr);
14310395be96SApurva Nandan
1432f453f293SPratyush Yadav all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
1433f453f293SPratyush Yadav !op->data.dtr;
1434f453f293SPratyush Yadav
1435f1d388f2SMatthias Schiffer if (all_true) {
1436f1d388f2SMatthias Schiffer /* Right now we only support 8-8-8 DTR mode. */
1437f1d388f2SMatthias Schiffer if (op->cmd.nbytes && op->cmd.buswidth != 8)
1438f453f293SPratyush Yadav return false;
1439f1d388f2SMatthias Schiffer if (op->addr.nbytes && op->addr.buswidth != 8)
1440f1d388f2SMatthias Schiffer return false;
1441f1d388f2SMatthias Schiffer if (op->data.nbytes && op->data.buswidth != 8)
1442f1d388f2SMatthias Schiffer return false;
14431aeda096SMatthias Schiffer } else if (!all_false) {
1444f1d388f2SMatthias Schiffer /* Mixed DTR modes are not supported. */
1445f1d388f2SMatthias Schiffer return false;
1446f1d388f2SMatthias Schiffer }
1447f453f293SPratyush Yadav
1448d2275139SPratyush Yadav return spi_mem_default_supports_op(mem, op);
1449a273596bSPratyush Yadav }
1450a273596bSPratyush Yadav
cqspi_of_get_flash_pdata(struct platform_device * pdev,struct cqspi_flash_pdata * f_pdata,struct device_node * np)145131fb632bSRamuthevar Vadivel Murugan static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
145231fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata,
145331fb632bSRamuthevar Vadivel Murugan struct device_node *np)
145431fb632bSRamuthevar Vadivel Murugan {
145531fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
145631fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine read-delay\n");
145731fb632bSRamuthevar Vadivel Murugan return -ENXIO;
145831fb632bSRamuthevar Vadivel Murugan }
145931fb632bSRamuthevar Vadivel Murugan
146031fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
146131fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
146231fb632bSRamuthevar Vadivel Murugan return -ENXIO;
146331fb632bSRamuthevar Vadivel Murugan }
146431fb632bSRamuthevar Vadivel Murugan
146531fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
146631fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
146731fb632bSRamuthevar Vadivel Murugan return -ENXIO;
146831fb632bSRamuthevar Vadivel Murugan }
146931fb632bSRamuthevar Vadivel Murugan
147031fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
147131fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
147231fb632bSRamuthevar Vadivel Murugan return -ENXIO;
147331fb632bSRamuthevar Vadivel Murugan }
147431fb632bSRamuthevar Vadivel Murugan
147531fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
147631fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
147731fb632bSRamuthevar Vadivel Murugan return -ENXIO;
147831fb632bSRamuthevar Vadivel Murugan }
147931fb632bSRamuthevar Vadivel Murugan
148031fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
148131fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
148231fb632bSRamuthevar Vadivel Murugan return -ENXIO;
148331fb632bSRamuthevar Vadivel Murugan }
148431fb632bSRamuthevar Vadivel Murugan
148531fb632bSRamuthevar Vadivel Murugan return 0;
148631fb632bSRamuthevar Vadivel Murugan }
148731fb632bSRamuthevar Vadivel Murugan
cqspi_of_get_pdata(struct cqspi_st * cqspi)148831fb632bSRamuthevar Vadivel Murugan static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
148931fb632bSRamuthevar Vadivel Murugan {
149031fb632bSRamuthevar Vadivel Murugan struct device *dev = &cqspi->pdev->dev;
149131fb632bSRamuthevar Vadivel Murugan struct device_node *np = dev->of_node;
149209e393e3SSai Krishna Potthuri u32 id[2];
149331fb632bSRamuthevar Vadivel Murugan
149431fb632bSRamuthevar Vadivel Murugan cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
149531fb632bSRamuthevar Vadivel Murugan
149631fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
149731fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine fifo-depth\n");
149831fb632bSRamuthevar Vadivel Murugan return -ENXIO;
149931fb632bSRamuthevar Vadivel Murugan }
150031fb632bSRamuthevar Vadivel Murugan
150131fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
150231fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine fifo-width\n");
150331fb632bSRamuthevar Vadivel Murugan return -ENXIO;
150431fb632bSRamuthevar Vadivel Murugan }
150531fb632bSRamuthevar Vadivel Murugan
150631fb632bSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "cdns,trigger-address",
150731fb632bSRamuthevar Vadivel Murugan &cqspi->trigger_address)) {
150831fb632bSRamuthevar Vadivel Murugan dev_err(dev, "couldn't determine trigger-address\n");
150931fb632bSRamuthevar Vadivel Murugan return -ENXIO;
151031fb632bSRamuthevar Vadivel Murugan }
151131fb632bSRamuthevar Vadivel Murugan
1512b436fb7dSRamuthevar Vadivel Murugan if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect))
1513b436fb7dSRamuthevar Vadivel Murugan cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT;
1514b436fb7dSRamuthevar Vadivel Murugan
151531fb632bSRamuthevar Vadivel Murugan cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
151631fb632bSRamuthevar Vadivel Murugan
151709e393e3SSai Krishna Potthuri if (!of_property_read_u32_array(np, "power-domains", id,
151809e393e3SSai Krishna Potthuri ARRAY_SIZE(id)))
151909e393e3SSai Krishna Potthuri cqspi->pd_dev_id = id[1];
152009e393e3SSai Krishna Potthuri
152131fb632bSRamuthevar Vadivel Murugan return 0;
152231fb632bSRamuthevar Vadivel Murugan }
152331fb632bSRamuthevar Vadivel Murugan
cqspi_controller_init(struct cqspi_st * cqspi)152431fb632bSRamuthevar Vadivel Murugan static void cqspi_controller_init(struct cqspi_st *cqspi)
152531fb632bSRamuthevar Vadivel Murugan {
152631fb632bSRamuthevar Vadivel Murugan u32 reg;
152731fb632bSRamuthevar Vadivel Murugan
152831fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0);
152931fb632bSRamuthevar Vadivel Murugan
153031fb632bSRamuthevar Vadivel Murugan /* Configure the remap address register, no remap */
153131fb632bSRamuthevar Vadivel Murugan writel(0, cqspi->iobase + CQSPI_REG_REMAP);
153231fb632bSRamuthevar Vadivel Murugan
153331fb632bSRamuthevar Vadivel Murugan /* Disable all interrupts. */
153431fb632bSRamuthevar Vadivel Murugan writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
153531fb632bSRamuthevar Vadivel Murugan
153631fb632bSRamuthevar Vadivel Murugan /* Configure the SRAM split to 1:1 . */
153731fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
153831fb632bSRamuthevar Vadivel Murugan
153931fb632bSRamuthevar Vadivel Murugan /* Load indirect trigger address. */
154031fb632bSRamuthevar Vadivel Murugan writel(cqspi->trigger_address,
154131fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
154231fb632bSRamuthevar Vadivel Murugan
154331fb632bSRamuthevar Vadivel Murugan /* Program read watermark -- 1/2 of the FIFO. */
154431fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
154531fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
154631fb632bSRamuthevar Vadivel Murugan /* Program write watermark -- 1/8 of the FIFO. */
154731fb632bSRamuthevar Vadivel Murugan writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
154831fb632bSRamuthevar Vadivel Murugan cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
154931fb632bSRamuthevar Vadivel Murugan
1550ad2775dcSRamuthevar Vadivel Murugan /* Disable direct access controller */
1551ad2775dcSRamuthevar Vadivel Murugan if (!cqspi->use_direct_mode) {
155231fb632bSRamuthevar Vadivel Murugan reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1553ad2775dcSRamuthevar Vadivel Murugan reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
155431fb632bSRamuthevar Vadivel Murugan writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1555ad2775dcSRamuthevar Vadivel Murugan }
155631fb632bSRamuthevar Vadivel Murugan
15571a6f854fSSai Krishna Potthuri /* Enable DMA interface */
15581a6f854fSSai Krishna Potthuri if (cqspi->use_dma_read) {
15591a6f854fSSai Krishna Potthuri reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
15601a6f854fSSai Krishna Potthuri reg |= CQSPI_REG_CONFIG_DMA_MASK;
15611a6f854fSSai Krishna Potthuri writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
15621a6f854fSSai Krishna Potthuri }
15631a6f854fSSai Krishna Potthuri
156431fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 1);
156531fb632bSRamuthevar Vadivel Murugan }
156631fb632bSRamuthevar Vadivel Murugan
cqspi_request_mmap_dma(struct cqspi_st * cqspi)156731fb632bSRamuthevar Vadivel Murugan static int cqspi_request_mmap_dma(struct cqspi_st *cqspi)
156831fb632bSRamuthevar Vadivel Murugan {
156931fb632bSRamuthevar Vadivel Murugan dma_cap_mask_t mask;
157031fb632bSRamuthevar Vadivel Murugan
157131fb632bSRamuthevar Vadivel Murugan dma_cap_zero(mask);
157231fb632bSRamuthevar Vadivel Murugan dma_cap_set(DMA_MEMCPY, mask);
157331fb632bSRamuthevar Vadivel Murugan
157431fb632bSRamuthevar Vadivel Murugan cqspi->rx_chan = dma_request_chan_by_mask(&mask);
157531fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->rx_chan)) {
157631fb632bSRamuthevar Vadivel Murugan int ret = PTR_ERR(cqspi->rx_chan);
157776159e2fSIan Abbott
157831fb632bSRamuthevar Vadivel Murugan cqspi->rx_chan = NULL;
1579436a5c20SKrzysztof Kozlowski return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n");
158031fb632bSRamuthevar Vadivel Murugan }
158131fb632bSRamuthevar Vadivel Murugan init_completion(&cqspi->rx_dma_complete);
158231fb632bSRamuthevar Vadivel Murugan
158331fb632bSRamuthevar Vadivel Murugan return 0;
158431fb632bSRamuthevar Vadivel Murugan }
158531fb632bSRamuthevar Vadivel Murugan
cqspi_get_name(struct spi_mem * mem)15862ea370a9SVignesh Raghavendra static const char *cqspi_get_name(struct spi_mem *mem)
15872ea370a9SVignesh Raghavendra {
15881c75d749SYang Yingliang struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller);
15892ea370a9SVignesh Raghavendra struct device *dev = &cqspi->pdev->dev;
15902ea370a9SVignesh Raghavendra
15919e264f3fSAmit Kumar Mahapatra via Alsa-devel return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev),
15929e264f3fSAmit Kumar Mahapatra via Alsa-devel spi_get_chipselect(mem->spi, 0));
15932ea370a9SVignesh Raghavendra }
15942ea370a9SVignesh Raghavendra
159531fb632bSRamuthevar Vadivel Murugan static const struct spi_controller_mem_ops cqspi_mem_ops = {
159631fb632bSRamuthevar Vadivel Murugan .exec_op = cqspi_exec_mem_op,
15972ea370a9SVignesh Raghavendra .get_name = cqspi_get_name,
1598a273596bSPratyush Yadav .supports_op = cqspi_supports_mem_op,
159931fb632bSRamuthevar Vadivel Murugan };
160031fb632bSRamuthevar Vadivel Murugan
1601a9be4549SMiquel Raynal static const struct spi_controller_mem_caps cqspi_mem_caps = {
1602a9be4549SMiquel Raynal .dtr = true,
1603a9be4549SMiquel Raynal };
1604a9be4549SMiquel Raynal
cqspi_setup_flash(struct cqspi_st * cqspi)160531fb632bSRamuthevar Vadivel Murugan static int cqspi_setup_flash(struct cqspi_st *cqspi)
160631fb632bSRamuthevar Vadivel Murugan {
160731fb632bSRamuthevar Vadivel Murugan struct platform_device *pdev = cqspi->pdev;
160831fb632bSRamuthevar Vadivel Murugan struct device *dev = &pdev->dev;
160931fb632bSRamuthevar Vadivel Murugan struct device_node *np = dev->of_node;
161031fb632bSRamuthevar Vadivel Murugan struct cqspi_flash_pdata *f_pdata;
161131fb632bSRamuthevar Vadivel Murugan unsigned int cs;
161231fb632bSRamuthevar Vadivel Murugan int ret;
161331fb632bSRamuthevar Vadivel Murugan
161431fb632bSRamuthevar Vadivel Murugan /* Get flash device data */
161531fb632bSRamuthevar Vadivel Murugan for_each_available_child_of_node(dev->of_node, np) {
161631fb632bSRamuthevar Vadivel Murugan ret = of_property_read_u32(np, "reg", &cs);
161731fb632bSRamuthevar Vadivel Murugan if (ret) {
161831fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Couldn't determine chip select.\n");
161987d62d8fSJunlin Yang of_node_put(np);
162031fb632bSRamuthevar Vadivel Murugan return ret;
162131fb632bSRamuthevar Vadivel Murugan }
162231fb632bSRamuthevar Vadivel Murugan
162331fb632bSRamuthevar Vadivel Murugan if (cs >= CQSPI_MAX_CHIPSELECT) {
162431fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Chip select %d out of range.\n", cs);
162587d62d8fSJunlin Yang of_node_put(np);
162631fb632bSRamuthevar Vadivel Murugan return -EINVAL;
162731fb632bSRamuthevar Vadivel Murugan }
162831fb632bSRamuthevar Vadivel Murugan
162931fb632bSRamuthevar Vadivel Murugan f_pdata = &cqspi->f_pdata[cs];
163031fb632bSRamuthevar Vadivel Murugan f_pdata->cqspi = cqspi;
163131fb632bSRamuthevar Vadivel Murugan f_pdata->cs = cs;
163231fb632bSRamuthevar Vadivel Murugan
163331fb632bSRamuthevar Vadivel Murugan ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
163487d62d8fSJunlin Yang if (ret) {
163587d62d8fSJunlin Yang of_node_put(np);
163631fb632bSRamuthevar Vadivel Murugan return ret;
163731fb632bSRamuthevar Vadivel Murugan }
163887d62d8fSJunlin Yang }
163931fb632bSRamuthevar Vadivel Murugan
164031fb632bSRamuthevar Vadivel Murugan return 0;
164131fb632bSRamuthevar Vadivel Murugan }
164231fb632bSRamuthevar Vadivel Murugan
cqspi_jh7110_clk_init(struct platform_device * pdev,struct cqspi_st * cqspi)164333f1ef6dSWilliam Qiu static int cqspi_jh7110_clk_init(struct platform_device *pdev, struct cqspi_st *cqspi)
164433f1ef6dSWilliam Qiu {
164533f1ef6dSWilliam Qiu static struct clk_bulk_data qspiclk[] = {
164633f1ef6dSWilliam Qiu { .id = "apb" },
164733f1ef6dSWilliam Qiu { .id = "ahb" },
164833f1ef6dSWilliam Qiu };
164933f1ef6dSWilliam Qiu
165033f1ef6dSWilliam Qiu int ret = 0;
165133f1ef6dSWilliam Qiu
165233f1ef6dSWilliam Qiu ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(qspiclk), qspiclk);
165333f1ef6dSWilliam Qiu if (ret) {
165433f1ef6dSWilliam Qiu dev_err(&pdev->dev, "%s: failed to get qspi clocks\n", __func__);
165533f1ef6dSWilliam Qiu return ret;
165633f1ef6dSWilliam Qiu }
165733f1ef6dSWilliam Qiu
165833f1ef6dSWilliam Qiu cqspi->clks[CLK_QSPI_APB] = qspiclk[0].clk;
165933f1ef6dSWilliam Qiu cqspi->clks[CLK_QSPI_AHB] = qspiclk[1].clk;
166033f1ef6dSWilliam Qiu
166133f1ef6dSWilliam Qiu ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_APB]);
166233f1ef6dSWilliam Qiu if (ret) {
166333f1ef6dSWilliam Qiu dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_APB\n", __func__);
166433f1ef6dSWilliam Qiu return ret;
166533f1ef6dSWilliam Qiu }
166633f1ef6dSWilliam Qiu
166733f1ef6dSWilliam Qiu ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_AHB]);
166833f1ef6dSWilliam Qiu if (ret) {
166933f1ef6dSWilliam Qiu dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_AHB\n", __func__);
167033f1ef6dSWilliam Qiu goto disable_apb_clk;
167133f1ef6dSWilliam Qiu }
167233f1ef6dSWilliam Qiu
167333f1ef6dSWilliam Qiu cqspi->is_jh7110 = true;
167433f1ef6dSWilliam Qiu
167533f1ef6dSWilliam Qiu return 0;
167633f1ef6dSWilliam Qiu
167733f1ef6dSWilliam Qiu disable_apb_clk:
167833f1ef6dSWilliam Qiu clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]);
167933f1ef6dSWilliam Qiu
168033f1ef6dSWilliam Qiu return ret;
168133f1ef6dSWilliam Qiu }
168233f1ef6dSWilliam Qiu
cqspi_jh7110_disable_clk(struct platform_device * pdev,struct cqspi_st * cqspi)168333f1ef6dSWilliam Qiu static void cqspi_jh7110_disable_clk(struct platform_device *pdev, struct cqspi_st *cqspi)
168433f1ef6dSWilliam Qiu {
168533f1ef6dSWilliam Qiu clk_disable_unprepare(cqspi->clks[CLK_QSPI_AHB]);
168633f1ef6dSWilliam Qiu clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]);
168733f1ef6dSWilliam Qiu }
cqspi_probe(struct platform_device * pdev)168831fb632bSRamuthevar Vadivel Murugan static int cqspi_probe(struct platform_device *pdev)
168931fb632bSRamuthevar Vadivel Murugan {
169031fb632bSRamuthevar Vadivel Murugan const struct cqspi_driver_platdata *ddata;
169147fef94aSWilliam Qiu struct reset_control *rstc, *rstc_ocp, *rstc_ref;
169231fb632bSRamuthevar Vadivel Murugan struct device *dev = &pdev->dev;
16931c75d749SYang Yingliang struct spi_controller *host;
169431fb632bSRamuthevar Vadivel Murugan struct resource *res_ahb;
169531fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi;
169631fb632bSRamuthevar Vadivel Murugan int ret;
169731fb632bSRamuthevar Vadivel Murugan int irq;
169831fb632bSRamuthevar Vadivel Murugan
16991c75d749SYang Yingliang host = devm_spi_alloc_host(&pdev->dev, sizeof(*cqspi));
17001c75d749SYang Yingliang if (!host) {
17011c75d749SYang Yingliang dev_err(&pdev->dev, "devm_spi_alloc_host failed\n");
170231fb632bSRamuthevar Vadivel Murugan return -ENOMEM;
170331fb632bSRamuthevar Vadivel Murugan }
17041c75d749SYang Yingliang host->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL;
17051c75d749SYang Yingliang host->mem_ops = &cqspi_mem_ops;
17061c75d749SYang Yingliang host->mem_caps = &cqspi_mem_caps;
17071c75d749SYang Yingliang host->dev.of_node = pdev->dev.of_node;
170831fb632bSRamuthevar Vadivel Murugan
17091c75d749SYang Yingliang cqspi = spi_controller_get_devdata(host);
171031fb632bSRamuthevar Vadivel Murugan
171131fb632bSRamuthevar Vadivel Murugan cqspi->pdev = pdev;
17121c75d749SYang Yingliang cqspi->host = host;
171333f1ef6dSWilliam Qiu cqspi->is_jh7110 = false;
1714ea94191eSMeng Li platform_set_drvdata(pdev, cqspi);
171531fb632bSRamuthevar Vadivel Murugan
171631fb632bSRamuthevar Vadivel Murugan /* Obtain configuration from OF. */
171731fb632bSRamuthevar Vadivel Murugan ret = cqspi_of_get_pdata(cqspi);
171831fb632bSRamuthevar Vadivel Murugan if (ret) {
171931fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get mandatory OF data.\n");
172073d5fe04SVaishnav Achath return -ENODEV;
172131fb632bSRamuthevar Vadivel Murugan }
172231fb632bSRamuthevar Vadivel Murugan
172331fb632bSRamuthevar Vadivel Murugan /* Obtain QSPI clock. */
172431fb632bSRamuthevar Vadivel Murugan cqspi->clk = devm_clk_get(dev, NULL);
172531fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->clk)) {
172631fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot claim QSPI clock.\n");
172731fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->clk);
172873d5fe04SVaishnav Achath return ret;
172931fb632bSRamuthevar Vadivel Murugan }
173031fb632bSRamuthevar Vadivel Murugan
173131fb632bSRamuthevar Vadivel Murugan /* Obtain and remap controller address. */
17324e12ef2bSYang Yingliang cqspi->iobase = devm_platform_ioremap_resource(pdev, 0);
173331fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->iobase)) {
173431fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot remap controller address.\n");
173531fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->iobase);
173673d5fe04SVaishnav Achath return ret;
173731fb632bSRamuthevar Vadivel Murugan }
173831fb632bSRamuthevar Vadivel Murugan
173931fb632bSRamuthevar Vadivel Murugan /* Obtain and remap AHB address. */
17404e12ef2bSYang Yingliang cqspi->ahb_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res_ahb);
174131fb632bSRamuthevar Vadivel Murugan if (IS_ERR(cqspi->ahb_base)) {
174231fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot remap AHB address.\n");
174331fb632bSRamuthevar Vadivel Murugan ret = PTR_ERR(cqspi->ahb_base);
174473d5fe04SVaishnav Achath return ret;
174531fb632bSRamuthevar Vadivel Murugan }
174631fb632bSRamuthevar Vadivel Murugan cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
174731fb632bSRamuthevar Vadivel Murugan cqspi->ahb_size = resource_size(res_ahb);
174831fb632bSRamuthevar Vadivel Murugan
174931fb632bSRamuthevar Vadivel Murugan init_completion(&cqspi->transfer_complete);
175031fb632bSRamuthevar Vadivel Murugan
175131fb632bSRamuthevar Vadivel Murugan /* Obtain IRQ line. */
175231fb632bSRamuthevar Vadivel Murugan irq = platform_get_irq(pdev, 0);
175373d5fe04SVaishnav Achath if (irq < 0)
175473d5fe04SVaishnav Achath return -ENXIO;
175531fb632bSRamuthevar Vadivel Murugan
175631fb632bSRamuthevar Vadivel Murugan pm_runtime_enable(dev);
1757b7be05d5SMinghao Chi ret = pm_runtime_resume_and_get(dev);
1758b7be05d5SMinghao Chi if (ret < 0)
17594d0ef0a1SZhang Qilong goto probe_pm_failed;
176031fb632bSRamuthevar Vadivel Murugan
176131fb632bSRamuthevar Vadivel Murugan ret = clk_prepare_enable(cqspi->clk);
176231fb632bSRamuthevar Vadivel Murugan if (ret) {
176331fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot enable QSPI clock.\n");
176431fb632bSRamuthevar Vadivel Murugan goto probe_clk_failed;
176531fb632bSRamuthevar Vadivel Murugan }
176631fb632bSRamuthevar Vadivel Murugan
176731fb632bSRamuthevar Vadivel Murugan /* Obtain QSPI reset control */
176831fb632bSRamuthevar Vadivel Murugan rstc = devm_reset_control_get_optional_exclusive(dev, "qspi");
176931fb632bSRamuthevar Vadivel Murugan if (IS_ERR(rstc)) {
1770ac9978fcSZhihao Cheng ret = PTR_ERR(rstc);
177131fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get QSPI reset.\n");
177231fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed;
177331fb632bSRamuthevar Vadivel Murugan }
177431fb632bSRamuthevar Vadivel Murugan
177531fb632bSRamuthevar Vadivel Murugan rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp");
177631fb632bSRamuthevar Vadivel Murugan if (IS_ERR(rstc_ocp)) {
1777ac9978fcSZhihao Cheng ret = PTR_ERR(rstc_ocp);
177831fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot get QSPI OCP reset.\n");
177931fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed;
178031fb632bSRamuthevar Vadivel Murugan }
178131fb632bSRamuthevar Vadivel Murugan
178247fef94aSWilliam Qiu if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) {
178347fef94aSWilliam Qiu rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref");
178447fef94aSWilliam Qiu if (IS_ERR(rstc_ref)) {
178547fef94aSWilliam Qiu ret = PTR_ERR(rstc_ref);
178647fef94aSWilliam Qiu dev_err(dev, "Cannot get QSPI REF reset.\n");
178747fef94aSWilliam Qiu goto probe_reset_failed;
178847fef94aSWilliam Qiu }
178947fef94aSWilliam Qiu reset_control_assert(rstc_ref);
179047fef94aSWilliam Qiu reset_control_deassert(rstc_ref);
179147fef94aSWilliam Qiu }
179247fef94aSWilliam Qiu
179331fb632bSRamuthevar Vadivel Murugan reset_control_assert(rstc);
179431fb632bSRamuthevar Vadivel Murugan reset_control_deassert(rstc);
179531fb632bSRamuthevar Vadivel Murugan
179631fb632bSRamuthevar Vadivel Murugan reset_control_assert(rstc_ocp);
179731fb632bSRamuthevar Vadivel Murugan reset_control_deassert(rstc_ocp);
179831fb632bSRamuthevar Vadivel Murugan
179931fb632bSRamuthevar Vadivel Murugan cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
18001c75d749SYang Yingliang host->max_speed_hz = cqspi->master_ref_clk_hz;
180198d948ebSDinh Nguyen
180298d948ebSDinh Nguyen /* write completion is supported by default */
180398d948ebSDinh Nguyen cqspi->wr_completion = true;
180498d948ebSDinh Nguyen
180531fb632bSRamuthevar Vadivel Murugan ddata = of_device_get_match_data(dev);
180631fb632bSRamuthevar Vadivel Murugan if (ddata) {
180731fb632bSRamuthevar Vadivel Murugan if (ddata->quirks & CQSPI_NEEDS_WR_DELAY)
1808f453f293SPratyush Yadav cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC,
180931fb632bSRamuthevar Vadivel Murugan cqspi->master_ref_clk_hz);
181031fb632bSRamuthevar Vadivel Murugan if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL)
18111c75d749SYang Yingliang host->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL;
1812e8c51b16SDhruva Gole if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) {
181331fb632bSRamuthevar Vadivel Murugan cqspi->use_direct_mode = true;
1814e8c51b16SDhruva Gole cqspi->use_direct_mode_wr = true;
1815e8c51b16SDhruva Gole }
18161a6f854fSSai Krishna Potthuri if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA)
18171a6f854fSSai Krishna Potthuri cqspi->use_dma_read = true;
181898d948ebSDinh Nguyen if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION)
181998d948ebSDinh Nguyen cqspi->wr_completion = false;
18209ee5b6d5SNiravkumar L Rabara if (ddata->quirks & CQSPI_SLOW_SRAM)
18219ee5b6d5SNiravkumar L Rabara cqspi->slow_sram = true;
1822f5c2f9f9SBrad Larson if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR)
1823f5c2f9f9SBrad Larson cqspi->apb_ahb_hazard = true;
18241a6f854fSSai Krishna Potthuri
182533f1ef6dSWilliam Qiu if (ddata->jh7110_clk_init) {
182633f1ef6dSWilliam Qiu ret = cqspi_jh7110_clk_init(pdev, cqspi);
182733f1ef6dSWilliam Qiu if (ret)
1828b1432249SYang Yingliang goto probe_reset_failed;
182933f1ef6dSWilliam Qiu }
183033f1ef6dSWilliam Qiu
183109e393e3SSai Krishna Potthuri if (of_device_is_compatible(pdev->dev.of_node,
1832947c70a2SJiasheng Jiang "xlnx,versal-ospi-1.0")) {
1833947c70a2SJiasheng Jiang ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1834947c70a2SJiasheng Jiang if (ret)
1835947c70a2SJiasheng Jiang goto probe_reset_failed;
1836947c70a2SJiasheng Jiang }
183731fb632bSRamuthevar Vadivel Murugan }
183831fb632bSRamuthevar Vadivel Murugan
183931fb632bSRamuthevar Vadivel Murugan ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
184031fb632bSRamuthevar Vadivel Murugan pdev->name, cqspi);
184131fb632bSRamuthevar Vadivel Murugan if (ret) {
184231fb632bSRamuthevar Vadivel Murugan dev_err(dev, "Cannot request IRQ.\n");
184331fb632bSRamuthevar Vadivel Murugan goto probe_reset_failed;
184431fb632bSRamuthevar Vadivel Murugan }
184531fb632bSRamuthevar Vadivel Murugan
184631fb632bSRamuthevar Vadivel Murugan cqspi_wait_idle(cqspi);
184731fb632bSRamuthevar Vadivel Murugan cqspi_controller_init(cqspi);
184831fb632bSRamuthevar Vadivel Murugan cqspi->current_cs = -1;
184931fb632bSRamuthevar Vadivel Murugan cqspi->sclk = 0;
185031fb632bSRamuthevar Vadivel Murugan
18511c75d749SYang Yingliang host->num_chipselect = cqspi->num_chipselect;
1852b436fb7dSRamuthevar Vadivel Murugan
185331fb632bSRamuthevar Vadivel Murugan ret = cqspi_setup_flash(cqspi);
185431fb632bSRamuthevar Vadivel Murugan if (ret) {
185531fb632bSRamuthevar Vadivel Murugan dev_err(dev, "failed to setup flash parameters %d\n", ret);
185631fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed;
185731fb632bSRamuthevar Vadivel Murugan }
185831fb632bSRamuthevar Vadivel Murugan
185931fb632bSRamuthevar Vadivel Murugan if (cqspi->use_direct_mode) {
186031fb632bSRamuthevar Vadivel Murugan ret = cqspi_request_mmap_dma(cqspi);
186131fb632bSRamuthevar Vadivel Murugan if (ret == -EPROBE_DEFER)
186231fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed;
186331fb632bSRamuthevar Vadivel Murugan }
186431fb632bSRamuthevar Vadivel Murugan
18651c75d749SYang Yingliang ret = spi_register_controller(host);
186631fb632bSRamuthevar Vadivel Murugan if (ret) {
186731fb632bSRamuthevar Vadivel Murugan dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret);
186831fb632bSRamuthevar Vadivel Murugan goto probe_setup_failed;
186931fb632bSRamuthevar Vadivel Murugan }
187031fb632bSRamuthevar Vadivel Murugan
187131fb632bSRamuthevar Vadivel Murugan return 0;
187231fb632bSRamuthevar Vadivel Murugan probe_setup_failed:
187331fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0);
187431fb632bSRamuthevar Vadivel Murugan probe_reset_failed:
1875b1432249SYang Yingliang if (cqspi->is_jh7110)
1876b1432249SYang Yingliang cqspi_jh7110_disable_clk(pdev, cqspi);
187731fb632bSRamuthevar Vadivel Murugan clk_disable_unprepare(cqspi->clk);
187831fb632bSRamuthevar Vadivel Murugan probe_clk_failed:
187931fb632bSRamuthevar Vadivel Murugan pm_runtime_put_sync(dev);
18804d0ef0a1SZhang Qilong probe_pm_failed:
188131fb632bSRamuthevar Vadivel Murugan pm_runtime_disable(dev);
188231fb632bSRamuthevar Vadivel Murugan return ret;
188331fb632bSRamuthevar Vadivel Murugan }
188431fb632bSRamuthevar Vadivel Murugan
cqspi_remove(struct platform_device * pdev)18856fe41879SUwe Kleine-König static void cqspi_remove(struct platform_device *pdev)
188631fb632bSRamuthevar Vadivel Murugan {
188731fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = platform_get_drvdata(pdev);
188831fb632bSRamuthevar Vadivel Murugan
18891c75d749SYang Yingliang spi_unregister_controller(cqspi->host);
189031fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0);
189131fb632bSRamuthevar Vadivel Murugan
189231fb632bSRamuthevar Vadivel Murugan if (cqspi->rx_chan)
189331fb632bSRamuthevar Vadivel Murugan dma_release_channel(cqspi->rx_chan);
189431fb632bSRamuthevar Vadivel Murugan
189531fb632bSRamuthevar Vadivel Murugan clk_disable_unprepare(cqspi->clk);
189631fb632bSRamuthevar Vadivel Murugan
189733f1ef6dSWilliam Qiu if (cqspi->is_jh7110)
189833f1ef6dSWilliam Qiu cqspi_jh7110_disable_clk(pdev, cqspi);
189933f1ef6dSWilliam Qiu
190031fb632bSRamuthevar Vadivel Murugan pm_runtime_put_sync(&pdev->dev);
190131fb632bSRamuthevar Vadivel Murugan pm_runtime_disable(&pdev->dev);
190231fb632bSRamuthevar Vadivel Murugan }
190331fb632bSRamuthevar Vadivel Murugan
cqspi_suspend(struct device * dev)190431fb632bSRamuthevar Vadivel Murugan static int cqspi_suspend(struct device *dev)
190531fb632bSRamuthevar Vadivel Murugan {
190631fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev_get_drvdata(dev);
19072087e85bSDhruva Gole int ret;
190831fb632bSRamuthevar Vadivel Murugan
1909*03f1573cSThéo Lebrun ret = spi_controller_suspend(cqspi->host);
191031fb632bSRamuthevar Vadivel Murugan cqspi_controller_enable(cqspi, 0);
19112087e85bSDhruva Gole
19122087e85bSDhruva Gole clk_disable_unprepare(cqspi->clk);
19132087e85bSDhruva Gole
19142087e85bSDhruva Gole return ret;
191531fb632bSRamuthevar Vadivel Murugan }
191631fb632bSRamuthevar Vadivel Murugan
cqspi_resume(struct device * dev)191731fb632bSRamuthevar Vadivel Murugan static int cqspi_resume(struct device *dev)
191831fb632bSRamuthevar Vadivel Murugan {
191931fb632bSRamuthevar Vadivel Murugan struct cqspi_st *cqspi = dev_get_drvdata(dev);
192031fb632bSRamuthevar Vadivel Murugan
19212087e85bSDhruva Gole clk_prepare_enable(cqspi->clk);
19222087e85bSDhruva Gole cqspi_wait_idle(cqspi);
19232087e85bSDhruva Gole cqspi_controller_init(cqspi);
19242087e85bSDhruva Gole
19252087e85bSDhruva Gole cqspi->current_cs = -1;
19262087e85bSDhruva Gole cqspi->sclk = 0;
19272087e85bSDhruva Gole
1928*03f1573cSThéo Lebrun return spi_controller_resume(cqspi->host);
192931fb632bSRamuthevar Vadivel Murugan }
193031fb632bSRamuthevar Vadivel Murugan
1931be3206e8SDhruva Gole static DEFINE_SIMPLE_DEV_PM_OPS(cqspi_dev_pm_ops, cqspi_suspend, cqspi_resume);
193231fb632bSRamuthevar Vadivel Murugan
193331fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata cdns_qspi = {
193431fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_DISABLE_DAC_MODE,
193531fb632bSRamuthevar Vadivel Murugan };
193631fb632bSRamuthevar Vadivel Murugan
193731fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata k2g_qspi = {
193831fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_NEEDS_WR_DELAY,
193931fb632bSRamuthevar Vadivel Murugan };
194031fb632bSRamuthevar Vadivel Murugan
194131fb632bSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata am654_ospi = {
194231fb632bSRamuthevar Vadivel Murugan .hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
194331fb632bSRamuthevar Vadivel Murugan .quirks = CQSPI_NEEDS_WR_DELAY,
194431fb632bSRamuthevar Vadivel Murugan };
194531fb632bSRamuthevar Vadivel Murugan
1946ad2775dcSRamuthevar Vadivel Murugan static const struct cqspi_driver_platdata intel_lgm_qspi = {
1947ad2775dcSRamuthevar Vadivel Murugan .quirks = CQSPI_DISABLE_DAC_MODE,
1948ad2775dcSRamuthevar Vadivel Murugan };
1949ad2775dcSRamuthevar Vadivel Murugan
195098d948ebSDinh Nguyen static const struct cqspi_driver_platdata socfpga_qspi = {
19519ee5b6d5SNiravkumar L Rabara .quirks = CQSPI_DISABLE_DAC_MODE
19529ee5b6d5SNiravkumar L Rabara | CQSPI_NO_SUPPORT_WR_COMPLETION
19539ee5b6d5SNiravkumar L Rabara | CQSPI_SLOW_SRAM,
195498d948ebSDinh Nguyen };
195598d948ebSDinh Nguyen
195609e393e3SSai Krishna Potthuri static const struct cqspi_driver_platdata versal_ospi = {
195709e393e3SSai Krishna Potthuri .hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
19581a6f854fSSai Krishna Potthuri .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA,
19591a6f854fSSai Krishna Potthuri .indirect_read_dma = cqspi_versal_indirect_read_dma,
19601a6f854fSSai Krishna Potthuri .get_dma_status = cqspi_get_versal_dma_status,
196109e393e3SSai Krishna Potthuri };
196209e393e3SSai Krishna Potthuri
196347fef94aSWilliam Qiu static const struct cqspi_driver_platdata jh7110_qspi = {
196447fef94aSWilliam Qiu .quirks = CQSPI_DISABLE_DAC_MODE,
196533f1ef6dSWilliam Qiu .jh7110_clk_init = cqspi_jh7110_clk_init,
196647fef94aSWilliam Qiu };
196747fef94aSWilliam Qiu
1968f5c2f9f9SBrad Larson static const struct cqspi_driver_platdata pensando_cdns_qspi = {
1969f5c2f9f9SBrad Larson .quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE,
1970f5c2f9f9SBrad Larson };
1971f5c2f9f9SBrad Larson
197231fb632bSRamuthevar Vadivel Murugan static const struct of_device_id cqspi_dt_ids[] = {
197331fb632bSRamuthevar Vadivel Murugan {
197431fb632bSRamuthevar Vadivel Murugan .compatible = "cdns,qspi-nor",
197531fb632bSRamuthevar Vadivel Murugan .data = &cdns_qspi,
197631fb632bSRamuthevar Vadivel Murugan },
197731fb632bSRamuthevar Vadivel Murugan {
197831fb632bSRamuthevar Vadivel Murugan .compatible = "ti,k2g-qspi",
197931fb632bSRamuthevar Vadivel Murugan .data = &k2g_qspi,
198031fb632bSRamuthevar Vadivel Murugan },
198131fb632bSRamuthevar Vadivel Murugan {
198231fb632bSRamuthevar Vadivel Murugan .compatible = "ti,am654-ospi",
198331fb632bSRamuthevar Vadivel Murugan .data = &am654_ospi,
198431fb632bSRamuthevar Vadivel Murugan },
1985ab2d2875SRamuthevar Vadivel Murugan {
1986ab2d2875SRamuthevar Vadivel Murugan .compatible = "intel,lgm-qspi",
1987ad2775dcSRamuthevar Vadivel Murugan .data = &intel_lgm_qspi,
1988ab2d2875SRamuthevar Vadivel Murugan },
198909e393e3SSai Krishna Potthuri {
199009e393e3SSai Krishna Potthuri .compatible = "xlnx,versal-ospi-1.0",
19910d868829SIan Abbott .data = &versal_ospi,
199209e393e3SSai Krishna Potthuri },
199398d948ebSDinh Nguyen {
199498d948ebSDinh Nguyen .compatible = "intel,socfpga-qspi",
19950d868829SIan Abbott .data = &socfpga_qspi,
199698d948ebSDinh Nguyen },
199747fef94aSWilliam Qiu {
199847fef94aSWilliam Qiu .compatible = "starfive,jh7110-qspi",
199947fef94aSWilliam Qiu .data = &jh7110_qspi,
200047fef94aSWilliam Qiu },
2001f5c2f9f9SBrad Larson {
2002f5c2f9f9SBrad Larson .compatible = "amd,pensando-elba-qspi",
2003f5c2f9f9SBrad Larson .data = &pensando_cdns_qspi,
2004f5c2f9f9SBrad Larson },
200531fb632bSRamuthevar Vadivel Murugan { /* end of table */ }
200631fb632bSRamuthevar Vadivel Murugan };
200731fb632bSRamuthevar Vadivel Murugan
200831fb632bSRamuthevar Vadivel Murugan MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
200931fb632bSRamuthevar Vadivel Murugan
201031fb632bSRamuthevar Vadivel Murugan static struct platform_driver cqspi_platform_driver = {
201131fb632bSRamuthevar Vadivel Murugan .probe = cqspi_probe,
20126fe41879SUwe Kleine-König .remove_new = cqspi_remove,
201331fb632bSRamuthevar Vadivel Murugan .driver = {
201431fb632bSRamuthevar Vadivel Murugan .name = CQSPI_NAME,
2015be3206e8SDhruva Gole .pm = &cqspi_dev_pm_ops,
201631fb632bSRamuthevar Vadivel Murugan .of_match_table = cqspi_dt_ids,
201731fb632bSRamuthevar Vadivel Murugan },
201831fb632bSRamuthevar Vadivel Murugan };
201931fb632bSRamuthevar Vadivel Murugan
202031fb632bSRamuthevar Vadivel Murugan module_platform_driver(cqspi_platform_driver);
202131fb632bSRamuthevar Vadivel Murugan
202231fb632bSRamuthevar Vadivel Murugan MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
202331fb632bSRamuthevar Vadivel Murugan MODULE_LICENSE("GPL v2");
202431fb632bSRamuthevar Vadivel Murugan MODULE_ALIAS("platform:" CQSPI_NAME);
202531fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
202631fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");
202731fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>");
202831fb632bSRamuthevar Vadivel Murugan MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>");
2029f453f293SPratyush Yadav MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>");
2030