/openbmc/linux/Documentation/arch/x86/ |
H A D | topology.rst | 24 threads, cores, packages, etc. 36 - cores 41 Packages contain a number of cores plus shared resources, e.g. DRAM 52 The number of cores in a package. This information is retrieved via CPUID. 65 and deduced from the APIC IDs of the cores in the package.
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/openbmc/linux/arch/arm/boot/dts/arm/ |
H A D | vexpress-v2p-ca15_a7.dts | 360 /* Total current for the two A15 cores */ 367 /* Total current for the three A7 cores */ 381 /* Total power for the two A15 cores */ 388 /* Total power for the three A7 cores */ 395 /* Total energy for the two A15 cores */ 402 /* Total energy for the three A7 cores */
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/openbmc/linux/Documentation/devicetree/bindings/arc/ |
H A D | axs103.txt | 5 HS38x cores.
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/openbmc/linux/Documentation/devicetree/bindings/remoteproc/ |
H A D | ti,pru-rproc.yaml | 7 title: TI Programmable Realtime Unit (PRU) cores 14 (PRU-ICSS or PRUSS) has two 32-bit load/store RISC CPU cores called 20 PRU cores called RTUs with slightly different IP integration. The K3 SoCs 22 auxiliary Transmit PRU cores called Tx_PRUs that augment the PRUs. Each RTU
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/openbmc/linux/Documentation/devicetree/bindings/soc/ti/ |
H A D | ti,pruss.yaml | 18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and 38 by both the PRU cores. The Interrupt Controller (INTC) and a CFG module are 39 common to both the PRU cores. Each PRU core also has a private instruction 51 processor cores, the memories node, an INTC node and an MDIO node represented 284 that is common to all the PRU cores. This should be represented as an 299 PRU Node. Each PRUSS has dual PRU cores, each represented as a RemoteProc 302 present on K3 SoCs have additional auxiliary PRU cores with slightly
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/openbmc/u-boot/arch/arm/cpu/armv7/ls102xa/ |
H A D | Kconfig | 50 cores, count the reserved ports. This will allocate enough memory 51 in spin table to properly handle all cores.
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/openbmc/linux/Documentation/devicetree/bindings/bus/ |
H A D | baikal,bt1-axi.yaml | 15 high-speed peripheral IP-cores with RAM controller and with MIPS P5600 16 cores. Traffic arbitration is done by means of DW AXI Interconnect (so
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/openbmc/linux/Documentation/devicetree/bindings/clock/ |
H A D | baikal,bt1-ccu-pll.yaml | 30 | +----+------|- MIPS P5600 cores 48 to create a clock for the MIPS P5600 cores, the embedded DDR controller, 78 clocks consumer (like P5600 cores or DDR controller) or passed over a CCU
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/openbmc/linux/drivers/cpuidle/ |
H A D | Kconfig.arm | 56 define different C-states for little and big cores through the 131 CPU and L2 cores. It interface with various system drivers to put 132 the cores in low power modes.
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/openbmc/u-boot/arch/arm/dts/ |
H A D | socfpga_cyclone5.dtsi | 7 /* First 4KB has trampoline code for secondary cores. */
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H A D | socfpga_arria5.dtsi | 7 /* First 4KB has trampoline code for secondary cores. */
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/openbmc/qemu/target/xtensa/ |
H A D | meson.build | 3 xtensa_cores = fs.read('cores.list')
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/openbmc/u-boot/doc/ |
H A D | README.b4860qds | 8 StarCore and Power Architecture® cores. It targets the broadband wireless 28 e6500 cores, SC3900 FVP cores, memories and external interfaces. 37 management, and allocation tasks from the cores 108 1. Less e6500 cores: 1 cluster with 2 e6500 cores 109 2. Less SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster.
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/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/ |
H A D | trusted-firmware-a-fvp-base.inc | 19 # Our fvp-base machine explicitly has v8.4 cores
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/openbmc/linux/arch/arm/boot/dts/intel/socfpga/ |
H A D | socfpga_arria5.dtsi | 7 /* First 4KB has trampoline code for secondary cores. */
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H A D | socfpga_cyclone5.dtsi | 7 /* First 4KB has trampoline code for secondary cores. */
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/openbmc/u-boot/arch/arm/cpu/armv8/ |
H A D | Kconfig | 18 bool "Enable data coherency with other cores in cluster" 23 For A53, it enables data coherency with other cores in the 26 Cortex A53/57/72 cores require CPUECTLR_EL1.SMPEN set even 145 of CPU cores, platforms with asymmetric clusters don't apply here.
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/openbmc/openbmc-test-automation/redfish/systems/ |
H A D | test_systems_inventory.robot | 27 [Documentation] Get the total number of CPUs and cores in the system. 40 # Get the number of cores. 43 ${cores}= Get CPU TotalCores ${cpu} 44 ${total_num_cores}= Evaluate $total_num_cores + ${cores}
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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
H A D | snps,archs-intc.txt | 1 * ARC-HS incore Interrupt Controller (Provided by cores implementing ARCv2 ISA)
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/openbmc/openbmc/meta-ibm/recipes-phosphor/dbus/thermal-policy/ibm-ac-server/ |
H A D | thermal-policy.yaml | 3 # Shut down the system if more than three cores 9 'The machine has two processor chips with 24 cores each.' 132 'If this condition passes at least three cores are running
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/openbmc/linux/Documentation/devicetree/bindings/arm/amlogic/ |
H A D | pmu.txt | 5 This includes the power to the CPU cores.
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/openbmc/u-boot/Documentation/devicetree/bindings/axi/ |
H A D | gdsys,ihs_axi.txt | 4 the connected devices (usually IP cores) can be controlled via software.
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/openbmc/linux/arch/arm/mach-mstar/ |
H A D | Kconfig | 12 based on Armv7 cores like the Cortex A7 and share the same
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/openbmc/linux/arch/arc/ |
H A D | Kconfig | 102 The original ARC ISA of ARC600/700 cores 108 ISA for the Next Generation ARC-HS cores 137 - SMP configurations of up to 4 cores with coherency 182 In SMP configuration cores can be configured as Halt-on-reset 195 This IP block enables SMP in ARC-HS38 cores. 430 On HS cores, taken interrupt auto saves the regfile on stack. 437 On HS cores, loop buffer (LPB) is programmable in runtime and can 482 ARC cores with 40 bit Physical Addressing support
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/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
H A D | README.soc | 15 processor cores with datapath acceleration optimized for L2/3 packet 53 architecture combining eight ARM A53 processor cores 63 - Cores are in 2 cluster of 4-cores each 85 processor cores with high-performance data path acceleration logic and network 171 processor cores with datapath acceleration optimized for L2/3 packet 212 processor cores with high-performance data path acceleration logic and network 280 cores with advanced, high-performance datapath acceleration and
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