/openbmc/u-boot/doc/ |
H A D | README.ARC | 5 More information on ARC cores avaialble here:
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H A D | README.NDS32 | 36 Andes Technology has 4 families of CPU cores: N12, N10, N9, N8.
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H A D | README.xtensa | 9 SoC cores in the same manner as ARM, MIPS, etc. 11 Xtensa licensees create their own Xtensa cores with selected features
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/openbmc/qemu/hw/ppc/ |
H A D | pnv.c | 313 PnvCore *pnv_core = chip->cores[i]; in pnv_chip_power8_dt_populate() 337 PnvCore *pnv_core = chip->cores[i]; in pnv_chip_power9_dt_populate() 360 PnvCore *pnv_core = chip->cores[i]; in pnv_chip_power10_dt_populate() 889 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); in pnv_init() 931 object_property_set_int(chip, "nr-cores", machine->smp.cores, in pnv_init() 1226 PnvCore *pnv_core = chip->cores[i]; in pnv_chip_icp_realize() 1468 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], in pnv_chip_quad_realize() 1707 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], in pnv_chip_power10_quad_realize() 1967 chip->cores = g_new0(PnvCore *, chip->nr_cores); in pnv_chip_core_realize() 1983 chip->cores[i] = pnv_core; in pnv_chip_core_realize() [all …]
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/openbmc/linux/tools/power/x86/turbostat/ |
H A D | turbostat.c | 548 struct core_data cores; member 1757 average.cores.c3 += c->c3; in sum_counters() 1758 average.cores.c6 += c->c6; in sum_counters() 1759 average.cores.c7 += c->c7; in sum_counters() 1760 average.cores.mc6_us += c->mc6_us; in sum_counters() 1762 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c); in sum_counters() 1763 average.cores.core_throt_cnt = MAX(average.cores.core_throt_cnt, c->core_throt_cnt); in sum_counters() 1849 average.cores.c3 /= topo.num_cores; in compute_average() 2613 unsigned int cores[buckets_no]; in dump_knl_turbo_ratio_limits() local 2644 cores[b_nr] = (msr & 0xFF) >> 1; in dump_knl_turbo_ratio_limits() [all …]
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/openbmc/linux/Documentation/admin-guide/perf/ |
H A D | qcom_l3_pmu.rst | 7 by all cores within a socket. Each slice is exposed as a separate uncore perf
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/openbmc/qemu/docs/system/ |
H A D | target-avr.rst | 7 These can have one of the following cores: avr1, avr2, avr25, avr3, avr31,
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/openbmc/openbmc/poky/meta/recipes-extended/pigz/ |
H A D | pigz_2.8.bb | 4 multiple cores to the hilt when compressing data. pigz was written by Mark \
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/openbmc/qemu/include/hw/ppc/ |
H A D | pnv_chip.h | 30 PnvCore **cores; member
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/openbmc/u-boot/board/freescale/ls1021aqds/ |
H A D | README | 14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores 29 - Dual high-preformance ARM Cortex-A7 cores, each core includes:
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/openbmc/u-boot/board/freescale/ls1021atwr/ |
H A D | README | 14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores 29 - Dual high-preformance ARM Cortex-A7 cores, each core includes:
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/openbmc/linux/drivers/mailbox/ |
H A D | Kconfig | 60 send short messages between Highbank's A9 cores and the EnergyCore 97 between CPU cores and MCU processor on Some Rockchip SOCs. 210 Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller. 211 It is used to send short messages between ARM64-bit cores and
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/openbmc/u-boot/arch/arm/mach-rockchip/rk3368/ |
H A D | Kconfig | 14 - 8x Cortex-A53 (in 2 clusters of 4 cores each)
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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
H A D | mediatek,mtk-cirq.yaml | 14 work outside of MCUSYS which comprises with Cortex-Ax cores, CCI and GIC.
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H A D | ti,pruss-intc.yaml | 14 to all the PRU cores. Most interrupt controllers can route 64 input events 18 interrupts (0, 1) are fed exclusively to the internal PRU cores, with the
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/openbmc/linux/Documentation/devicetree/bindings/remoteproc/ |
H A D | qcom,sc8180x-pas.yaml | 14 firmware on the Qualcomm DSP Hexagon cores.
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H A D | qcom,qcs404-pas.yaml | 14 firmware on the Qualcomm DSP Hexagon cores.
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/openbmc/linux/Documentation/arch/arm/keystone/ |
H A D | overview.rst | 8 and c66x DSP cores. This document describes essential information required
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/openbmc/linux/Documentation/admin-guide/pm/ |
H A D | intel_epb.rst | 40 example, SMT siblings or cores in one package). For this reason, updating the
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/openbmc/linux/arch/arm/boot/dts/calxeda/ |
H A D | highbank.dts | 8 /* First 4KB has pen for secondary cores. */
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/openbmc/qemu/docs/system/riscv/ |
H A D | sifive_u.rst | 13 * Up to 4 U54 / U34 cores 31 With QEMU, one can create a machine with 1 E51 core and up to 4 U54 cores. It 33 that the RISC-V cores are replaced by the 32-bit ones (E31 and U34), to help 309 U-Boot proper. Hence the number of cores and size of memory have to match 310 the real hardware, ie: 5 cores (-smp 5) and 8 GiB memory (-m 8G).
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/openbmc/linux/drivers/media/platform/amphion/ |
H A D | vpu_core.c | 205 list_for_each_entry(c, &vpu->cores, list) { in vpu_core_find_proper_by_type() 233 list_for_each_entry(c, &vpu->cores, list) { in vpu_core_is_exist() 279 list_add_tail(&core->list, &vpu->cores); in vpu_core_register() 531 list_for_each_entry(core, &vpu->cores, list) { in vpu_get_resource()
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/openbmc/u-boot/arch/arm/dts/ |
H A D | fsl-imx8-ca53.dtsi | 43 /* We have 1 clusters having 4 Cortex-A53 cores */
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/openbmc/linux/Documentation/devicetree/bindings/regulator/ |
H A D | richtek,rtq2134-regulator.yaml | 14 integrates with four high efficient, synchronous step-down converter cores.
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/openbmc/linux/sound/soc/intel/skylake/ |
H A D | skl.h | 120 struct skl_dsp_cores cores; member
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