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/openbmc/u-boot/doc/
H A DREADME.ARC5 More information on ARC cores avaialble here:
H A DREADME.NDS3236 Andes Technology has 4 families of CPU cores: N12, N10, N9, N8.
H A DREADME.xtensa9 SoC cores in the same manner as ARM, MIPS, etc.
11 Xtensa licensees create their own Xtensa cores with selected features
/openbmc/qemu/hw/ppc/
H A Dpnv.c313 PnvCore *pnv_core = chip->cores[i]; in pnv_chip_power8_dt_populate()
337 PnvCore *pnv_core = chip->cores[i]; in pnv_chip_power9_dt_populate()
360 PnvCore *pnv_core = chip->cores[i]; in pnv_chip_power10_dt_populate()
889 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); in pnv_init()
931 object_property_set_int(chip, "nr-cores", machine->smp.cores, in pnv_init()
1226 PnvCore *pnv_core = chip->cores[i]; in pnv_chip_icp_realize()
1468 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], in pnv_chip_quad_realize()
1707 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], in pnv_chip_power10_quad_realize()
1967 chip->cores = g_new0(PnvCore *, chip->nr_cores); in pnv_chip_core_realize()
1983 chip->cores[i] = pnv_core; in pnv_chip_core_realize()
[all …]
/openbmc/linux/tools/power/x86/turbostat/
H A Dturbostat.c548 struct core_data cores; member
1757 average.cores.c3 += c->c3; in sum_counters()
1758 average.cores.c6 += c->c6; in sum_counters()
1759 average.cores.c7 += c->c7; in sum_counters()
1760 average.cores.mc6_us += c->mc6_us; in sum_counters()
1762 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c); in sum_counters()
1763 average.cores.core_throt_cnt = MAX(average.cores.core_throt_cnt, c->core_throt_cnt); in sum_counters()
1849 average.cores.c3 /= topo.num_cores; in compute_average()
2613 unsigned int cores[buckets_no]; in dump_knl_turbo_ratio_limits() local
2644 cores[b_nr] = (msr & 0xFF) >> 1; in dump_knl_turbo_ratio_limits()
[all …]
/openbmc/linux/Documentation/admin-guide/perf/
H A Dqcom_l3_pmu.rst7 by all cores within a socket. Each slice is exposed as a separate uncore perf
/openbmc/qemu/docs/system/
H A Dtarget-avr.rst7 These can have one of the following cores: avr1, avr2, avr25, avr3, avr31,
/openbmc/openbmc/poky/meta/recipes-extended/pigz/
H A Dpigz_2.8.bb4 multiple cores to the hilt when compressing data. pigz was written by Mark \
/openbmc/qemu/include/hw/ppc/
H A Dpnv_chip.h30 PnvCore **cores; member
/openbmc/u-boot/board/freescale/ls1021aqds/
H A DREADME14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
29 - Dual high-preformance ARM Cortex-A7 cores, each core includes:
/openbmc/u-boot/board/freescale/ls1021atwr/
H A DREADME14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
29 - Dual high-preformance ARM Cortex-A7 cores, each core includes:
/openbmc/linux/drivers/mailbox/
H A DKconfig60 send short messages between Highbank's A9 cores and the EnergyCore
97 between CPU cores and MCU processor on Some Rockchip SOCs.
210 Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.
211 It is used to send short messages between ARM64-bit cores and
/openbmc/u-boot/arch/arm/mach-rockchip/rk3368/
H A DKconfig14 - 8x Cortex-A53 (in 2 clusters of 4 cores each)
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dmediatek,mtk-cirq.yaml14 work outside of MCUSYS which comprises with Cortex-Ax cores, CCI and GIC.
H A Dti,pruss-intc.yaml14 to all the PRU cores. Most interrupt controllers can route 64 input events
18 interrupts (0, 1) are fed exclusively to the internal PRU cores, with the
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,sc8180x-pas.yaml14 firmware on the Qualcomm DSP Hexagon cores.
H A Dqcom,qcs404-pas.yaml14 firmware on the Qualcomm DSP Hexagon cores.
/openbmc/linux/Documentation/arch/arm/keystone/
H A Doverview.rst8 and c66x DSP cores. This document describes essential information required
/openbmc/linux/Documentation/admin-guide/pm/
H A Dintel_epb.rst40 example, SMT siblings or cores in one package). For this reason, updating the
/openbmc/linux/arch/arm/boot/dts/calxeda/
H A Dhighbank.dts8 /* First 4KB has pen for secondary cores. */
/openbmc/qemu/docs/system/riscv/
H A Dsifive_u.rst13 * Up to 4 U54 / U34 cores
31 With QEMU, one can create a machine with 1 E51 core and up to 4 U54 cores. It
33 that the RISC-V cores are replaced by the 32-bit ones (E31 and U34), to help
309 U-Boot proper. Hence the number of cores and size of memory have to match
310 the real hardware, ie: 5 cores (-smp 5) and 8 GiB memory (-m 8G).
/openbmc/linux/drivers/media/platform/amphion/
H A Dvpu_core.c205 list_for_each_entry(c, &vpu->cores, list) { in vpu_core_find_proper_by_type()
233 list_for_each_entry(c, &vpu->cores, list) { in vpu_core_is_exist()
279 list_add_tail(&core->list, &vpu->cores); in vpu_core_register()
531 list_for_each_entry(core, &vpu->cores, list) { in vpu_get_resource()
/openbmc/u-boot/arch/arm/dts/
H A Dfsl-imx8-ca53.dtsi43 /* We have 1 clusters having 4 Cortex-A53 cores */
/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Drichtek,rtq2134-regulator.yaml14 integrates with four high efficient, synchronous step-down converter cores.
/openbmc/linux/sound/soc/intel/skylake/
H A Dskl.h120 struct skl_dsp_cores cores; member

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