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/openbmc/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-v3s.dtsi65 <&ccu CLK_TCON0>;
78 clocks = <&ccu CLK_CPU>;
128 <&ccu CLK_DE>;
191 <&ccu CLK_TCON0>;
225 <&ccu CLK_MMC0>,
246 <&ccu CLK_MMC1>,
267 <&ccu CLK_MMC2>,
287 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
322 ccu: clock@1c20000 { label
460 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
[all …]
H A Dsun8i-a23-a33.dtsi65 clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
66 <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
67 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
169 clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
189 <&ccu 13>;
223 <&ccu CLK_MMC0>,
324 clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>;
606 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
630 clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
654 clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
[all …]
H A Dsun8i-h3.dtsi78 clocks = <&ccu CLK_CPUX>;
191 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
192 <&ccu CLK_DRAM_VE>;
203 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
225 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
236 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
277 &ccu {
292 <&ccu CLK_MMC0>,
293 <&ccu CLK_MMC0_OUTPUT>,
304 <&ccu CLK_MMC1>,
[all …]
H A Dsun8i-a33.dtsi209 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
210 <&ccu CLK_DRAM_VE>;
221 clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
232 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
245 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
262 <&ccu CLK_DSI_SCLK>;
283 <&ccu CLK_DSI_DPHY>;
370 clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
371 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
374 resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
[all …]
H A Dsun9i-a80.dtsi227 <&ccu CLK_PLL_AUDIO>;
465 clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
584 clocks = <&ccu CLK_DE>,
585 <&ccu CLK_SDRAM>,
586 <&ccu CLK_BUS_DE>;
879 clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>;
882 <&ccu RST_BUS_EDP>,
883 <&ccu RST_BUS_LVDS>;
912 clocks = <&ccu CLK_BUS_LCD1>, <&ccu CLK_LCD1>;
914 resets = <&ccu RST_BUS_LCD1>, <&ccu RST_BUS_EDP>;
[all …]
H A Dsun5i-a10s.dtsi63 clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_HDMI>,
64 <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DRAM_DE_BE>,
65 <&ccu CLK_DE_BE>, <&ccu CLK_HDMI>;
80 clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>,
81 <&ccu CLK_PLL_VIDEO0_2X>,
82 <&ccu CLK_PLL_VIDEO1_2X>;
111 clocks = <&ccu CLK_HOSC>;
118 &ccu {
119 compatible = "allwinner,sun5i-a10s-ccu";
/openbmc/u-boot/arch/arm/dts/
H A Dsun8i-a83t.dtsi425 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
428 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
458 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
611 clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>;
773 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
788 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
801 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
816 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
932 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
964 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
[all …]
H A Dsun8i-a23-a33.dtsi64 clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
65 <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
66 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
140 <&ccu CLK_MMC0>,
159 <&ccu CLK_MMC1>,
178 <&ccu CLK_MMC2>,
197 clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
227 <&ccu CLK_USB_PHY1>;
253 clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>;
260 ccu: clock@1c20000 { label
[all …]
H A Dsun8i-v3s.dtsi61 clocks = <&ccu CLK_CPU>;
103 <&ccu CLK_MMC0>,
104 <&ccu CLK_MMC0_OUTPUT>,
105 <&ccu CLK_MMC0_SAMPLE>;
122 <&ccu CLK_MMC1>,
123 <&ccu CLK_MMC1_OUTPUT>,
124 <&ccu CLK_MMC1_SAMPLE>;
141 <&ccu CLK_MMC2>,
142 <&ccu CLK_MMC2_OUTPUT>,
143 <&ccu CLK_MMC2_SAMPLE>;
[all …]
H A Dsun50i-h6.dtsi95 ccu: clock@3001000 { label
156 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
158 resets = <&ccu RST_BUS_MMC0>;
170 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
172 resets = <&ccu RST_BUS_MMC1>;
184 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
186 resets = <&ccu RST_BUS_MMC2>;
200 clocks = <&ccu CLK_BUS_UART0>;
201 resets = <&ccu RST_BUS_UART0>;
211 clocks = <&ccu CLK_BUS_UART1>;
[all …]
H A Dsun8i-h3.dtsi162 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
172 &ccu {
183 <&ccu CLK_MMC0>,
184 <&ccu CLK_MMC0_OUTPUT>,
185 <&ccu CLK_MMC0_SAMPLE>;
195 <&ccu CLK_MMC1>,
196 <&ccu CLK_MMC1_OUTPUT>,
197 <&ccu CLK_MMC1_SAMPLE>;
207 <&ccu CLK_MMC2>,
208 <&ccu CLK_MMC2_OUTPUT>,
[all …]
H A Dsun8i-a33.dtsi212 <&ccu CLK_LCD_CH0>;
252 clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
263 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
276 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
293 <&ccu CLK_DSI_SCLK>;
331 clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
359 clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
360 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
363 resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
400 clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
[all …]
H A Dsun5i-a10s.dtsi67 clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_HDMI>,
68 <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DRAM_DE_BE>,
69 <&ccu CLK_DE_BE>, <&ccu CLK_HDMI>;
84 clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>,
85 <&ccu CLK_PLL_VIDEO0_2X>,
86 <&ccu CLK_PLL_VIDEO1_2X>;
117 clocks = <&ccu CLK_HOSC>;
124 &ccu {
125 compatible = "allwinner,sun5i-a10s-ccu";
H A Dsun9i-a80.dtsi191 <&ccu CLK_PLL_PERIPH0>,
192 <&ccu CLK_PLL_AUDIO>;
408 <&ccu CLK_MMC0_OUTPUT>,
521 clocks = <&ccu CLK_DE>,
522 <&ccu CLK_SDRAM>,
523 <&ccu CLK_BUS_DE>;
846 clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>;
848 resets = <&ccu RST_BUS_LCD0>, <&ccu RST_BUS_EDP>;
879 clocks = <&ccu CLK_BUS_LCD1>, <&ccu CLK_LCD1>;
881 resets = <&ccu RST_BUS_LCD1>, <&ccu RST_BUS_EDP>;
[all …]
/openbmc/linux/drivers/clk/bcm/
H A Dclk-kona-setup.c85 range = bcm_clk->ccu->range; in peri_clk_data_offsets_valid()
749 if (!ccu->base) in kona_ccu_teardown()
753 ccu_clks_teardown(ccu); in kona_ccu_teardown()
754 of_node_put(ccu->node); in kona_ccu_teardown()
755 ccu->node = NULL; in kona_ccu_teardown()
756 iounmap(ccu->base); in kona_ccu_teardown()
757 ccu->base = NULL; in kona_ccu_teardown()
822 ccu->base = ioremap(res.start, ccu->range); in kona_dt_ccu_setup()
823 if (!ccu->base) { in kona_dt_ccu_setup()
836 if (!ccu->kona_clks[i].ccu) in kona_dt_ccu_setup()
[all …]
/openbmc/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-a100.dtsi95 ccu: clock@3001000 { label
108 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
110 resets = <&ccu RST_BUS_DMA>;
222 clocks = <&ccu CLK_BUS_I2C0>;
223 resets = <&ccu RST_BUS_I2C0>;
237 clocks = <&ccu CLK_BUS_I2C1>;
238 resets = <&ccu RST_BUS_I2C1>;
252 clocks = <&ccu CLK_BUS_I2C2>;
280 clocks = <&ccu CLK_BUS_THS>;
282 resets = <&ccu RST_BUS_THS>;
[all …]
/openbmc/linux/drivers/clk/baikal-t1/
H A DMakefile2 obj-$(CONFIG_CLK_BT1_CCU_PLL) += ccu-pll.o clk-ccu-pll.o
3 obj-$(CONFIG_CLK_BT1_CCU_DIV) += ccu-div.o clk-ccu-div.o
4 obj-$(CONFIG_CLK_BT1_CCU_RST) += ccu-rst.o
/openbmc/linux/Documentation/devicetree/bindings/display/
H A Dallwinner,sun8i-a83t-dw-hdmi.yaml153 * This comes from the clock/sun8i-a83t-ccu.h and
154 * reset/sun8i-a83t-ccu.h headers, but we can't include them since
168 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
169 <&ccu CLK_HDMI>;
171 resets = <&ccu RST_BUS_HDMI1>;
205 * This comes from the clock/sun50i-h6-ccu.h and
206 * reset/sun50i-h6-ccu.h headers, but we can't include them since
224 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
225 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
226 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
[all …]
H A Dallwinner,sun4i-a10-display-backend.yaml162 * This comes from the clock/sun4i-a10-ccu.h and
163 * reset/sun4i-a10-ccu.h headers, but we can't include them since
177 clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
178 <&ccu CLK_DRAM_DE_BE0>;
181 resets = <&ccu RST_DE_BE0>;
225 * This comes from the clock/sun8i-a23-a33-ccu.h and
226 * reset/sun8i-a23-a33-ccu.h headers, but we can't include them
243 clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
244 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
247 resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
H A Dallwinner,sun4i-a10-tcon.yaml384 resets = <&ccu RST_TCON0>;
386 clocks = <&ccu CLK_AHB_LCD0>,
387 <&ccu CLK_TCON0_CH0>,
457 resets = <&ccu RST_AHB1_LCD0>, <&ccu RST_AHB1_LVDS>;
460 <&ccu CLK_LCD0_CH0>,
461 <&ccu CLK_LCD0_CH1>,
462 <&ccu CLK_PLL_MIPI>;
531 clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>;
533 resets = <&ccu RST_BUS_LCD0>, <&ccu RST_BUS_EDP>, <&ccu RST_BUS_LVDS>;
581 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dallwinner,sun8i-a83t-usb-phy.yaml93 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
94 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
105 clocks = <&ccu CLK_USB_PHY0>,
106 <&ccu CLK_USB_PHY1>,
107 <&ccu CLK_USB_HSIC>,
108 <&ccu CLK_USB_HSIC_12M>;
113 resets = <&ccu RST_USB_PHY0>,
114 <&ccu RST_USB_PHY1>,
115 <&ccu RST_USB_HSIC>;
H A Dallwinner,sun8i-h3-usb-phy.yaml130 #include <dt-bindings/clock/sun8i-h3-ccu.h>
131 #include <dt-bindings/reset/sun8i-h3-ccu.h>
146 clocks = <&ccu CLK_USB_PHY0>,
147 <&ccu CLK_USB_PHY1>,
148 <&ccu CLK_USB_PHY2>,
149 <&ccu CLK_USB_PHY3>;
154 resets = <&ccu RST_USB_PHY0>,
155 <&ccu RST_USB_PHY1>,
156 <&ccu RST_USB_PHY2>,
157 <&ccu RST_USB_PHY3>;
H A Dallwinner,sun6i-a31-usb-phy.yaml91 #include <dt-bindings/clock/sun6i-a31-ccu.h>
92 #include <dt-bindings/reset/sun6i-a31-ccu.h>
103 clocks = <&ccu CLK_USB_PHY0>,
104 <&ccu CLK_USB_PHY1>,
105 <&ccu CLK_USB_PHY2>;
109 resets = <&ccu RST_USB_PHY0>,
110 <&ccu RST_USB_PHY1>,
111 <&ccu RST_USB_PHY2>;
H A Dallwinner,sun8i-r40-usb-phy.yaml93 #include <dt-bindings/clock/sun8i-r40-ccu.h>
94 #include <dt-bindings/reset/sun8i-r40-ccu.h>
107 clocks = <&ccu CLK_USB_PHY0>,
108 <&ccu CLK_USB_PHY1>,
109 <&ccu CLK_USB_PHY2>;
113 resets = <&ccu RST_USB_PHY0>,
114 <&ccu RST_USB_PHY1>,
115 <&ccu RST_USB_PHY2>;
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun9i-a80-de-clks.yaml54 #include <dt-bindings/clock/sun9i-a80-ccu.h>
55 #include <dt-bindings/reset/sun9i-a80-ccu.h>
60 clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>;
62 resets = <&ccu RST_BUS_DE>;

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