Lines Matching refs:ccu
46 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
47 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
65 <&ccu CLK_TCON0>;
78 clocks = <&ccu CLK_CPU>;
127 clocks = <&ccu CLK_BUS_DE>,
128 <&ccu CLK_DE>;
131 resets = <&ccu RST_BUS_DE>;
181 clocks = <&ccu CLK_BUS_DMA>;
182 resets = <&ccu RST_BUS_DMA>;
190 clocks = <&ccu CLK_BUS_TCON0>,
191 <&ccu CLK_TCON0>;
196 resets = <&ccu RST_BUS_TCON0>;
224 clocks = <&ccu CLK_BUS_MMC0>,
225 <&ccu CLK_MMC0>,
226 <&ccu CLK_MMC0_OUTPUT>,
227 <&ccu CLK_MMC0_SAMPLE>;
232 resets = <&ccu RST_BUS_MMC0>;
245 clocks = <&ccu CLK_BUS_MMC1>,
246 <&ccu CLK_MMC1>,
247 <&ccu CLK_MMC1_OUTPUT>,
248 <&ccu CLK_MMC1_SAMPLE>;
253 resets = <&ccu RST_BUS_MMC1>;
266 clocks = <&ccu CLK_BUS_MMC2>,
267 <&ccu CLK_MMC2>,
268 <&ccu CLK_MMC2_OUTPUT>,
269 <&ccu CLK_MMC2_SAMPLE>;
274 resets = <&ccu RST_BUS_MMC2>;
287 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
291 resets = <&ccu RST_BUS_CE>;
298 clocks = <&ccu CLK_BUS_OTG>;
299 resets = <&ccu RST_BUS_OTG>;
314 clocks = <&ccu CLK_USB_PHY0>;
316 resets = <&ccu RST_USB_PHY0>;
322 ccu: clock@1c20000 { label
323 compatible = "allwinner,sun8i-v3s-ccu";
346 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
460 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
462 resets = <&ccu RST_BUS_CODEC>;
480 clocks = <&ccu CLK_BUS_UART0>;
483 resets = <&ccu RST_BUS_UART0>;
493 clocks = <&ccu CLK_BUS_UART1>;
496 resets = <&ccu RST_BUS_UART1>;
506 clocks = <&ccu CLK_BUS_UART2>;
509 resets = <&ccu RST_BUS_UART2>;
519 clocks = <&ccu CLK_BUS_I2C0>;
520 resets = <&ccu RST_BUS_I2C0>;
532 clocks = <&ccu CLK_BUS_I2C1>;
533 resets = <&ccu RST_BUS_I2C1>;
545 resets = <&ccu RST_BUS_EMAC>;
547 clocks = <&ccu CLK_BUS_EMAC>;
575 clocks = <&ccu CLK_BUS_EPHY>;
576 resets = <&ccu RST_BUS_EPHY>;
586 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
592 resets = <&ccu RST_BUS_SPI0>;
613 clocks = <&ccu CLK_BUS_CSI>,
614 <&ccu CLK_CSI1_SCLK>,
615 <&ccu CLK_DRAM_CSI>;
617 resets = <&ccu RST_BUS_CSI>;