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Searched refs:RGMII (Results 101 – 125 of 176) sorted by relevance

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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dethernet-phy.yaml196 RGMII Receive PHY Clock Delay defined in pico seconds. This is used for
202 RGMII Transmit PHY Clock Delay defined in pico seconds. This is used for
H A Drockchip-dwmac.yaml77 For RGMII, it must be "input", means main clock(125MHz)
H A Dsnps,dwc-qos-ethernet.txt29 In some configurations (e.g. GMII/RGMII), this clock also drives the PHY TX
34 In some configurations (e.g. GMII/RGMII), this clock is derived from the
H A Dti,icssg-prueth.yaml107 to ICSSG control register for RGMII transmit delay
H A Dstm32-dwmac.yaml87 set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125.
H A Dti,cpsw-switch.yaml17 independent interface (RGMII), reduced media independent interface (RMII),
/openbmc/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxbb-nanopi-k2.dts247 "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk",
249 "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
H A Dmeson-gxm-nexbox-a1.dts164 /* External PHY is in RGMII */
H A Dmeson-gxm-rbox-pro.dts166 /* External PHY is in RGMII */
/openbmc/u-boot/doc/device-tree-bindings/net/
H A Dsnps,dwc-qos-ethernet.txt26 In some configurations (e.g. GMII/RGMII), this clock also drives the PHY TX
31 In some configurations (e.g. GMII/RGMII), this clock is derived from the
/openbmc/u-boot/board/freescale/mpc837xemds/
H A DREADME30 SW7[1-8]= 0110_1101 (TSEC1/2 interface setting - RGMII)
/openbmc/u-boot/doc/
H A DREADME.kwbimage76 # Configure RGMII-0 interface pad voltage to 1.8V
/openbmc/linux/Documentation/networking/dsa/
H A Dsja1105.rst358 RGMII fixed-link and internal delays
363 correct RGMII timing budget.
370 In RGMII the clock frequency changes with link speed (125 MHz at 1000 Mbps, 25
373 In the situation where the switch port is connected through an RGMII fixed-link
377 The take-away is that in RGMII mode, the switch's internal delays are only
/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage_256M8_1.cfg55 # bit 7: 0, RGMII-pads voltage = 3.3V
59 # bit 15: 0, MPP RGMII-pads voltage = 3.3V
H A Dkwbimage_128M16_1.cfg55 # bit 7: 0, RGMII-pads voltage = 3.3V
59 # bit 15: 0, MPP RGMII-pads voltage = 3.3V
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc36 - Up to 2 x RGMII supporting 1000Mbps
195 - Up to 2 x RGMII supporting 1000Mbps (MAC 3, 4)
299 Support for two RGMII parallel interfaces.
/openbmc/u-boot/board/freescale/ls1088a/
H A DREADME111 - 2 RGMII
/openbmc/u-boot/board/Seagate/nas220/
H A Dkwbimage.cfg23 # Configure RGMII-0 interface pad voltage to 1.8V
/openbmc/linux/arch/arm/boot/dts/nxp/ls/
H A Dls1021a-tsn.dts121 /* RGMII delays added via PCB traces */
/openbmc/u-boot/board/Marvell/dreamplug/
H A Dkwbimage.cfg19 # Configure RGMII-0/1 interface pad voltage to 1.8V
/openbmc/u-boot/board/Marvell/sheevaplug/
H A Dkwbimage.cfg18 # Configure RGMII-0 interface pad voltage to 1.8V
/openbmc/u-boot/board/Seagate/dockstar/
H A Dkwbimage.cfg21 # Configure RGMII-0 interface pad voltage to 1.8V
/openbmc/u-boot/board/Marvell/guruplug/
H A Dkwbimage.cfg18 # Configure RGMII-0/1 interface pad voltage to 1.8V
/openbmc/u-boot/board/Seagate/goflexhome/
H A Dkwbimage.cfg24 # Configure RGMII-0 interface pad voltage to 1.8V
/openbmc/u-boot/board/Synology/ds109/
H A Dkwbimage.cfg19 # Configure RGMII-0/1 interface pad voltage to 1.8V

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