/openbmc/linux/Documentation/devicetree/bindings/clock/ |
H A D | brcm,iproc-clocks.yaml | 16 LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL 59 description: The input parent clock phandle for the PLL / ASIU clock. For 103 The following table defines the set of PLL/clock index and ID for Cygnus. 155 The following table defines the set of PLL/clock for Hurricane 2: 174 The following table defines the set of PLL/clock index and ID for Northstar and 209 The following table defines the set of PLL/clock index and ID for Northstar 2. 267 The following table defines the set of PLL/clock index and ID for Stingray.
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H A D | qcom,hfpll.txt | 1 High-Frequency PLL (HFPLL) 36 Definition: Name of the PLL. Typically hfpllX where X is a CPU number
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H A D | altr_socfpga.txt | 9 "altr,socfpga-pll-clock" - for a PLL clock 11 PLL clock.
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H A D | samsung,exynos-audss-clock.yaml | 31 Fixed rate PLL reference clock, parent of mout_audss. "fin_pll" is 34 Input PLL to the AudioSS block, parent of mout_audss. "fout_epll" is
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H A D | qcom,lcc.yaml | 56 - description: PLL 4 Vote clock 90 - description: PLL 4 Vote clock
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H A D | cirrus,cs2000-cp.yaml | 52 This mode allows the PLL to maintain lock even when CLK_IN 59 digital PLL of the silicon.
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H A D | st,nomadik.txt | 23 PLL nodes: these nodes represent the two PLLs on the system, 27 Required properties for the two PLL nodes:
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H A D | renesas,5p35023.yaml | 15 express applications. The 5P35023 device is a three PLL 16 architecture design, and each PLL is individually programmable
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H A D | ti-keystone-pllctrl.txt | 5 the NETCP modules) requires a PLL Controller to manage the various clock
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H A D | allwinner,sun9i-a80-pll4-clk.yaml | 7 title: Allwinner A80 Peripheral PLL
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/openbmc/linux/drivers/clk/mediatek/ |
H A D | clk-mt8192-apmixedsys.c | 35 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ macro 67 PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 77 PLL(CLK_APMIXED_USBPLL, "usbpll", 0x03c4, 0x03cc, 0x00000000,
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/openbmc/linux/Documentation/devicetree/bindings/phy/ |
H A D | phy-rockchip-inno-hdmi.txt | 11 oscillator reference PLL clock input and "refpclk" for pclk- 12 based refeference PLL clock input.
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H A D | samsung,ufs-phy.yaml | 70 - description: PLL reference clock 86 - description: PLL reference clock
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H A D | phy-stm32-usbphyc.yaml | 14 PLL configuration. 17 |_ PLL 49 description: regulator providing 1V1 power supply to the PLL block 52 description: regulator providing 1V8 power supply to the PLL block
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/openbmc/linux/arch/arm/boot/dts/arm/ |
H A D | vexpress-v2p-ca15_a7.dts | 257 /* A15 PLL 0 reference clock */ 266 /* A15 PLL 1 reference clock */ 275 /* A7 PLL 0 reference clock */ 284 /* A7 PLL 1 reference clock */ 302 /* HDLCD PLL reference clock */ 320 /* SYS PLL reference clock */ 329 /* DDR2 PLL reference clock */
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/openbmc/linux/drivers/clk/meson/ |
H A D | Kconfig | 110 tristate "Amlogic A1 SoC PLL controller support" 116 Support for the PLL clock controller on Amlogic A113L based 117 device, A1 SoC Family. Say Y if you want A1 PLL clock controller
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/openbmc/linux/drivers/clk/rockchip/ |
H A D | clk-rk3188.c | 216 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), 218 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), 220 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8), 222 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12), 227 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), 229 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), 231 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8), 233 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
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/openbmc/linux/Documentation/devicetree/bindings/sound/ |
H A D | fsl,micfil.yaml | 45 - description: PLL clock source for 8kHz series 46 - description: PLL clock source for 11kHz series
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H A D | nvidia,tegra-audio-common.yaml | 16 - description: PLL A clock 17 - description: PLL A OUT0 clock
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/openbmc/linux/drivers/clk/samsung/ |
H A D | clk-exynos5250.c | 736 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, 738 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK, 740 [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, 742 [gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK, 744 [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, 746 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, 748 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
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H A D | clk-exynos5420.c | 1465 [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, 1467 [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, 1469 [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK, 1471 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, 1473 [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK, 1475 [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK, 1477 [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK, 1479 [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK, 1481 [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK, 1483 [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, [all …]
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/openbmc/linux/drivers/clk/starfive/ |
H A D | Kconfig | 25 bool "StarFive JH7110 PLL clock support" 29 Say yes here to support the PLL clock controller on the
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/openbmc/u-boot/board/freescale/mpc832xemds/ |
H A D | README | 28 SW3[1-8]= 0000_1000 (core PLL setting, core enable) 29 SW4[1-8]= 0001_0010 (Flash boot on local bus, system PLL setting) 32 SW7[1-8]= 1000_0011 (QE PLL setting)
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/openbmc/linux/Documentation/userspace-api/media/mediactl/ |
H A D | media-types.rst | 113 consists on a PLL tuning stage that converts radio frequency (RF) 115 internally IF-PLL decoders for audio and video, but older models 119 - IF-PLL video decoder. It receives the IF from a PLL and decodes 123 Those devices use a different I2C address than the tuner PLL. 126 - IF-PLL sound decoder. It receives the IF from a PLL and decodes 130 tuner PLL and should be controlled together with the IF-PLL video
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/openbmc/u-boot/cmd/aspeed/ |
H A D | Kconfig | 17 bool "ASPEED PLL test"
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