Home
last modified time | relevance | path

Searched refs:PLL (Results 76 – 100 of 294) sorted by relevance

12345678910>>...12

/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dbrcm,iproc-clocks.yaml16 LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
59 description: The input parent clock phandle for the PLL / ASIU clock. For
103 The following table defines the set of PLL/clock index and ID for Cygnus.
155 The following table defines the set of PLL/clock for Hurricane 2:
174 The following table defines the set of PLL/clock index and ID for Northstar and
209 The following table defines the set of PLL/clock index and ID for Northstar 2.
267 The following table defines the set of PLL/clock index and ID for Stingray.
H A Dqcom,hfpll.txt1 High-Frequency PLL (HFPLL)
36 Definition: Name of the PLL. Typically hfpllX where X is a CPU number
H A Daltr_socfpga.txt9 "altr,socfpga-pll-clock" - for a PLL clock
11 PLL clock.
H A Dsamsung,exynos-audss-clock.yaml31 Fixed rate PLL reference clock, parent of mout_audss. "fin_pll" is
34 Input PLL to the AudioSS block, parent of mout_audss. "fout_epll" is
H A Dqcom,lcc.yaml56 - description: PLL 4 Vote clock
90 - description: PLL 4 Vote clock
H A Dcirrus,cs2000-cp.yaml52 This mode allows the PLL to maintain lock even when CLK_IN
59 digital PLL of the silicon.
H A Dst,nomadik.txt23 PLL nodes: these nodes represent the two PLLs on the system,
27 Required properties for the two PLL nodes:
H A Drenesas,5p35023.yaml15 express applications. The 5P35023 device is a three PLL
16 architecture design, and each PLL is individually programmable
H A Dti-keystone-pllctrl.txt5 the NETCP modules) requires a PLL Controller to manage the various clock
H A Dallwinner,sun9i-a80-pll4-clk.yaml7 title: Allwinner A80 Peripheral PLL
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt8192-apmixedsys.c35 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ macro
67 PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
77 PLL(CLK_APMIXED_USBPLL, "usbpll", 0x03c4, 0x03cc, 0x00000000,
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dphy-rockchip-inno-hdmi.txt11 oscillator reference PLL clock input and "refpclk" for pclk-
12 based refeference PLL clock input.
H A Dsamsung,ufs-phy.yaml70 - description: PLL reference clock
86 - description: PLL reference clock
H A Dphy-stm32-usbphyc.yaml14 PLL configuration.
17 |_ PLL
49 description: regulator providing 1V1 power supply to the PLL block
52 description: regulator providing 1V8 power supply to the PLL block
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca15_a7.dts257 /* A15 PLL 0 reference clock */
266 /* A15 PLL 1 reference clock */
275 /* A7 PLL 0 reference clock */
284 /* A7 PLL 1 reference clock */
302 /* HDLCD PLL reference clock */
320 /* SYS PLL reference clock */
329 /* DDR2 PLL reference clock */
/openbmc/linux/drivers/clk/meson/
H A DKconfig110 tristate "Amlogic A1 SoC PLL controller support"
116 Support for the PLL clock controller on Amlogic A113L based
117 device, A1 SoC Family. Say Y if you want A1 PLL clock controller
/openbmc/linux/drivers/clk/rockchip/
H A Dclk-rk3188.c216 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
218 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
220 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
222 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
227 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
229 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
231 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
233 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dfsl,micfil.yaml45 - description: PLL clock source for 8kHz series
46 - description: PLL clock source for 11kHz series
H A Dnvidia,tegra-audio-common.yaml16 - description: PLL A clock
17 - description: PLL A OUT0 clock
/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos5250.c736 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
738 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
740 [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
742 [gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK,
744 [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
746 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
748 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
H A Dclk-exynos5420.c1465 [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
1467 [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
1469 [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK,
1471 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
1473 [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK,
1475 [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK,
1477 [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK,
1479 [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK,
1481 [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
1483 [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
[all …]
/openbmc/linux/drivers/clk/starfive/
H A DKconfig25 bool "StarFive JH7110 PLL clock support"
29 Say yes here to support the PLL clock controller on the
/openbmc/u-boot/board/freescale/mpc832xemds/
H A DREADME28 SW3[1-8]= 0000_1000 (core PLL setting, core enable)
29 SW4[1-8]= 0001_0010 (Flash boot on local bus, system PLL setting)
32 SW7[1-8]= 1000_0011 (QE PLL setting)
/openbmc/linux/Documentation/userspace-api/media/mediactl/
H A Dmedia-types.rst113 consists on a PLL tuning stage that converts radio frequency (RF)
115 internally IF-PLL decoders for audio and video, but older models
119 - IF-PLL video decoder. It receives the IF from a PLL and decodes
123 Those devices use a different I2C address than the tuner PLL.
126 - IF-PLL sound decoder. It receives the IF from a PLL and decodes
130 tuner PLL and should be controlled together with the IF-PLL video
/openbmc/u-boot/cmd/aspeed/
H A DKconfig17 bool "ASPEED PLL test"

12345678910>>...12