Searched hist:a12cf0a8 (Results 1 – 7 of 7) sorted by relevance
| /openbmc/linux/arch/m68k/include/asm/ |
| H A D | m52xxacr.h | a12cf0a8 Mon Nov 08 18:12:29 CST 2010 Greg Ungerer <gerg@uclinux.org> m68knommu: create bit definitions for the version 2 ColdFire cache controller
The version 2 ColdFire CPU based cores all contain a similar cache
controller unit. Create a set of bit flag definitions for the supporting
registers.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
a12cf0a8 Mon Nov 08 18:12:29 CST 2010 Greg Ungerer <gerg@uclinux.org> m68knommu: create bit definitions for the version 2 ColdFire cache controller
The version 2 ColdFire CPU based cores all contain a similar cache
controller unit. Create a set of bit flag definitions for the supporting
registers.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
|
| H A D | m5272sim.h | a12cf0a8 Mon Nov 08 18:12:29 CST 2010 Greg Ungerer <gerg@uclinux.org> m68knommu: create bit definitions for the version 2 ColdFire cache controller
The version 2 ColdFire CPU based cores all contain a similar cache
controller unit. Create a set of bit flag definitions for the supporting
registers.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
a12cf0a8 Mon Nov 08 18:12:29 CST 2010 Greg Ungerer <gerg@uclinux.org> m68knommu: create bit definitions for the version 2 ColdFire cache controller
The version 2 ColdFire CPU based cores all contain a similar cache
controller unit. Create a set of bit flag definitions for the supporting
registers.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
|
| H A D | m5206sim.h | a12cf0a8 Mon Nov 08 18:12:29 CST 2010 Greg Ungerer <gerg@uclinux.org> m68knommu: create bit definitions for the version 2 ColdFire cache controller
The version 2 ColdFire CPU based cores all contain a similar cache
controller unit. Create a set of bit flag definitions for the supporting
registers.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
a12cf0a8 Mon Nov 08 18:12:29 CST 2010 Greg Ungerer <gerg@uclinux.org> m68knommu: create bit definitions for the version 2 ColdFire cache controller
The version 2 ColdFire CPU based cores all contain a similar cache
controller unit. Create a set of bit flag definitions for the supporting
registers.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
|
| H A D | m520xsim.h | a12cf0a8 Mon Nov 08 18:12:29 CST 2010 Greg Ungerer <gerg@uclinux.org> m68knommu: create bit definitions for the version 2 ColdFire cache controller
The version 2 ColdFire CPU based cores all contain a similar cache
controller unit. Create a set of bit flag definitions for the supporting
registers.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
a12cf0a8 Mon Nov 08 18:12:29 CST 2010 Greg Ungerer <gerg@uclinux.org> m68knommu: create bit definitions for the version 2 ColdFire cache controller
The version 2 ColdFire CPU based cores all contain a similar cache
controller unit. Create a set of bit flag definitions for the supporting
registers.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
|
| H A D | m523xsim.h | a12cf0a8 Mon Nov 08 18:12:29 CST 2010 Greg Ungerer <gerg@uclinux.org> m68knommu: create bit definitions for the version 2 ColdFire cache controller
The version 2 ColdFire CPU based cores all contain a similar cache
controller unit. Create a set of bit flag definitions for the supporting
registers.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
a12cf0a8 Mon Nov 08 18:12:29 CST 2010 Greg Ungerer <gerg@uclinux.org> m68knommu: create bit definitions for the version 2 ColdFire cache controller
The version 2 ColdFire CPU based cores all contain a similar cache
controller unit. Create a set of bit flag definitions for the supporting
registers.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
|
| H A D | m528xsim.h | a12cf0a8 Mon Nov 08 18:12:29 CST 2010 Greg Ungerer <gerg@uclinux.org> m68knommu: create bit definitions for the version 2 ColdFire cache controller
The version 2 ColdFire CPU based cores all contain a similar cache
controller unit. Create a set of bit flag definitions for the supporting
registers.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
a12cf0a8 Mon Nov 08 18:12:29 CST 2010 Greg Ungerer <gerg@uclinux.org> m68knommu: create bit definitions for the version 2 ColdFire cache controller
The version 2 ColdFire CPU based cores all contain a similar cache
controller unit. Create a set of bit flag definitions for the supporting
registers.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
|
| H A D | m527xsim.h | a12cf0a8 Mon Nov 08 18:12:29 CST 2010 Greg Ungerer <gerg@uclinux.org> m68knommu: create bit definitions for the version 2 ColdFire cache controller
The version 2 ColdFire CPU based cores all contain a similar cache
controller unit. Create a set of bit flag definitions for the supporting
registers.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
a12cf0a8 Mon Nov 08 18:12:29 CST 2010 Greg Ungerer <gerg@uclinux.org> m68knommu: create bit definitions for the version 2 ColdFire cache controller
The version 2 ColdFire CPU based cores all contain a similar cache
controller unit. Create a set of bit flag definitions for the supporting
registers.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
|