1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 249148020SSam Ravnborg /****************************************************************************/ 349148020SSam Ravnborg 449148020SSam Ravnborg /* 549148020SSam Ravnborg * m520xsim.h -- ColdFire 5207/5208 System Integration Module support. 649148020SSam Ravnborg * 749148020SSam Ravnborg * (C) Copyright 2005, Intec Automation (mike@steroidmicros.com) 849148020SSam Ravnborg */ 949148020SSam Ravnborg 1049148020SSam Ravnborg /****************************************************************************/ 1149148020SSam Ravnborg #ifndef m520xsim_h 1249148020SSam Ravnborg #define m520xsim_h 1349148020SSam Ravnborg /****************************************************************************/ 1449148020SSam Ravnborg 157fc82b65SGreg Ungerer #define CPU_NAME "COLDFIRE(m520x)" 16733f31b7SGreg Ungerer #define CPU_INSTR_PER_JIFFY 3 17ce3de78aSGreg Ungerer #define MCF_BUSCLK (MCF_CLK / 2) 187fc82b65SGreg Ungerer 19a12cf0a8SGreg Ungerer #include <asm/m52xxacr.h> 20a12cf0a8SGreg Ungerer 2149148020SSam Ravnborg /* 22277c5e3eSGreg Ungerer * Define the 520x SIM register set addresses. 2349148020SSam Ravnborg */ 24571f0608SGreg Ungerer #define MCFICM_INTC0 0xFC048000 /* Base for Interrupt Ctrl 0 */ 2549148020SSam Ravnborg #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 2649148020SSam Ravnborg #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 2749148020SSam Ravnborg #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 2849148020SSam Ravnborg #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ 2949148020SSam Ravnborg #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ 3049148020SSam Ravnborg #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ 31cd3dd406SGreg Ungerer #define MCFINTC_SIMR 0x1c /* Set interrupt mask 0-63 */ 32cd3dd406SGreg Ungerer #define MCFINTC_CIMR 0x1d /* Clear interrupt mask 0-63 */ 3349148020SSam Ravnborg #define MCFINTC_ICR0 0x40 /* Base ICR register */ 3449148020SSam Ravnborg 35277c5e3eSGreg Ungerer /* 36277c5e3eSGreg Ungerer * The common interrupt controller code just wants to know the absolute 37277c5e3eSGreg Ungerer * address to the SIMR and CIMR registers (not offsets into IPSBAR). 38277c5e3eSGreg Ungerer * The 520x family only has a single INTC unit. 39277c5e3eSGreg Ungerer */ 40571f0608SGreg Ungerer #define MCFINTC0_SIMR (MCFICM_INTC0 + MCFINTC_SIMR) 41571f0608SGreg Ungerer #define MCFINTC0_CIMR (MCFICM_INTC0 + MCFINTC_CIMR) 42571f0608SGreg Ungerer #define MCFINTC0_ICR0 (MCFICM_INTC0 + MCFINTC_ICR0) 43277c5e3eSGreg Ungerer #define MCFINTC1_SIMR (0) 44277c5e3eSGreg Ungerer #define MCFINTC1_CIMR (0) 45277c5e3eSGreg Ungerer #define MCFINTC1_ICR0 (0) 4632234328SSteven King #define MCFINTC2_SIMR (0) 4732234328SSteven King #define MCFINTC2_CIMR (0) 4832234328SSteven King #define MCFINTC2_ICR0 (0) 49277c5e3eSGreg Ungerer 5049148020SSam Ravnborg #define MCFINT_VECBASE 64 5149148020SSam Ravnborg #define MCFINT_UART0 26 /* Interrupt number for UART0 */ 5249148020SSam Ravnborg #define MCFINT_UART1 27 /* Interrupt number for UART1 */ 5349148020SSam Ravnborg #define MCFINT_UART2 28 /* Interrupt number for UART2 */ 542d24b532SSteven King #define MCFINT_I2C0 30 /* Interrupt number for I2C */ 5549148020SSam Ravnborg #define MCFINT_QSPI 31 /* Interrupt number for QSPI */ 56d4e08372SGreg Ungerer #define MCFINT_FECRX0 36 /* Interrupt number for FEC RX */ 57d4e08372SGreg Ungerer #define MCFINT_FECTX0 40 /* Interrupt number for FEC RX */ 58d4e08372SGreg Ungerer #define MCFINT_FECENTC0 42 /* Interrupt number for FEC RX */ 5949148020SSam Ravnborg #define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */ 6049148020SSam Ravnborg 61ffc203bcSGreg Ungerer #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) 62ffc203bcSGreg Ungerer #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) 63ffc203bcSGreg Ungerer #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) 64ffc203bcSGreg Ungerer 65d4e08372SGreg Ungerer #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) 66d4e08372SGreg Ungerer #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) 67d4e08372SGreg Ungerer #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) 68d4e08372SGreg Ungerer 69a4e2e2acSGreg Ungerer #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) 70bdee4e26SSteven King #define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1) 71a4e2e2acSGreg Ungerer 722d24b532SSteven King #define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0) 7349148020SSam Ravnborg /* 7449148020SSam Ravnborg * SDRAM configuration registers. 7549148020SSam Ravnborg */ 76571f0608SGreg Ungerer #define MCFSIM_SDMR 0xFC0a8000 /* SDRAM Mode/Extended Mode Register */ 77571f0608SGreg Ungerer #define MCFSIM_SDCR 0xFC0a8004 /* SDRAM Control Register */ 78571f0608SGreg Ungerer #define MCFSIM_SDCFG1 0xFC0a8008 /* SDRAM Configuration Register 1 */ 79571f0608SGreg Ungerer #define MCFSIM_SDCFG2 0xFC0a800c /* SDRAM Configuration Register 2 */ 80571f0608SGreg Ungerer #define MCFSIM_SDCS0 0xFC0a8110 /* SDRAM Chip Select 0 Configuration */ 81571f0608SGreg Ungerer #define MCFSIM_SDCS1 0xFC0a8114 /* SDRAM Chip Select 1 Configuration */ 8249148020SSam Ravnborg 83a12cf0a8SGreg Ungerer /* 84a12cf0a8SGreg Ungerer * EPORT and GPIO registers. 85a12cf0a8SGreg Ungerer */ 8647e0c7e1SGreg Ungerer #define MCFEPORT_EPPAR 0xFC088000 87afde8560Ssfking@fdwdc.com #define MCFEPORT_EPDDR 0xFC088002 8847e0c7e1SGreg Ungerer #define MCFEPORT_EPIER 0xFC088003 89afde8560Ssfking@fdwdc.com #define MCFEPORT_EPDR 0xFC088004 90afde8560Ssfking@fdwdc.com #define MCFEPORT_EPPDR 0xFC088005 9147e0c7e1SGreg Ungerer #define MCFEPORT_EPFR 0xFC088006 92afde8560Ssfking@fdwdc.com 93afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_BUSCTL 0xFC0A4000 94afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_BE 0xFC0A4001 95afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_CS 0xFC0A4002 96afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_FECI2C 0xFC0A4003 97afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_QSPI 0xFC0A4004 98afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_TIMER 0xFC0A4005 99afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_UART 0xFC0A4006 100afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_FECH 0xFC0A4007 101afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_FECL 0xFC0A4008 102afde8560Ssfking@fdwdc.com 103afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_BUSCTL 0xFC0A400C 104afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_BE 0xFC0A400D 105afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_CS 0xFC0A400E 106afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_FECI2C 0xFC0A400F 107afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_QSPI 0xFC0A4010 108afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_TIMER 0xFC0A4011 109afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_UART 0xFC0A4012 110afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_FECH 0xFC0A4013 111afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_FECL 0xFC0A4014 112afde8560Ssfking@fdwdc.com 11389127ed3SPeter Turczak #define MCFGPIO_PPDSDR_CS 0xFC0A401A 11489127ed3SPeter Turczak #define MCFGPIO_PPDSDR_FECI2C 0xFC0A401B 11589127ed3SPeter Turczak #define MCFGPIO_PPDSDR_QSPI 0xFC0A401C 11689127ed3SPeter Turczak #define MCFGPIO_PPDSDR_TIMER 0xFC0A401D 11789127ed3SPeter Turczak #define MCFGPIO_PPDSDR_UART 0xFC0A401E 11889127ed3SPeter Turczak #define MCFGPIO_PPDSDR_FECH 0xFC0A401F 11989127ed3SPeter Turczak #define MCFGPIO_PPDSDR_FECL 0xFC0A4020 120afde8560Ssfking@fdwdc.com 121afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BUSCTL 0xFC0A4024 122afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BE 0xFC0A4025 123afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_CS 0xFC0A4026 124afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FECI2C 0xFC0A4027 125afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_QSPI 0xFC0A4028 126afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_TIMER 0xFC0A4029 127afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_UART 0xFC0A402A 128afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FECH 0xFC0A402B 129afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FECL 0xFC0A402C 13057015421SGreg Ungerer 131afde8560Ssfking@fdwdc.com /* 132afde8560Ssfking@fdwdc.com * Generic GPIO support 133afde8560Ssfking@fdwdc.com */ 13489127ed3SPeter Turczak #define MCFGPIO_PODR MCFGPIO_PODR_CS 13589127ed3SPeter Turczak #define MCFGPIO_PDDR MCFGPIO_PDDR_CS 13689127ed3SPeter Turczak #define MCFGPIO_PPDR MCFGPIO_PPDSDR_CS 13789127ed3SPeter Turczak #define MCFGPIO_SETR MCFGPIO_PPDSDR_CS 13889127ed3SPeter Turczak #define MCFGPIO_CLRR MCFGPIO_PCLRR_CS 139afde8560Ssfking@fdwdc.com 140afde8560Ssfking@fdwdc.com #define MCFGPIO_PIN_MAX 80 141afde8560Ssfking@fdwdc.com #define MCFGPIO_IRQ_MAX 8 142afde8560Ssfking@fdwdc.com #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 14349148020SSam Ravnborg 144571f0608SGreg Ungerer #define MCF_GPIO_PAR_UART 0xFC0A4036 145571f0608SGreg Ungerer #define MCF_GPIO_PAR_FECI2C 0xFC0A4033 146571f0608SGreg Ungerer #define MCF_GPIO_PAR_QSPI 0xFC0A4034 147571f0608SGreg Ungerer #define MCF_GPIO_PAR_FEC 0xFC0A4038 14849148020SSam Ravnborg 14949148020SSam Ravnborg #define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001) 15049148020SSam Ravnborg #define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002) 15149148020SSam Ravnborg 15249148020SSam Ravnborg #define MCF_GPIO_PAR_UART_PAR_URXD1 (0x0040) 15349148020SSam Ravnborg #define MCF_GPIO_PAR_UART_PAR_UTXD1 (0x0080) 15449148020SSam Ravnborg 15549148020SSam Ravnborg #define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02) 15649148020SSam Ravnborg #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) 15749148020SSam Ravnborg 15825ce4a90SGreg Ungerer /* 159f317c71aSGreg Ungerer * PIT timer module. 160f317c71aSGreg Ungerer */ 161f317c71aSGreg Ungerer #define MCFPIT_BASE1 0xFC080000 /* Base address of TIMER1 */ 162f317c71aSGreg Ungerer #define MCFPIT_BASE2 0xFC084000 /* Base address of TIMER2 */ 163f317c71aSGreg Ungerer 164f317c71aSGreg Ungerer /* 16557015421SGreg Ungerer * UART module. 16657015421SGreg Ungerer */ 167ffc203bcSGreg Ungerer #define MCFUART_BASE0 0xFC060000 /* Base address of UART0 */ 168ffc203bcSGreg Ungerer #define MCFUART_BASE1 0xFC064000 /* Base address of UART1 */ 169ffc203bcSGreg Ungerer #define MCFUART_BASE2 0xFC068000 /* Base address of UART2 */ 170571f0608SGreg Ungerer 171571f0608SGreg Ungerer /* 172571f0608SGreg Ungerer * FEC module. 173571f0608SGreg Ungerer */ 174d4e08372SGreg Ungerer #define MCFFEC_BASE0 0xFC030000 /* Base of FEC ethernet */ 175d4e08372SGreg Ungerer #define MCFFEC_SIZE0 0x800 /* Register set size */ 17657015421SGreg Ungerer 17757015421SGreg Ungerer /* 178a4e2e2acSGreg Ungerer * QSPI module. 179a4e2e2acSGreg Ungerer */ 180a4e2e2acSGreg Ungerer #define MCFQSPI_BASE 0xFC05C000 /* Base of QSPI module */ 181a4e2e2acSGreg Ungerer #define MCFQSPI_SIZE 0x40 /* Register set size */ 182a4e2e2acSGreg Ungerer 183a4e2e2acSGreg Ungerer #define MCFQSPI_CS0 46 184a4e2e2acSGreg Ungerer #define MCFQSPI_CS1 47 185a4e2e2acSGreg Ungerer #define MCFQSPI_CS2 27 186a4e2e2acSGreg Ungerer 187a4e2e2acSGreg Ungerer /* 18825985edcSLucas De Marchi * Reset Control Unit. 18925ce4a90SGreg Ungerer */ 19025ce4a90SGreg Ungerer #define MCF_RCR 0xFC0A0000 19125ce4a90SGreg Ungerer #define MCF_RSR 0xFC0A0001 19225ce4a90SGreg Ungerer 19325ce4a90SGreg Ungerer #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 19425ce4a90SGreg Ungerer #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 19525ce4a90SGreg Ungerer 196fe66158aSSteven King /* 197fe66158aSSteven King * Power Management. 198fe66158aSSteven King */ 199fe66158aSSteven King #define MCFPM_WCR 0xfc040013 200fe66158aSSteven King #define MCFPM_PPMSR0 0xfc04002c 201fe66158aSSteven King #define MCFPM_PPMCR0 0xfc04002d 202fe66158aSSteven King #define MCFPM_PPMHR0 0xfc040030 203fe66158aSSteven King #define MCFPM_PPMLR0 0xfc040034 204fe66158aSSteven King #define MCFPM_LPCR 0xfc0a0007 205fe66158aSSteven King 2062d24b532SSteven King /* 2072d24b532SSteven King * I2C module. 2082d24b532SSteven King */ 2092d24b532SSteven King #define MCFI2C_BASE0 0xFC058000 2102d24b532SSteven King #define MCFI2C_SIZE0 0x40 2112d24b532SSteven King 21249148020SSam Ravnborg /****************************************************************************/ 21349148020SSam Ravnborg #endif /* m520xsim_h */ 214