xref: /openbmc/linux/arch/m68k/include/asm/m52xxacr.h (revision b2441318)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /****************************************************************************/
3 
4 /*
5  * m52xxacr.h -- ColdFire version 2 core cache support
6  *
7  * (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com>
8  */
9 
10 /****************************************************************************/
11 #ifndef m52xxacr_h
12 #define m52xxacr_h
13 /****************************************************************************/
14 
15 /*
16  * All varients of the ColdFire using version 2 cores have a similar
17  * cache setup. Although not absolutely identical the cache register
18  * definitions are compatible for all of them. Mostly they support a
19  * configurable cache memory that can be instruction only, data only,
20  * or split instruction and data. The exception is the very old version 2
21  * core based parts, like the 5206(e), 5249 and 5272, which are instruction
22  * cache only. Cache size varies from 2k up to 16k.
23  */
24 
25 /*
26  * Define the Cache Control register flags.
27  */
28 #define CACR_CENB	0x80000000	/* Enable cache */
29 #define CACR_CDPI	0x10000000	/* Disable invalidation by CPUSHL */
30 #define CACR_CFRZ	0x08000000	/* Cache freeze mode */
31 #define CACR_CINV	0x01000000	/* Invalidate cache */
32 #define CACR_DISI	0x00800000	/* Disable instruction cache */
33 #define CACR_DISD	0x00400000	/* Disable data cache */
34 #define CACR_INVI	0x00200000	/* Invalidate instruction cache */
35 #define CACR_INVD	0x00100000	/* Invalidate data cache */
36 #define CACR_CEIB	0x00000400	/* Non-cachable instruction burst */
37 #define CACR_DCM	0x00000200	/* Default cache mode */
38 #define CACR_DBWE	0x00000100	/* Buffered write enable */
39 #define CACR_DWP	0x00000020	/* Write protection */
40 #define CACR_EUSP	0x00000010	/* Enable separate user a7 */
41 
42 /*
43  * Define the Access Control register flags.
44  */
45 #define ACR_BASE_POS	24		/* Address Base (upper 8 bits) */
46 #define ACR_MASK_POS	16		/* Address Mask (next 8 bits) */
47 #define ACR_ENABLE	0x00008000	/* Enable this ACR */
48 #define ACR_USER	0x00000000	/* Allow only user accesses */
49 #define ACR_SUPER	0x00002000	/* Allow supervisor access only */
50 #define ACR_ANY		0x00004000	/* Allow any access type */
51 #define ACR_CENB	0x00000000	/* Caching of region enabled */
52 #define ACR_CDIS	0x00000040	/* Caching of region disabled */
53 #define ACR_BWE		0x00000020	/* Write buffer enabled */
54 #define ACR_WPROTECT	0x00000004	/* Write protect region */
55 
56 /*
57  * Set the cache controller settings we will use. On the cores that support
58  * a split cache configuration we allow all the combinations at Kconfig
59  * time. For those cores that only have an instruction cache we just set
60  * that as on.
61  */
62 #if defined(CONFIG_CACHE_I)
63 #define CACHE_TYPE	(CACR_DISD + CACR_EUSP)
64 #define CACHE_INVTYPEI	0
65 #elif defined(CONFIG_CACHE_D)
66 #define CACHE_TYPE	(CACR_DISI + CACR_EUSP)
67 #define CACHE_INVTYPED	0
68 #elif defined(CONFIG_CACHE_BOTH)
69 #define CACHE_TYPE	CACR_EUSP
70 #define CACHE_INVTYPEI	CACR_INVI
71 #define CACHE_INVTYPED	CACR_INVD
72 #else
73 /* This is the instruction cache only devices (no split cache, no eusp) */
74 #define CACHE_TYPE	0
75 #define CACHE_INVTYPEI	0
76 #endif
77 
78 #define CACHE_INIT	(CACR_CINV + CACHE_TYPE)
79 #define CACHE_MODE	(CACR_CENB + CACHE_TYPE + CACR_DCM)
80 
81 #define CACHE_INVALIDATE  (CACHE_MODE + CACR_CINV)
82 #if defined(CACHE_INVTYPEI)
83 #define CACHE_INVALIDATEI (CACHE_MODE + CACR_CINV + CACHE_INVTYPEI)
84 #endif
85 #if defined(CACHE_INVTYPED)
86 #define CACHE_INVALIDATED (CACHE_MODE + CACR_CINV + CACHE_INVTYPED)
87 #endif
88 
89 #define ACR0_MODE	((CONFIG_RAMBASE & 0xff000000) + \
90 			 (0x000f0000) + \
91 			 (ACR_ENABLE + ACR_ANY + ACR_CENB + ACR_BWE))
92 #define ACR1_MODE	0
93 
94 /****************************************************************************/
95 #endif  /* m52xxsim_h */
96