Searched hist:"3 a3c9dc4" (Results 1 – 6 of 6) sorted by relevance
| /openbmc/qemu/target/xtensa/ |
| H A D | helper.h | 3a3c9dc4 Sat Nov 26 05:48:41 CST 2011 Max Filippov <jcmvbkbc@gmail.com> target-xtensa: implement RER/WER instructions
RER and WER are privileged instructions for accessing external
registers. External register address space is local to processor core.
There's no alignment requirements, addressable units are 32-bit wide
registers.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
|
| H A D | overlay_tool.h | 3a3c9dc4 Sat Nov 26 05:48:41 CST 2011 Max Filippov <jcmvbkbc@gmail.com> target-xtensa: implement RER/WER instructions
RER and WER are privileged instructions for accessing external
registers. External register address space is local to processor core.
There's no alignment requirements, addressable units are 32-bit wide
registers.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
|
| H A D | op_helper.c | 3a3c9dc4 Sat Nov 26 05:48:41 CST 2011 Max Filippov <jcmvbkbc@gmail.com> target-xtensa: implement RER/WER instructions
RER and WER are privileged instructions for accessing external
registers. External register address space is local to processor core.
There's no alignment requirements, addressable units are 32-bit wide
registers.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
|
| H A D | cpu.c | 3a3c9dc4 Sat Nov 26 05:48:41 CST 2011 Max Filippov <jcmvbkbc@gmail.com> target-xtensa: implement RER/WER instructions
RER and WER are privileged instructions for accessing external
registers. External register address space is local to processor core.
There's no alignment requirements, addressable units are 32-bit wide
registers.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
|
| H A D | cpu.h | 3a3c9dc4 Sat Nov 26 05:48:41 CST 2011 Max Filippov <jcmvbkbc@gmail.com> target-xtensa: implement RER/WER instructions
RER and WER are privileged instructions for accessing external
registers. External register address space is local to processor core.
There's no alignment requirements, addressable units are 32-bit wide
registers.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
|
| H A D | translate.c | 3a3c9dc4 Sat Nov 26 05:48:41 CST 2011 Max Filippov <jcmvbkbc@gmail.com> target-xtensa: implement RER/WER instructions
RER and WER are privileged instructions for accessing external
registers. External register address space is local to processor core.
There's no alignment requirements, addressable units are 32-bit wide
registers.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
|