1fcf5ef2aSThomas Huth /*
2fcf5ef2aSThomas Huth * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
3fcf5ef2aSThomas Huth * All rights reserved.
4fcf5ef2aSThomas Huth *
5fcf5ef2aSThomas Huth * Redistribution and use in source and binary forms, with or without
6fcf5ef2aSThomas Huth * modification, are permitted provided that the following conditions are met:
7fcf5ef2aSThomas Huth * * Redistributions of source code must retain the above copyright
8fcf5ef2aSThomas Huth * notice, this list of conditions and the following disclaimer.
9fcf5ef2aSThomas Huth * * Redistributions in binary form must reproduce the above copyright
10fcf5ef2aSThomas Huth * notice, this list of conditions and the following disclaimer in the
11fcf5ef2aSThomas Huth * documentation and/or other materials provided with the distribution.
12fcf5ef2aSThomas Huth * * Neither the name of the Open Source and Linux Lab nor the
13fcf5ef2aSThomas Huth * names of its contributors may be used to endorse or promote products
14fcf5ef2aSThomas Huth * derived from this software without specific prior written permission.
15fcf5ef2aSThomas Huth *
16fcf5ef2aSThomas Huth * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17fcf5ef2aSThomas Huth * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18fcf5ef2aSThomas Huth * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19fcf5ef2aSThomas Huth * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20fcf5ef2aSThomas Huth * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21fcf5ef2aSThomas Huth * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22fcf5ef2aSThomas Huth * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23fcf5ef2aSThomas Huth * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24fcf5ef2aSThomas Huth * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25fcf5ef2aSThomas Huth * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26fcf5ef2aSThomas Huth */
27fcf5ef2aSThomas Huth
28fcf5ef2aSThomas Huth #include "qemu/osdep.h"
29fcf5ef2aSThomas Huth #include "cpu.h"
30fcf5ef2aSThomas Huth #include "exec/helper-proto.h"
31fcf5ef2aSThomas Huth #include "qemu/host-utils.h"
32fcf5ef2aSThomas Huth #include "exec/exec-all.h"
33b8be0524SPhilippe Mathieu-Daudé #include "qemu/atomic.h"
34fcf5ef2aSThomas Huth #include "qemu/timer.h"
35fcf5ef2aSThomas Huth
36ba7651fbSMax Filippov #ifndef CONFIG_USER_ONLY
37ba7651fbSMax Filippov
HELPER(update_ccount)3859a71f75SMax Filippov void HELPER(update_ccount)(CPUXtensaState *env)
39fcf5ef2aSThomas Huth {
40*bcb9d2eaSPhilippe Mathieu-Daudé XtensaCPU *cpu = env_archcpu(env);
4159a71f75SMax Filippov uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
4259a71f75SMax Filippov
4359a71f75SMax Filippov env->ccount_time = now;
4459a71f75SMax Filippov env->sregs[CCOUNT] = env->ccount_base +
459e377be1SMax Filippov (uint32_t)clock_ns_to_ticks(cpu->clock, now - env->time_base);
46fcf5ef2aSThomas Huth }
47fcf5ef2aSThomas Huth
HELPER(wsr_ccount)4859a71f75SMax Filippov void HELPER(wsr_ccount)(CPUXtensaState *env, uint32_t v)
49fcf5ef2aSThomas Huth {
5059a71f75SMax Filippov int i;
5159a71f75SMax Filippov
5259a71f75SMax Filippov HELPER(update_ccount)(env);
5359a71f75SMax Filippov env->ccount_base += v - env->sregs[CCOUNT];
5459a71f75SMax Filippov for (i = 0; i < env->config->nccompare; ++i) {
5559a71f75SMax Filippov HELPER(update_ccompare)(env, i);
5659a71f75SMax Filippov }
5759a71f75SMax Filippov }
5859a71f75SMax Filippov
HELPER(update_ccompare)5959a71f75SMax Filippov void HELPER(update_ccompare)(CPUXtensaState *env, uint32_t i)
6059a71f75SMax Filippov {
61*bcb9d2eaSPhilippe Mathieu-Daudé XtensaCPU *cpu = env_archcpu(env);
6259a71f75SMax Filippov uint64_t dcc;
6359a71f75SMax Filippov
64d73415a3SStefan Hajnoczi qatomic_and(&env->sregs[INTSET],
65fa92bd4aSMax Filippov ~(1u << env->config->timerint[i]));
6659a71f75SMax Filippov HELPER(update_ccount)(env);
6759a71f75SMax Filippov dcc = (uint64_t)(env->sregs[CCOMPARE + i] - env->sregs[CCOUNT] - 1) + 1;
6859a71f75SMax Filippov timer_mod(env->ccompare[i].timer,
699e377be1SMax Filippov env->ccount_time + clock_ticks_to_ns(cpu->clock, dcc));
70d2132510SMax Filippov env->yield_needed = 1;
71fcf5ef2aSThomas Huth }
72fcf5ef2aSThomas Huth
73fcf5ef2aSThomas Huth /*!
74fcf5ef2aSThomas Huth * Check vaddr accessibility/cache attributes and raise an exception if
75fcf5ef2aSThomas Huth * specified by the ATOMCTL SR.
76fcf5ef2aSThomas Huth *
77fcf5ef2aSThomas Huth * Note: local memory exclusion is not implemented
78fcf5ef2aSThomas Huth */
HELPER(check_atomctl)79fcf5ef2aSThomas Huth void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr)
80fcf5ef2aSThomas Huth {
81fcf5ef2aSThomas Huth uint32_t paddr, page_size, access;
82fcf5ef2aSThomas Huth uint32_t atomctl = env->sregs[ATOMCTL];
83fcf5ef2aSThomas Huth int rc = xtensa_get_physical_addr(env, true, vaddr, 1,
84fcf5ef2aSThomas Huth xtensa_get_cring(env), &paddr, &page_size, &access);
85fcf5ef2aSThomas Huth
86fcf5ef2aSThomas Huth /*
87fcf5ef2aSThomas Huth * s32c1i never causes LOAD_PROHIBITED_CAUSE exceptions,
88fcf5ef2aSThomas Huth * see opcode description in the ISA
89fcf5ef2aSThomas Huth */
90fcf5ef2aSThomas Huth if (rc == 0 &&
91fcf5ef2aSThomas Huth (access & (PAGE_READ | PAGE_WRITE)) != (PAGE_READ | PAGE_WRITE)) {
92fcf5ef2aSThomas Huth rc = STORE_PROHIBITED_CAUSE;
93fcf5ef2aSThomas Huth }
94fcf5ef2aSThomas Huth
95fcf5ef2aSThomas Huth if (rc) {
96fcf5ef2aSThomas Huth HELPER(exception_cause_vaddr)(env, pc, rc, vaddr);
97fcf5ef2aSThomas Huth }
98fcf5ef2aSThomas Huth
99fcf5ef2aSThomas Huth /*
100fcf5ef2aSThomas Huth * When data cache is not configured use ATOMCTL bypass field.
101fcf5ef2aSThomas Huth * See ISA, 4.3.12.4 The Atomic Operation Control Register (ATOMCTL)
102fcf5ef2aSThomas Huth * under the Conditional Store Option.
103fcf5ef2aSThomas Huth */
104fcf5ef2aSThomas Huth if (!xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) {
105fcf5ef2aSThomas Huth access = PAGE_CACHE_BYPASS;
106fcf5ef2aSThomas Huth }
107fcf5ef2aSThomas Huth
108fcf5ef2aSThomas Huth switch (access & PAGE_CACHE_MASK) {
109fcf5ef2aSThomas Huth case PAGE_CACHE_WB:
110fcf5ef2aSThomas Huth atomctl >>= 2;
111fcf5ef2aSThomas Huth /* fall through */
112fcf5ef2aSThomas Huth case PAGE_CACHE_WT:
113fcf5ef2aSThomas Huth atomctl >>= 2;
114fcf5ef2aSThomas Huth /* fall through */
115fcf5ef2aSThomas Huth case PAGE_CACHE_BYPASS:
116fcf5ef2aSThomas Huth if ((atomctl & 0x3) == 0) {
117fcf5ef2aSThomas Huth HELPER(exception_cause_vaddr)(env, pc,
118fcf5ef2aSThomas Huth LOAD_STORE_ERROR_CAUSE, vaddr);
119fcf5ef2aSThomas Huth }
120fcf5ef2aSThomas Huth break;
121fcf5ef2aSThomas Huth
122fcf5ef2aSThomas Huth case PAGE_CACHE_ISOLATE:
123fcf5ef2aSThomas Huth HELPER(exception_cause_vaddr)(env, pc,
124fcf5ef2aSThomas Huth LOAD_STORE_ERROR_CAUSE, vaddr);
125fcf5ef2aSThomas Huth break;
126fcf5ef2aSThomas Huth
127fcf5ef2aSThomas Huth default:
128fcf5ef2aSThomas Huth break;
129fcf5ef2aSThomas Huth }
130fcf5ef2aSThomas Huth }
131fcf5ef2aSThomas Huth
HELPER(check_exclusive)132b345e140SMax Filippov void HELPER(check_exclusive)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr,
133b345e140SMax Filippov uint32_t is_write)
134b345e140SMax Filippov {
135b345e140SMax Filippov uint32_t paddr, page_size, access;
136b345e140SMax Filippov uint32_t atomctl = env->sregs[ATOMCTL];
137b345e140SMax Filippov int rc = xtensa_get_physical_addr(env, true, vaddr, is_write,
138b345e140SMax Filippov xtensa_get_cring(env), &paddr,
139b345e140SMax Filippov &page_size, &access);
140b345e140SMax Filippov
141b345e140SMax Filippov if (rc) {
142b345e140SMax Filippov HELPER(exception_cause_vaddr)(env, pc, rc, vaddr);
143b345e140SMax Filippov }
144b345e140SMax Filippov
145b345e140SMax Filippov /* When data cache is not configured use ATOMCTL bypass field. */
146b345e140SMax Filippov if (!xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) {
147b345e140SMax Filippov access = PAGE_CACHE_BYPASS;
148b345e140SMax Filippov }
149b345e140SMax Filippov
150b345e140SMax Filippov switch (access & PAGE_CACHE_MASK) {
151b345e140SMax Filippov case PAGE_CACHE_WB:
152b345e140SMax Filippov atomctl >>= 2;
153b345e140SMax Filippov /* fall through */
154b345e140SMax Filippov case PAGE_CACHE_WT:
155b345e140SMax Filippov atomctl >>= 2;
156b345e140SMax Filippov /* fall through */
157b345e140SMax Filippov case PAGE_CACHE_BYPASS:
158b345e140SMax Filippov if ((atomctl & 0x3) == 0) {
159b345e140SMax Filippov HELPER(exception_cause_vaddr)(env, pc,
160b345e140SMax Filippov EXCLUSIVE_ERROR_CAUSE, vaddr);
161b345e140SMax Filippov }
162b345e140SMax Filippov break;
163b345e140SMax Filippov
164b345e140SMax Filippov case PAGE_CACHE_ISOLATE:
165b345e140SMax Filippov HELPER(exception_cause_vaddr)(env, pc,
166b345e140SMax Filippov LOAD_STORE_ERROR_CAUSE, vaddr);
167b345e140SMax Filippov break;
168b345e140SMax Filippov
169b345e140SMax Filippov default:
170b345e140SMax Filippov break;
171b345e140SMax Filippov }
172b345e140SMax Filippov }
173b345e140SMax Filippov
HELPER(wsr_memctl)1749e03ade4SMax Filippov void HELPER(wsr_memctl)(CPUXtensaState *env, uint32_t v)
1759e03ade4SMax Filippov {
1769e03ade4SMax Filippov if (xtensa_option_enabled(env->config, XTENSA_OPTION_ICACHE)) {
1779e03ade4SMax Filippov if (extract32(v, MEMCTL_IUSEWAYS_SHIFT, MEMCTL_IUSEWAYS_LEN) >
1789e03ade4SMax Filippov env->config->icache_ways) {
1799e03ade4SMax Filippov deposit32(v, MEMCTL_IUSEWAYS_SHIFT, MEMCTL_IUSEWAYS_LEN,
1809e03ade4SMax Filippov env->config->icache_ways);
1819e03ade4SMax Filippov }
1829e03ade4SMax Filippov }
1839e03ade4SMax Filippov if (xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) {
1849e03ade4SMax Filippov if (extract32(v, MEMCTL_DUSEWAYS_SHIFT, MEMCTL_DUSEWAYS_LEN) >
1859e03ade4SMax Filippov env->config->dcache_ways) {
1869e03ade4SMax Filippov deposit32(v, MEMCTL_DUSEWAYS_SHIFT, MEMCTL_DUSEWAYS_LEN,
1879e03ade4SMax Filippov env->config->dcache_ways);
1889e03ade4SMax Filippov }
1899e03ade4SMax Filippov if (extract32(v, MEMCTL_DALLOCWAYS_SHIFT, MEMCTL_DALLOCWAYS_LEN) >
1909e03ade4SMax Filippov env->config->dcache_ways) {
1919e03ade4SMax Filippov deposit32(v, MEMCTL_DALLOCWAYS_SHIFT, MEMCTL_DALLOCWAYS_LEN,
1929e03ade4SMax Filippov env->config->dcache_ways);
1939e03ade4SMax Filippov }
1949e03ade4SMax Filippov }
1959e03ade4SMax Filippov env->sregs[MEMCTL] = v & env->config->memctl_mask;
1969e03ade4SMax Filippov }
1979e03ade4SMax Filippov
198ba7651fbSMax Filippov #endif
199fcf5ef2aSThomas Huth
HELPER(rer)2003a3c9dc4SMax Filippov uint32_t HELPER(rer)(CPUXtensaState *env, uint32_t addr)
2013a3c9dc4SMax Filippov {
202ba7651fbSMax Filippov #ifndef CONFIG_USER_ONLY
2033a3c9dc4SMax Filippov return address_space_ldl(env->address_space_er, addr,
2042c5b1d2aSAlistair Francis MEMTXATTRS_UNSPECIFIED, NULL);
205ba7651fbSMax Filippov #else
206ba7651fbSMax Filippov return 0;
207ba7651fbSMax Filippov #endif
2083a3c9dc4SMax Filippov }
2093a3c9dc4SMax Filippov
HELPER(wer)2103a3c9dc4SMax Filippov void HELPER(wer)(CPUXtensaState *env, uint32_t data, uint32_t addr)
2113a3c9dc4SMax Filippov {
212ba7651fbSMax Filippov #ifndef CONFIG_USER_ONLY
2133a3c9dc4SMax Filippov address_space_stl(env->address_space_er, addr, data,
2142c5b1d2aSAlistair Francis MEMTXATTRS_UNSPECIFIED, NULL);
215ba7651fbSMax Filippov #endif
2163a3c9dc4SMax Filippov }
217