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ee3eb3a7 |
| 23-Mar-2022 |
Marc-André Lureau <marcandre.lureau@redhat.com> |
Replace TARGET_WORDS_BIGENDIAN
Convert the TARGET_WORDS_BIGENDIAN macro, similarly to what was done with HOST_BIG_ENDIAN. The new TARGET_BIG_ENDIAN macro is either 0 or 1, and thus should always be
Replace TARGET_WORDS_BIGENDIAN
Convert the TARGET_WORDS_BIGENDIAN macro, similarly to what was done with HOST_BIG_ENDIAN. The new TARGET_BIG_ENDIAN macro is either 0 or 1, and thus should always be defined to prevent misuse.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Suggested-by: Halil Pasic <pasic@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220323155743.1585078-8-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Revision tags: v6.2.0, v6.1.0 |
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#
8e49197c |
| 26-Aug-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/hdeller/tags/target-hppa-v3-pull-request' into staging artist out of bounds fixes # gpg: Signature made Wed 26 Aug 2020 22:09:55 BST # gpg:
Merge remote-tracking branch 'remotes/hdeller/tags/target-hppa-v3-pull-request' into staging artist out of bounds fixes # gpg: Signature made Wed 26 Aug 2020 22:09:55 BST # gpg: using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F # gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown] # gpg: aka "Helge Deller <deller@kernel.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 4544 8228 2CD9 10DB EF3D 25F8 3E5F 3D04 A7A2 4603 # Subkey fingerprint: BCE9 123E 1AD2 9F07 C049 BBDE F712 B510 A23A 0F5F * remotes/hdeller/tags/target-hppa-v3-pull-request: hw/display/artist: Fix invalidation of lines near screen border hw/display/artist: Fix invalidation of lines in artist_draw_line() hw/display/artist: Unbreak size mismatch memory accesses hw/display/artist: Prevent out of VRAM buffer accesses Revert "hw/display/artist: Avoid drawing line when nothing to display" hw/display/artist: Refactor artist_rop8() to avoid buffer over-run hw/display/artist: Check offset in draw_line to avoid buffer over-run hw/hppa/lasi: Don't abort on invalid IMR value hw/display/artist.c: fix out of bounds check hw/hppa: Implement proper SeaBIOS version check seabios-hppa: Update to SeaBIOS hppa version 1 hw/hppa: Sync hppa_hardware.h file with SeaBIOS sources Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
25f6dc28 |
| 26-Aug-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/maxreitz/tags/pull-block-2020-08-26' into staging Block patches: - qcow2 subclusters (extended L2 entries) # gpg: Signature made Wed 26 Aug
Merge remote-tracking branch 'remotes/maxreitz/tags/pull-block-2020-08-26' into staging Block patches: - qcow2 subclusters (extended L2 entries) # gpg: Signature made Wed 26 Aug 2020 08:37:04 BST # gpg: using RSA key 91BEB60A30DB3E8857D11829F407DB0061D5CF40 # gpg: issuer "mreitz@redhat.com" # gpg: Good signature from "Max Reitz <mreitz@redhat.com>" [full] # Primary key fingerprint: 91BE B60A 30DB 3E88 57D1 1829 F407 DB00 61D5 CF40 * remotes/maxreitz/tags/pull-block-2020-08-26: (34 commits) iotests: Add tests for qcow2 images with extended L2 entries qcow2: Assert that expand_zero_clusters_in_l1() does not support subclusters qcow2: Allow preallocation and backing files if extended_l2 is set qcow2: Add the 'extended_l2' option and the QCOW2_INCOMPAT_EXTL2 bit qcow2: Add prealloc field to QCowL2Meta qcow2: Add subcluster support to qcow2_measure() qcow2: Add subcluster support to qcow2_co_pwrite_zeroes() qcow2: Add subcluster support to handle_alloc_space() qcow2: Clear the L2 bitmap when allocating a compressed cluster qcow2: Update L2 bitmap in qcow2_alloc_cluster_link_l2() qcow2: Add subcluster support to check_refcounts_l2() qcow2: Add subcluster support to discard_in_l2_slice() qcow2: Add subcluster support to zero_in_l2_slice() qcow2: Add subcluster support to qcow2_get_host_offset() qcow2: Add subcluster support to calculate_l2_meta() qcow2: Handle QCOW2_SUBCLUSTER_UNALLOCATED_ALLOC qcow2: Replace QCOW2_CLUSTER_* with QCOW2_SUBCLUSTER_* qcow2: Add cluster type parameter to qcow2_get_host_offset() qcow2: Add qcow2_cluster_is_allocated() qcow2: Add qcow2_get_subcluster_range_type() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
7774e403 |
| 25-Aug-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/kraxel/tags/fixes-20200825-pull-request' into staging meson: keymap fixes # gpg: Signature made Tue 25 Aug 2020 07:19:15 BST # gpg:
Merge remote-tracking branch 'remotes/kraxel/tags/fixes-20200825-pull-request' into staging meson: keymap fixes # gpg: Signature made Tue 25 Aug 2020 07:19:15 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/fixes-20200825-pull-request: meson: avoid compiling qemu-keymap by default meson: move xkbcommon to meson meson: drop keymaps symlink Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
44423107 |
| 24-Aug-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/xtensa/tags/20200821-xtensa' into staging target/xtensa updates for 5.2: - add NMI support; - add DFPU option implementation; - update
Merge remote-tracking branch 'remotes/xtensa/tags/20200821-xtensa' into staging target/xtensa updates for 5.2: - add NMI support; - add DFPU option implementation; - update FPU tests to support both FPU2000 and DFPU; - add example cores with FPU2000 and DFPU. # gpg: Signature made Fri 21 Aug 2020 21:09:37 BST # gpg: using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044 # gpg: issuer "jcmvbkbc@gmail.com" # gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown] # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" [full] # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" [full] # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20200821-xtensa: (24 commits) target/xtensa: import DSP3400 core target/xtensa: import de233_fpu core tests/tcg/xtensa: add DFP0 arithmetic tests tests/tcg/xtensa: test double precision load/store tests/tcg/xtensa: add fp0 div and sqrt tests tests/tcg/xtensa: update test_lsc for DFPU tests/tcg/xtensa: update test_fp1 for DFPU tests/tcg/xtensa: update test_fp0_conv for DFPU tests/tcg/xtensa: expand madd tests tests/tcg/xtensa: update test_fp0_arith for DFPU tests/tcg/xtensa: fix test execution on ISS target/xtensa: implement FPU division and square root target/xtensa: add DFPU registers and opcodes target/xtensa: add DFPU option target/xtensa: don't access BR regfile directly target/xtensa: move FSR/FCR register accessors target/xtensa: rename FPU2000 translators and helpers target/xtensa: support copying registers up to 64 bits wide target/xtensa: add geometry to xtensa_get_regfile_by_name softfloat: add xtensa specialization for pickNaNMulAdd ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
cfa9f051 |
| 30-Jun-2020 |
Max Filippov <jcmvbkbc@gmail.com> |
target/xtensa: add DFPU registers and opcodes DFPU may be configured with 32-bit or with 64-bit registers. Xtensa ISA does not specify how single-precision values are stored in 64-bit
target/xtensa: add DFPU registers and opcodes DFPU may be configured with 32-bit or with 64-bit registers. Xtensa ISA does not specify how single-precision values are stored in 64-bit registers. Existing implementations store them in the low half of the registers. Add value extraction and write back to single-precision opcodes. Add new double precision opcodes. Add 64-bit register file. Add 64-bit values dumping to the xtensa_cpu_dump_state. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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#
de6b55cb |
| 11-Jul-2020 |
Max Filippov <jcmvbkbc@gmail.com> |
target/xtensa: add DFPU option Double precision floating point unit is a FPU implementation different from the FPU2000 in the following ways: - it may be configured with only single
target/xtensa: add DFPU option Double precision floating point unit is a FPU implementation different from the FPU2000 in the following ways: - it may be configured with only single or with both single and double precision operations support; - it may be configured with division and square root opcodes; - FSR register accumulates inValid, division by Zero, Overflow, Underflow and Inexact result flags of operations; - QNaNs and SNaNs are handled properly; - NaN propagation rules are different. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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#
a7d479ee |
| 05-Jul-2020 |
Max Filippov <jcmvbkbc@gmail.com> |
target/xtensa: implement NMI support When NMI is configured it is taken regardless of INTENABLE SR contents, PS.INTLEVEL or PS.EXCM. It is cleared automatically once it's taken.
target/xtensa: implement NMI support When NMI is configured it is taken regardless of INTENABLE SR contents, PS.INTLEVEL or PS.EXCM. It is cleared automatically once it's taken. Add nmi_level to XtensaConfig, puth there NMI level from the overlay or XCHAL_NUM_INTLEVELS + 1 when NMI is not configured. Add NMI mask to INTENABLE SR and limit CINTLEVEL to nmi_level - 1 when determining pending IRQ level in check_interrupt(). Always take and clear pending interrupt at nmi_level in the handle_interrupt(). Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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#
4abf70a6 |
| 03-Jul-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/maxreitz/tags/pull-block-2020-06-24' into staging Block patches: - Two iotest fixes # gpg: Signature made Wed 24 Jun 2020 09:00:51 BST
Merge remote-tracking branch 'remotes/maxreitz/tags/pull-block-2020-06-24' into staging Block patches: - Two iotest fixes # gpg: Signature made Wed 24 Jun 2020 09:00:51 BST # gpg: using RSA key 91BEB60A30DB3E8857D11829F407DB0061D5CF40 # gpg: issuer "mreitz@redhat.com" # gpg: Good signature from "Max Reitz <mreitz@redhat.com>" [full] # Primary key fingerprint: 91BE B60A 30DB 3E88 57D1 1829 F407 DB00 61D5 CF40 * remotes/maxreitz/tags/pull-block-2020-06-24: iotests: don't test qcow2.py inside 291 iotests: Fix 051 output after qdev_init_nofail() removal Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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87fb952d |
| 26-Jun-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging Pull request # gpg: Signature made Wed 24 Jun 2020 11:01:57 BST # gpg: using
Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging Pull request # gpg: Signature made Wed 24 Jun 2020 11:01:57 BST # gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [full] # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [full] # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/block-pull-request: block/nvme: support nested aio_poll() block/nvme: keep BDRVNVMeState pointer in NVMeQueuePair block/nvme: clarify that free_req_queue is protected by q->lock block/nvme: switch to a NVMeRequest freelist block/nvme: don't access CQE after moving cq.head block/nvme: drop tautologous assertion block/nvme: poll queues without q->lock check-block: enable iotests with SafeStack configure: add flags to support SafeStack coroutine: add check for SafeStack in sigaltstack coroutine: support SafeStack in ucontext backend minikconf: explicitly set encoding to UTF-8 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
611ac633 |
| 26-Jun-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.1-20200626' into staging ppc patch queue 2020-06-26 Here's another pull request for qemu-5.1. Not very much in this one
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.1-20200626' into staging ppc patch queue 2020-06-26 Here's another pull request for qemu-5.1. Not very much in this one, just a handful of assorted minor fixes and cleanups. I'm about to go on holiday for a couple of weeks, so this will be my last PR before the freeze, and maybe the last for 5.1 at all. If there's some super important fix we need, Greg Kurz will handle it. # gpg: Signature made Fri 26 Jun 2020 07:36:59 BST # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-5.1-20200626: target/ppc: Remove TIDR from POWER10 processor ppc/pnv: Silence missing BMC warning with qtest spapr: Fix typos in comments and macro indentation spapr: Simplify some warning printing paths in spapr_caps.c Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
5acc270a |
| 25-Jun-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/xtensa/tags/20200625-xtensa' into staging target/xtensa fixes for 5.1: - fix access to special registers missing in the core configuration;
Merge remote-tracking branch 'remotes/xtensa/tags/20200625-xtensa' into staging target/xtensa fixes for 5.1: - fix access to special registers missing in the core configuration; - fix simcall opcode behavior for new hardware; - drop gen_io_end call from xtensa translator. # gpg: Signature made Thu 25 Jun 2020 09:08:58 BST # gpg: using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044 # gpg: issuer "jcmvbkbc@gmail.com" # gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown] # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" [full] # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" [full] # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20200625-xtensa: target/xtensa: drop gen_io_end call target/xtensa: fix simcall for newer hardware target/xtensa: fetch HW version from configuration overlay target/xtensa: work around missing SR definitions Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
2cc2278e |
| 04-May-2020 |
Max Filippov <jcmvbkbc@gmail.com> |
target/xtensa: fetch HW version from configuration overlay Xtensa architecture has features which behavior depends on hardware version. Provide hardware version information to translator
target/xtensa: fetch HW version from configuration overlay Xtensa architecture has features which behavior depends on hardware version. Provide hardware version information to translators: add XtensaConfig::hw_version and use XCHAL_HW_VERSION from configuration overlay to initialize it. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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#
b952544f |
| 10-Jan-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging * Compat machines fix (Denis) * Command line parsing fixes (Michal, Peter, Xiaoyao) * Cooperlake CPU mod
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging * Compat machines fix (Denis) * Command line parsing fixes (Michal, Peter, Xiaoyao) * Cooperlake CPU model fixes (Xiaoyao) * i386 gdb fix (mkdolata) * IOEventHandler cleanup (Philippe) * icount fix (Pavel) * RR support for random number sources (Pavel) * Kconfig fixes (Philippe) # gpg: Signature made Wed 08 Jan 2020 10:41:00 GMT # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (38 commits) chardev: Use QEMUChrEvent enum in IOEventHandler typedef chardev: use QEMUChrEvent instead of int chardev/char: Explicit we ignore some QEMUChrEvent in IOEventHandler monitor/hmp: Explicit we ignore a QEMUChrEvent in IOEventHandler monitor/qmp: Explicit we ignore few QEMUChrEvent in IOEventHandler virtio-console: Explicit we ignore some QEMUChrEvent in IOEventHandler vhost-user-blk: Explicit we ignore few QEMUChrEvent in IOEventHandler vhost-user-net: Explicit we ignore few QEMUChrEvent in IOEventHandler vhost-user-crypto: Explicit we ignore some QEMUChrEvent in IOEventHandler ccid-card-passthru: Explicit we ignore QEMUChrEvent in IOEventHandler hw/usb/redirect: Explicit we ignore few QEMUChrEvent in IOEventHandler hw/usb/dev-serial: Explicit we ignore few QEMUChrEvent in IOEventHandler hw/char/terminal3270: Explicit ignored QEMUChrEvent in IOEventHandler hw/ipmi: Explicit we ignore some QEMUChrEvent in IOEventHandler hw/ipmi: Remove unnecessary declarations target/i386: Add missed features to Cooperlake CPU model target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES target/i386: Fix handling of k_gs_base register in 32-bit mode in gdbstub hw/rtc/mc146818: Add missing dependency on ISA Bus hw/nvram/Kconfig: Restrict CHRP NVRAM to machines using OpenBIOS or SLOF ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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973d306d |
| 07-Jan-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging virtio, pci, pc: fixes, features Bugfixes all over the place. HMAT support. New flags for vhost-use
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging virtio, pci, pc: fixes, features Bugfixes all over the place. HMAT support. New flags for vhost-user-blk utility. Auto-tuning of seg max for virtio storage. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Mon 06 Jan 2020 17:05:05 GMT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: (32 commits) intel_iommu: add present bit check for pasid table entries intel_iommu: a fix to vtd_find_as_from_bus_num() virtio-net: delete also control queue when TX/RX deleted virtio: reset region cache when on queue deletion virtio-mmio: update queue size on guest write tests: add virtio-scsi and virtio-blk seg_max_adjust test virtio: make seg_max virtqueue size dependent hw: fix using 4.2 compat in 5.0 machine types for i440fx/q35 vhost-user-scsi: reset the device if supported vhost-user: add VHOST_USER_RESET_DEVICE to reset devices hw/pci/pci_host: Let pci_data_[read/write] use unsigned 'size' argument hw/pci/pci_host: Remove redundant PCI_DPRINTF() virtio-mmio: Clear v2 transport state on soft reset ACPI: add expected files for HMAT tests (acpihmat) tests/bios-tables-test: add test cases for ACPI HMAT tests/numa: Add case for QMP build HMAT hmat acpi: Build Memory Side Cache Information Structure(s) hmat acpi: Build System Locality Latency and Bandwidth Information Structure(s) hmat acpi: Build Memory Proximity Domain Attributes Structure(s) numa: Extend CLI to provide memory side cache information ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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a8f2c60c |
| 07-Jan-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/awilliam/tags/vfio-fixes-20200106.0' into staging VFIO fixes 2020-01-06 - Fix irqchip notifier de-registration if not registered (Peter Xu)
Merge remote-tracking branch 'remotes/awilliam/tags/vfio-fixes-20200106.0' into staging VFIO fixes 2020-01-06 - Fix irqchip notifier de-registration if not registered (Peter Xu) # gpg: Signature made Mon 06 Jan 2020 21:58:17 GMT # gpg: using RSA key 239B9B6E3BB08B22 # gpg: Good signature from "Alex Williamson <alex.williamson@redhat.com>" [full] # gpg: aka "Alex Williamson <alex@shazbot.org>" [full] # gpg: aka "Alex Williamson <alwillia@redhat.com>" [full] # gpg: aka "Alex Williamson <alex.l.williamson@gmail.com>" [full] # Primary key fingerprint: 42F6 C04E 540B D1A9 9E7B 8A90 239B 9B6E 3BB0 8B22 * remotes/awilliam/tags/vfio-fixes-20200106.0: vfio/pci: Don't remove irqchip notifier if not registered Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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cdbc5c51 |
| 07-Jan-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/xtensa/tags/20200106-xtensa' into staging target/xtensa improvements for v5.0: - fix ps.ring use in MPU configs; - use MPU background map f
Merge remote-tracking branch 'remotes/xtensa/tags/20200106-xtensa' into staging target/xtensa improvements for v5.0: - fix ps.ring use in MPU configs; - use MPU background map from the configuration overlay. # gpg: Signature made Mon 06 Jan 2020 20:00:33 GMT # gpg: using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044 # gpg: issuer "jcmvbkbc@gmail.com" # gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown] # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" [full] # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" [full] # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20200106-xtensa: target/xtensa: use MPU background map from core configuration target/xtensa: import xtensa/config/core-isa.h target/xtensa: fix ps.ring use in MPU configs Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v4.2.0 |
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#
a153a3f7 |
| 08-Dec-2019 |
Max Filippov <jcmvbkbc@gmail.com> |
target/xtensa: use MPU background map from core configuration Configuration overlay may define MPU background map. Import core-matmap.h from the overlay and use XCHAL_MPU_BACKGROUND_MAP
target/xtensa: use MPU background map from core configuration Configuration overlay may define MPU background map. Import core-matmap.h from the overlay and use XCHAL_MPU_BACKGROUND_MAP macro if it's defined. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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a4f667b6 |
| 21-May-2019 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190521-3' into staging s390x update: - have the bios tolerate bootmap signature entries - next chunk of vector instruction s
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190521-3' into staging s390x update: - have the bios tolerate bootmap signature entries - next chunk of vector instruction support in tcg - a headers update against Linux 5.2-rc1 - add more facilities and gen15 machines to the cpu model # gpg: Signature made Tue 21 May 2019 16:09:35 BST # gpg: using RSA key C3D0D66DC3624FF6A8C018CEDECF6B93C6F02FAF # gpg: issuer "cohuck@redhat.com" # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" [unknown] # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" [full] # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" [full] # gpg: aka "Cornelia Huck <cohuck@kernel.org>" [unknown] # gpg: aka "Cornelia Huck <cohuck@redhat.com>" [unknown] # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20190521-3: (55 commits) s390x/cpumodel: wire up 8561 and 8562 as gen15 machines s390x/cpumodel: add gen15 defintions s390x/cpumodel: add Deflate-conversion facility s390x/cpumodel: enhanced sort facility s390x/cpumodel: vector enhancements s390x/cpumodel: msa9 facility s390x/cpumodel: Miscellaneous-Instruction-Extensions Facility 3 s390x/cpumodel: ignore csske for expansion linux headers: update against Linux 5.2-rc1 update-linux-headers: handle new header file s390x/tcg: Implement VECTOR TEST UNDER MASK s390x/tcg: Implement VECTOR SUM ACROSS WORD s390x/tcg: Implement VECTOR SUM ACROSS QUADWORD s390x/tcg: Implement VECTOR SUM ACROSS DOUBLEWORD s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW INDICATION s390x/tcg: Implement VECTOR SUBTRACT COMPUTE BORROW INDICATION s390x/tcg: Implement VECTOR SUBTRACT s390x/tcg: Implement VECTOR SHIFT RIGHT LOGICAL * s390x/tcg: Implement VECTOR SHIFT RIGHT ARITHMETIC ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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247ba27c |
| 21-May-2019 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging pci, pc, virtio: features, fixes reconnect for vhost blk tests for UEFI misc other stuff S
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging pci, pc, virtio: features, fixes reconnect for vhost blk tests for UEFI misc other stuff Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Tue 21 May 2019 14:41:32 BST # gpg: using RSA key 281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: (34 commits) tests: acpi: print error unable to dump ACPI table during rebuild tests: acpi: refactor rebuild-expected-aml.sh to dump ACPI tables for a specified list of targets tests: acpi: allow to override default accelerator tests: acpi: ignore SMBIOS tests when UEFI firmware is used tests: acpi: add a way to start tests with UEFI firmware tests: acpi: add acpi_find_rsdp_address_uefi() helper tests: acpi: move boot_sector_init() into x86 tests branch tests: acpi: skip FACS table if board uses hw reduced ACPI profile tests: acpi: fetch X_DSDT if pointer to DSDT is 0 tests: acpi: make pointer to RSDP 64bit tests: acpi: make RSDT test routine handle XSDT tests: acpi: make acpi_fetch_table() take size of fetched table pointer tests: acpi: rename acpi_parse_rsdp_table() into acpi_fetch_rsdp_table() pci: Simplify pci_bus_is_root() pcie: Remove redundant test in pcie_mmcfg_data_{read,write}() libvhost-user: fix bad vu_log_write hw/arm/virt-acpi-build: pass AcpiMcfgInfo to build_mcfg() i386, acpi: remove mcfg_ prefix in AcpiMcfgInfo members hw/arm/virt-acpi-build: remove unnecessary variable mcfg_start do not call vhost_net_cleanup() on running net from char user event ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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62516a0a |
| 21-May-2019 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2019-05-21' into staging - qtest patches to get rid of the global_qtest variable in more tests - some iotests patches
Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2019-05-21' into staging - qtest patches to get rid of the global_qtest variable in more tests - some iotests patches that have multiple reviews and thus are ready to go # gpg: Signature made Tue 21 May 2019 11:40:31 BST # gpg: using RSA key 2ED9D774FE702DB5 # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * remotes/huth-gitlab/tags/pull-request-2019-05-21: tests/qemu-iotests: Remove the "_supported_os Linux" line from many tests cirrus / travis: Add gnu-sed and bash for macOS and FreeBSD tests/qemu-iotests: Do not hard-code the path to bash tests/qemu-iotests/check: Pick a default machine if necessary tests/qemu-iotests/005: Add a sanity check for large sparse file support tests/hd-geo-test: Use qtest_init() instead of qtest_start() tests/device-introspect: Use qtest_init() instead of qtest_start() tests/qom-test: Use qtest_init() instead of qtest_start() tests/numa-test: Use qtest_init() instead of qtest_start() tests/q35-test: Make test independent of global_qtest tests/libqos: Get rid of global_qtest dependency in qvring_init() tests/libqtest: Fix description of qtest_vinitf() and qtest_initf() tests/libqtest: Remove unused global_qtest-related wrapper functions Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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293c76cb |
| 21-May-2019 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/xtensa/tags/20190520-xtensa' into staging target/xtensa: SR reorganization and options for modern cores Reorganize special register handling to
Merge remote-tracking branch 'remotes/xtensa/tags/20190520-xtensa' into staging target/xtensa: SR reorganization and options for modern cores Reorganize special register handling to support configurations with conflicting SR definitions. Implement options used by the modern xtensa cores: - memory protection unit; - block prefetch; - exclusive access Add special register definitions and IRQ types for ECC/parity, gather/scatter and IDMA. # gpg: Signature made Mon 20 May 2019 18:53:05 BST # gpg: using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044 # gpg: issuer "jcmvbkbc@gmail.com" # gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown] # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" [full] # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" [full] # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20190520-xtensa: target/xtensa: implement exclusive access option target/xtensa: update list of exception causes target/xtensa: implement block prefetch option opcodes target/xtensa: implement DIWBUI.P opcode target/xtensa: implement MPU option target/xtensa: add parity/ECC option SRs target/xtensa: define IDMA and gather/scatter IRQ types target/xtensa: make internal MMU functions static target/xtensa: get rid of centralized SR properties Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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b345e140 |
| 18-Apr-2019 |
Max Filippov <jcmvbkbc@gmail.com> |
target/xtensa: implement exclusive access option The Exclusive Instructions provide a general-purpose mechanism for atomic updates of memory-based synchronization variables that can be
target/xtensa: implement exclusive access option The Exclusive Instructions provide a general-purpose mechanism for atomic updates of memory-based synchronization variables that can be used for exclusion algorithms. Use cmpxchg-based implementation that is sufficient for the typical use of exclusive access in atomic operations. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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75eed0e5 |
| 14-Apr-2019 |
Max Filippov <jcmvbkbc@gmail.com> |
target/xtensa: implement DIWBUI.P opcode This is a recent addition to the set of data cache opcodes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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Revision tags: v4.0.0-rc1, v4.0.0-rc0 |
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4d04ea35 |
| 13-Mar-2019 |
Max Filippov <jcmvbkbc@gmail.com> |
target/xtensa: implement MPU option The Memory Protection Unit Option (MPU) is a combined instruction and data memory protection unit with more protection flexibility than the Region
target/xtensa: implement MPU option The Memory Protection Unit Option (MPU) is a combined instruction and data memory protection unit with more protection flexibility than the Region Protection Option or the Region Translation Option but without any translation capability. It does no demand paging and does not reference a memory-based page table. Add memory protection unit option, internal state, SRs and opcodes. Implement MPU entries dumping in dump_mmu. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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