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/openbmc/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
25 # Polarity negative negative
28 mode "640x480-60"
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
50 # Polarity negative negative
52 mode "640x480-75"
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
71 # Polarity negative negative
73 mode "640x480-85"
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H A Dpxafb.rst10 modprobe pxafb options=vmem:2M,mode:640x480-8,passive
14 video=pxafb:vmem:2M,mode:640x480-8,passive
21 mode:XRESxYRES[-BPP]
45 vsynclen:VSYNC == LCCR2_VSW + 1
65 hsync:HSYNC, vsync:VSYNC
68 high.
74 outputen:POLARITY
76 Output Enable Polarity. 0 => active low, 1 => active high
78 pixclockpol:POLARITY
80 pixel clock polarity
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H A Dmatroxfb.rst16 * Most important: boot logo :-)
34 box) and matroxfb (for graphics mode). You should not compile-in vesafb
35 unless you have primary display on non-Matrox VBE2.0 device (see
43 -------------
58 -------------------------
73 ----------
86 Non-listed number can be achieved by more complicated command-line, for
93 XF{68,86}_FBDev should work just fine, but it is non-accelerated. On non-intel
97 Running another (accelerated) X-Server like XF86_SVGA works too. But (at least)
100 driver is possible, but you must not enable DRI - if you do, resolution and
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/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Drichtek,rtmv20-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rtmv20-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
16 There're still four pins for camera control, two inputs (strobe and vsync),
18 supply, vsync input from IR camera, and fsin1/fsin2 output for the optional.
27 wakeup-source: true
32 enable-gpios:
36 richtek,ld-pulse-delay-us:
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/openbmc/linux/include/media/i2c/
H A Dtvp7002.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics
6 * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>
19 * struct tvp7002_config - Platform dependent data
20 *@clk_polarity: Clock polarity
21 * 0 - Data clocked out on rising edge of DATACLK signal
22 * 1 - Data clocked out on falling edge of DATACLK signal
23 *@hs_polarity: HSYNC polarity
24 * 0 - Active low HSYNC output, 1 - Active high HSYNC output
25 *@vs_polarity: VSYNC Polarity
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/openbmc/linux/arch/sh/include/asm/
H A Dsh7760fb.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sh7760fb.h -- platform data for SH7760/SH7763 LCDC framebuffer driver.
5 * (c) 2006-2008 MSC Vertriebsges.m.b.H.,
19 /* The LCDC dma engine always sets bits 27-26 to 1: this is Area3 */
75 /* HSYNC polarity inversion */
78 /* VSYNC polarity inversion */
81 /* DISPLAY-ENABLE polarity inversion */
84 /* DISPLAY DATA BUS polarity inversion */
90 /* Disable output of HSYNC during VSYNC period */
93 /* Disable output of VSYNC during VSYNC period */
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/openbmc/linux/Documentation/devicetree/bindings/media/i2c/
H A Dtvp7002.txt7 - compatible : Must be "ti,tvp7002"
10 - hsync-active: HSYNC Polarity configuration for the bus. Default value when
13 - vsync-active: VSYNC Polarity configuration for the bus. Default value when
16 - pclk-sample: Clock polarity of the bus. Default value when this property is
19 - sync-on-green-active: Active state of Sync-on-green signal property of the
24 - field-even-active: Active-high Field ID output polarity control of the bus.
28 1 = FID output polarity inverted
31 video-interfaces.txt.
44 hsync-active = <1>;
45 vsync-active = <1>;
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H A Dtvp514x.txt3 The TVP5146/TVP5146m2/TVP5147/TVP5147m1 device is high quality, single-chip
5 video formats into digital video component. The tvp514x decoder supports analog-
6 to-digital (A/D) conversion of component RGB and YPbPr signals as well as A/D
7 conversion and decoding of NTSC, PAL and SECAM composite and S-video into
11 - compatible : value should be either one among the following
17 - hsync-active: HSYNC Polarity configuration for endpoint.
19 - vsync-active: VSYNC Polarity configuration for endpoint.
21 - pclk-sample: Clock polarity of the endpoint.
24 media/video-interfaces.txt.
37 hsync-active = <1>;
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H A Dtda1997x.txt1 Device-Tree bindings for the NXP TDA1997x HDMI receiver
6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
8 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
9 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
16 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
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/openbmc/linux/Documentation/devicetree/bindings/display/exynos/
H A Dexynos_dp.txt5 -dp-controller node
6 -dptx-phy node(defined inside dp-controller node)
8 For the DP-PHY initialization, we use the dptx-phy node.
9 Required properties for dptx-phy: deprecated, use phys and phy-names
10 -reg: deprecated
12 -samsung,enable-mask: deprecated
13 The bit-mask used to enable/disable DP PHY.
15 For the Panel initialization, we read data from dp-controller node.
16 Required properties for dp-controller:
17 -compatible:
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/openbmc/u-boot/drivers/video/
H A Dam335x-fb.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2013-2018 Hannes Schmelzer <oe5hpm@oevsv.at> -
4 * B&R Industrial Automation GmbH - http://www.br-automation.com
29 * 0 = DE is low-active
30 * 1 = DE is high-active
33 * 0 = pix-clk is high-active
34 * 1 = pic-clk is low-active
37 * 0 = HSYNC is active high
41 * 0 = VSYNC is active high
42 * 1 = VSYNC is active low
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/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dvideo-interfaces.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/video-interfaces.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sakari Ailus <sakari.ailus@linux.intel.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
29 #address-cells = <1>;
30 #size-cells = <0>;
45 a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
49 specify #address-cells, #size-cells properties independently for the 'port'
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/openbmc/u-boot/board/freescale/common/
H A Ddiu_ch7301.c1 // SPDX-License-Identifier: GPL-2.0+
26 * Set VSYNC/HSYNC to active high. This is polarity of sync signals
27 * from DIU->DVI. The DIU default is active igh, so DVI is set to
28 * active high.
41 /* Exit Power-down mode */
44 /* Monitor polarity is handled via DVI Sync Polarity Register */
68 /* Set Sync polarity register */ in diu_set_dvi_encoder()
73 puts("I2C: failed to select dvi syc polarity\n"); in diu_set_dvi_encoder()
/openbmc/u-boot/drivers/video/stm32/
H A Dstm32_ltdc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017-2018 STMicroelectronics - All Rights Reserved
16 #include <dm/device-internal.h>
85 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */
86 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */
87 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */
88 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */
101 #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */
102 #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */
109 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */
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/openbmc/linux/include/media/
H A Dv4l2-mediabus.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <linux/v4l2-mediabus.h>
46 * Signal polarity flags
47 * Note: in BT.656 mode HSYNC, FIELD, and VSYNC are unused
60 /* FIELD = 0/1 - Field1 (odd)/Field2 (even) */
62 /* FIELD = 1/0 - Field1 (odd)/Field2 (even) */
64 /* Active state of Sync-on-green (SoG) signal, 0/1 for LOW/HIGH respectively. */
71 /* Clock non-continuous mode support. */
77 * struct v4l2_mbus_config_mipi_csi2 - MIPI CSI-2 data bus configuration
82 * @lane_polarities: polarity of the lanes. The order is the same of
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/openbmc/linux/drivers/gpu/drm/bridge/adv7511/
H A Dadv7511.h1 /* SPDX-License-Identifier: GPL-2.0-only */
62 #define ADV7511_REG_GC(x) (0x4b + (x)) /* 0x4b - 0x51 */
66 #define ADV7511_REG_AVI_INFOFRAME(x) (0x55 + (x)) /* 0x55 - 0x6f */
70 #define ADV7511_REG_AUDIO_INFOFRAME(x) (0x73 + (x)) /* 0x73 - 0x7c */
77 #define ADV7511_REG_AN(x) (0xb0 + (x)) /* 0xb0 - 0xb7 */
80 #define ADV7511_REG_BKSV(x) (0xc0 + (x)) /* 0xc0 - 0xc3 */
84 #define ADV7511_REG_BSTATUS(x) (0xca + (x)) /* 0xca - 0xcb */
89 #define ADV7511_REG_SYNC_ADJUSTMENT(x) (0xd7 + (x)) /* 0xd7 - 0xdc */
251 * enum adv7511_sync_polarity - Polarity for the input sync signals
252 * @ADV7511_SYNC_POLARITY_PASSTHROUGH: Sync polarity matches that of
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/openbmc/linux/drivers/gpu/drm/panel/
H A Dpanel-ilitek-ili9322.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * - 8-bit serial RGB interface
7 * - 24-bit parallel RGB interface
8 * - 8-bit ITU-R BT.601 interface
9 * - 8-bit ITU-R BT.656 interface
10 * - Up to 320RGBx240 dots resolution TFT LCD displays
11 * - Scaling, brightness and contrast
19 * Derived from drivers/drm/gpu/panel/panel-samsung-ld9040.c
49 * High voltage on the communication signals, from 0.37 (0x00) to
64 /* 0 = right-to-left, 1 = left-to-right (default), horizontal flip */
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_hw_types.h41 * Note: do *not* add any types which are *not* used for HW programming - this
241 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such
363 * 0x0 - DISPLAY_MICRO_TILING
364 * 0x1 - THIN_MICRO_TILING
365 * 0x2 - DEPTH_MICRO_TILING
366 * 0x3 - ROTATED_MICRO_TILING
523 * enum dc_cursor_color_format - DC cursor programming mode
563 * divided into a high and low parts.
744 it is positive polarity --reversed with dal1 or video bios define*/
746 it is positive polarity --reversed with dal1 or video bios define*/
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/openbmc/linux/drivers/media/i2c/adv748x/
H A Dadv748x-hdmi.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <media/v4l2-ctrls.h>
12 #include <media/v4l2-device.h>
13 #include <media/v4l2-dv-timings.h>
14 #include <media/v4l2-ioctl.h>
16 #include <uapi/linux/v4l2-dv-timings.h>
20 /* -----------------------------------------------------------------------------
29 /* V4L2_DV_BT_CEA_720X480I59_94 - 0.5 MHz */
95 fmt->code = MEDIA_BUS_FMT_RGB888_1X24; in adv748x_hdmi_fill_format()
96 fmt->field = hdmi->timings.bt.interlaced ? in adv748x_hdmi_fill_format()
[all …]
/openbmc/linux/drivers/media/i2c/
H A Dtda1997x.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/v4l2-dv-timings.h>
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-device.h>
21 #include <media/v4l2-dv-timings.h>
22 #include <media/v4l2-event.h>
23 #include <media/v4l2-fwnode.h>
31 #include <dt-bindings/media/tda1997x.h>
40 MODULE_PARM_DESC(debug, "debug level (0-2)");
45 "HBR", /* High Bit Rate Audio */
[all …]
H A Dtw9910.c1 // SPDX-License-Identifier: GPL-2.0
13 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
26 #include <linux/v4l2-mediabus.h>
30 #include <media/v4l2-subdev.h>
45 #define CROP_HI 0x07 /* Cropping Register, High */
52 #define SCALE_HI 0x0E /* Scaling Register, High */
136 #define IFSEL_S 0x10 /* 01 : S-video decoding */
146 /* 1 : ITU-R-656 compatible data sequence format */
147 #define LEN 0x40 /* 0 : 8-bit YCrCb 4:2:2 output format */
148 /* 1 : 16-bit YCrCb 4:2:2 output format.*/
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/openbmc/linux/drivers/regulator/
H A Drtmv20-regulator.c1 // SPDX-License-Identifier: GPL-2.0+
75 gpiod_set_value(priv->enable_gpio, 1); in rtmv20_lsw_enable()
80 /* HW re-enable, disable cache only and sync regcache here */ in rtmv20_lsw_enable()
81 regcache_cache_only(priv->regmap, false); in rtmv20_lsw_enable()
82 ret = regcache_sync(priv->regmap); in rtmv20_lsw_enable()
99 regcache_cache_only(priv->regmap, true); in rtmv20_lsw_disable()
100 regcache_mark_dirty(priv->regmap); in rtmv20_lsw_disable()
102 gpiod_set_value(priv->enable_gpio, 0); in rtmv20_lsw_disable()
113 return -EINVAL; in rtmv20_lsw_set_current_limit()
118 sel = (max_uA - RTMV20_LSW_MINUA) / RTMV20_LSW_STEPUA; in rtmv20_lsw_set_current_limit()
[all …]
/openbmc/linux/drivers/gpu/drm/meson/
H A Dmeson_venc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
25 * - CVBS Encoding via the ENCI encoder and VDAC digital to analog converter
26 * - TMDS/HDMI Encoding via ENCI_DIV and ENCP
27 * - Setup of more clock rates for HDMI modes
31 * - LCD Panel encoding via ENCL
32 * - TV Panel encoding via ENCT
39 * vd1---| |-| | | VENC /---------|----VDAC
40 * vd2---| VIU |-| VPP |-|-----ENCI/-ENCI_DVI-|-|
41 * osd1--| |-| | | \ | X--HDMI-TX
42 * osd2--|_____|-|_____| | |\-ENCP--ENCP_DVI-|-|
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/openbmc/linux/drivers/gpu/drm/
H A Ddrm_modes.c2 * Copyright © 1997-2003 by The XFree86 Project, Inc.
4 * Copyright © 2007-2008 Intel Corporation
6 * Copyright 2005-2006 Luc Verhaegen
53 * drm_mode_debug_printmodeline - print a mode to dmesg
65 * drm_mode_create - create a new display mode
87 * drm_mode_destroy - remove a mode
103 * drm_mode_probed_add - add a mode to a connector's probed_mode list
114 WARN_ON(!mutex_is_locked(&connector->dev->mode_config.mutex)); in drm_mode_probed_add()
116 list_add_tail(&mode->head, &connector->probed_modes); in drm_mode_probed_add()
127 * - https://web.archive.org/web/20220406232708/http://www.kolumbus.fi/pami1/video/pal_ntsc.html
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/openbmc/linux/drivers/media/platform/xilinx/
H A Dxilinx-vtc.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2015 Ideas on Board
6 * Copyright (C) 2013-2015 Xilinx, Inc.
18 #include "xilinx-vip.h"
19 #include "xilinx-vtc.h"
145 * struct xvtc_device - Xilinx Video Timing Controller device structure
167 xvip_write(&xvtc->xvip, XVTC_GENERATOR_OFFSET + addr, value); in xvtc_gen_write()
170 /* -----------------------------------------------------------------------------
179 if (!xvtc->has_generator) in xvtc_generator_start()
180 return -ENXIO; in xvtc_generator_start()
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