1c0d9644fSLad, Prabhakar* Texas Instruments TV7002 video decoder
2c0d9644fSLad, Prabhakar
3c0d9644fSLad, PrabhakarThe TVP7002 device supports digitizing of video and graphics signal in RGB and
4c0d9644fSLad, PrabhakarYPbPr color space.
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6c0d9644fSLad, PrabhakarRequired Properties :
7c0d9644fSLad, Prabhakar- compatible : Must be "ti,tvp7002"
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9c0d9644fSLad, PrabhakarOptional Properties:
10c0d9644fSLad, Prabhakar- hsync-active: HSYNC Polarity configuration for the bus. Default value when
11c0d9644fSLad, Prabhakar  this property is not specified is <0>.
12c0d9644fSLad, Prabhakar
13c0d9644fSLad, Prabhakar- vsync-active: VSYNC Polarity configuration for the bus. Default value when
14c0d9644fSLad, Prabhakar  this property is not specified is <0>.
15c0d9644fSLad, Prabhakar
16c0d9644fSLad, Prabhakar- pclk-sample: Clock polarity of the bus. Default value when this property is
17c0d9644fSLad, Prabhakar  not specified is <0>.
18c0d9644fSLad, Prabhakar
19c0d9644fSLad, Prabhakar- sync-on-green-active: Active state of Sync-on-green signal property of the
20c0d9644fSLad, Prabhakar  endpoint.
21c0d9644fSLad, Prabhakar  0 = Normal Operation (Active Low, Default)
22c0d9644fSLad, Prabhakar  1 = Inverted operation
23c0d9644fSLad, Prabhakar
24c0d9644fSLad, Prabhakar- field-even-active: Active-high Field ID output polarity control of the bus.
25c0d9644fSLad, Prabhakar  Under normal operation, the field ID output is set to logic 1 for an odd field
26c0d9644fSLad, Prabhakar  (field 1) and set to logic 0 for an even field (field 0).
27c0d9644fSLad, Prabhakar  0 = Normal Operation (Active Low, Default)
28c0d9644fSLad, Prabhakar  1 = FID output polarity inverted
29c0d9644fSLad, Prabhakar
30c0d9644fSLad, PrabhakarFor further reading of port node refer Documentation/devicetree/bindings/media/
31c0d9644fSLad, Prabhakarvideo-interfaces.txt.
32c0d9644fSLad, Prabhakar
33c0d9644fSLad, PrabhakarExample:
34c0d9644fSLad, Prabhakar
35c0d9644fSLad, Prabhakar	i2c0@1c22000 {
36c0d9644fSLad, Prabhakar		...
37c0d9644fSLad, Prabhakar		...
38c0d9644fSLad, Prabhakar		tvp7002@5c {
39c0d9644fSLad, Prabhakar			compatible = "ti,tvp7002";
40c0d9644fSLad, Prabhakar			reg = <0x5c>;
41c0d9644fSLad, Prabhakar
42c0d9644fSLad, Prabhakar			port {
43c0d9644fSLad, Prabhakar				tvp7002_1: endpoint {
44c0d9644fSLad, Prabhakar					hsync-active = <1>;
45c0d9644fSLad, Prabhakar					vsync-active = <1>;
46c0d9644fSLad, Prabhakar					pclk-sample = <0>;
47c0d9644fSLad, Prabhakar					sync-on-green-active = <1>;
48c0d9644fSLad, Prabhakar					field-even-active = <0>;
49c0d9644fSLad, Prabhakar				};
50c0d9644fSLad, Prabhakar			};
51c0d9644fSLad, Prabhakar		};
52c0d9644fSLad, Prabhakar		...
53c0d9644fSLad, Prabhakar	};
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