1fda8d26eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
2c5827789SArchit Taneja /*
3c5827789SArchit Taneja * Analog Devices ADV7511 HDMI transmitter driver
4c5827789SArchit Taneja *
5c5827789SArchit Taneja * Copyright 2012 Analog Devices Inc.
6c5827789SArchit Taneja */
7c5827789SArchit Taneja
8c5827789SArchit Taneja #ifndef __DRM_I2C_ADV7511_H__
9c5827789SArchit Taneja #define __DRM_I2C_ADV7511_H__
10c5827789SArchit Taneja
11c5827789SArchit Taneja #include <linux/hdmi.h>
122437e7cdSArchit Taneja #include <linux/i2c.h>
132437e7cdSArchit Taneja #include <linux/regmap.h>
145b06ba23SArchit Taneja #include <linux/regulator/consumer.h>
152437e7cdSArchit Taneja
16fcd70cd3SDaniel Vetter #include <drm/drm_bridge.h>
17fcd70cd3SDaniel Vetter #include <drm/drm_connector.h>
181e4d58cdSArchit Taneja #include <drm/drm_mipi_dsi.h>
19fcd70cd3SDaniel Vetter #include <drm/drm_modes.h>
20c5827789SArchit Taneja
21c5827789SArchit Taneja #define ADV7511_REG_CHIP_REVISION 0x00
22c5827789SArchit Taneja #define ADV7511_REG_N0 0x01
23c5827789SArchit Taneja #define ADV7511_REG_N1 0x02
24c5827789SArchit Taneja #define ADV7511_REG_N2 0x03
25c5827789SArchit Taneja #define ADV7511_REG_SPDIF_FREQ 0x04
26c5827789SArchit Taneja #define ADV7511_REG_CTS_AUTOMATIC1 0x05
27c5827789SArchit Taneja #define ADV7511_REG_CTS_AUTOMATIC2 0x06
28c5827789SArchit Taneja #define ADV7511_REG_CTS_MANUAL0 0x07
29c5827789SArchit Taneja #define ADV7511_REG_CTS_MANUAL1 0x08
30c5827789SArchit Taneja #define ADV7511_REG_CTS_MANUAL2 0x09
31c5827789SArchit Taneja #define ADV7511_REG_AUDIO_SOURCE 0x0a
32c5827789SArchit Taneja #define ADV7511_REG_AUDIO_CONFIG 0x0b
33c5827789SArchit Taneja #define ADV7511_REG_I2S_CONFIG 0x0c
34c5827789SArchit Taneja #define ADV7511_REG_I2S_WIDTH 0x0d
35c5827789SArchit Taneja #define ADV7511_REG_AUDIO_SUB_SRC0 0x0e
36c5827789SArchit Taneja #define ADV7511_REG_AUDIO_SUB_SRC1 0x0f
37c5827789SArchit Taneja #define ADV7511_REG_AUDIO_SUB_SRC2 0x10
38c5827789SArchit Taneja #define ADV7511_REG_AUDIO_SUB_SRC3 0x11
39c5827789SArchit Taneja #define ADV7511_REG_AUDIO_CFG1 0x12
40c5827789SArchit Taneja #define ADV7511_REG_AUDIO_CFG2 0x13
41c5827789SArchit Taneja #define ADV7511_REG_AUDIO_CFG3 0x14
42c5827789SArchit Taneja #define ADV7511_REG_I2C_FREQ_ID_CFG 0x15
43c5827789SArchit Taneja #define ADV7511_REG_VIDEO_INPUT_CFG1 0x16
44c5827789SArchit Taneja #define ADV7511_REG_CSC_UPPER(x) (0x18 + (x) * 2)
45c5827789SArchit Taneja #define ADV7511_REG_CSC_LOWER(x) (0x19 + (x) * 2)
46c5827789SArchit Taneja #define ADV7511_REG_SYNC_DECODER(x) (0x30 + (x))
47c5827789SArchit Taneja #define ADV7511_REG_DE_GENERATOR (0x35 + (x))
48c5827789SArchit Taneja #define ADV7511_REG_PIXEL_REPETITION 0x3b
49c5827789SArchit Taneja #define ADV7511_REG_VIC_MANUAL 0x3c
50c5827789SArchit Taneja #define ADV7511_REG_VIC_SEND 0x3d
51c5827789SArchit Taneja #define ADV7511_REG_VIC_DETECTED 0x3e
52c5827789SArchit Taneja #define ADV7511_REG_AUX_VIC_DETECTED 0x3f
53c5827789SArchit Taneja #define ADV7511_REG_PACKET_ENABLE0 0x40
54c5827789SArchit Taneja #define ADV7511_REG_POWER 0x41
55c5827789SArchit Taneja #define ADV7511_REG_STATUS 0x42
56c5827789SArchit Taneja #define ADV7511_REG_EDID_I2C_ADDR 0x43
57c5827789SArchit Taneja #define ADV7511_REG_PACKET_ENABLE1 0x44
58c5827789SArchit Taneja #define ADV7511_REG_PACKET_I2C_ADDR 0x45
59c5827789SArchit Taneja #define ADV7511_REG_DSD_ENABLE 0x46
60c5827789SArchit Taneja #define ADV7511_REG_VIDEO_INPUT_CFG2 0x48
61c5827789SArchit Taneja #define ADV7511_REG_INFOFRAME_UPDATE 0x4a
62c5827789SArchit Taneja #define ADV7511_REG_GC(x) (0x4b + (x)) /* 0x4b - 0x51 */
63c5827789SArchit Taneja #define ADV7511_REG_AVI_INFOFRAME_VERSION 0x52
64c5827789SArchit Taneja #define ADV7511_REG_AVI_INFOFRAME_LENGTH 0x53
65c5827789SArchit Taneja #define ADV7511_REG_AVI_INFOFRAME_CHECKSUM 0x54
66c5827789SArchit Taneja #define ADV7511_REG_AVI_INFOFRAME(x) (0x55 + (x)) /* 0x55 - 0x6f */
67c5827789SArchit Taneja #define ADV7511_REG_AUDIO_INFOFRAME_VERSION 0x70
68c5827789SArchit Taneja #define ADV7511_REG_AUDIO_INFOFRAME_LENGTH 0x71
69c5827789SArchit Taneja #define ADV7511_REG_AUDIO_INFOFRAME_CHECKSUM 0x72
70c5827789SArchit Taneja #define ADV7511_REG_AUDIO_INFOFRAME(x) (0x73 + (x)) /* 0x73 - 0x7c */
71c5827789SArchit Taneja #define ADV7511_REG_INT_ENABLE(x) (0x94 + (x))
72c5827789SArchit Taneja #define ADV7511_REG_INT(x) (0x96 + (x))
73c5827789SArchit Taneja #define ADV7511_REG_INPUT_CLK_DIV 0x9d
74c5827789SArchit Taneja #define ADV7511_REG_PLL_STATUS 0x9e
75c5827789SArchit Taneja #define ADV7511_REG_HDMI_POWER 0xa1
76c5827789SArchit Taneja #define ADV7511_REG_HDCP_HDMI_CFG 0xaf
77c5827789SArchit Taneja #define ADV7511_REG_AN(x) (0xb0 + (x)) /* 0xb0 - 0xb7 */
78c5827789SArchit Taneja #define ADV7511_REG_HDCP_STATUS 0xb8
79c5827789SArchit Taneja #define ADV7511_REG_BCAPS 0xbe
80c5827789SArchit Taneja #define ADV7511_REG_BKSV(x) (0xc0 + (x)) /* 0xc0 - 0xc3 */
81c5827789SArchit Taneja #define ADV7511_REG_EDID_SEGMENT 0xc4
82c5827789SArchit Taneja #define ADV7511_REG_DDC_STATUS 0xc8
83c5827789SArchit Taneja #define ADV7511_REG_EDID_READ_CTRL 0xc9
84c5827789SArchit Taneja #define ADV7511_REG_BSTATUS(x) (0xca + (x)) /* 0xca - 0xcb */
85c5827789SArchit Taneja #define ADV7511_REG_TIMING_GEN_SEQ 0xd0
86c5827789SArchit Taneja #define ADV7511_REG_POWER2 0xd6
87c5827789SArchit Taneja #define ADV7511_REG_HSYNC_PLACEMENT_MSB 0xfa
88c5827789SArchit Taneja
89c5827789SArchit Taneja #define ADV7511_REG_SYNC_ADJUSTMENT(x) (0xd7 + (x)) /* 0xd7 - 0xdc */
90c5827789SArchit Taneja #define ADV7511_REG_TMDS_CLOCK_INV 0xde
91c5827789SArchit Taneja #define ADV7511_REG_ARC_CTRL 0xdf
92c5827789SArchit Taneja #define ADV7511_REG_CEC_I2C_ADDR 0xe1
93c5827789SArchit Taneja #define ADV7511_REG_CEC_CTRL 0xe2
94c5827789SArchit Taneja #define ADV7511_REG_CHIP_ID_HIGH 0xf5
95c5827789SArchit Taneja #define ADV7511_REG_CHIP_ID_LOW 0xf6
96c5827789SArchit Taneja
97680532c5SKieran Bingham /* Hardware defined default addresses for I2C register maps */
98680532c5SKieran Bingham #define ADV7511_CEC_I2C_ADDR_DEFAULT 0x3c
99680532c5SKieran Bingham #define ADV7511_EDID_I2C_ADDR_DEFAULT 0x3f
100680532c5SKieran Bingham #define ADV7511_PACKET_I2C_ADDR_DEFAULT 0x38
101680532c5SKieran Bingham
102c5827789SArchit Taneja #define ADV7511_CSC_ENABLE BIT(7)
103c5827789SArchit Taneja #define ADV7511_CSC_UPDATE_MODE BIT(5)
104c5827789SArchit Taneja
105c5827789SArchit Taneja #define ADV7511_INT0_HPD BIT(7)
106c5827789SArchit Taneja #define ADV7511_INT0_VSYNC BIT(5)
107c5827789SArchit Taneja #define ADV7511_INT0_AUDIO_FIFO_FULL BIT(4)
108c5827789SArchit Taneja #define ADV7511_INT0_EDID_READY BIT(2)
109c5827789SArchit Taneja #define ADV7511_INT0_HDCP_AUTHENTICATED BIT(1)
110c5827789SArchit Taneja
111c5827789SArchit Taneja #define ADV7511_INT1_DDC_ERROR BIT(7)
112c5827789SArchit Taneja #define ADV7511_INT1_BKSV BIT(6)
113c5827789SArchit Taneja #define ADV7511_INT1_CEC_TX_READY BIT(5)
114c5827789SArchit Taneja #define ADV7511_INT1_CEC_TX_ARBIT_LOST BIT(4)
115c5827789SArchit Taneja #define ADV7511_INT1_CEC_TX_RETRY_TIMEOUT BIT(3)
116c5827789SArchit Taneja #define ADV7511_INT1_CEC_RX_READY3 BIT(2)
117c5827789SArchit Taneja #define ADV7511_INT1_CEC_RX_READY2 BIT(1)
118c5827789SArchit Taneja #define ADV7511_INT1_CEC_RX_READY1 BIT(0)
119c5827789SArchit Taneja
120c5827789SArchit Taneja #define ADV7511_ARC_CTRL_POWER_DOWN BIT(0)
121c5827789SArchit Taneja
122c5827789SArchit Taneja #define ADV7511_CEC_CTRL_POWER_DOWN BIT(0)
123c5827789SArchit Taneja
124c5827789SArchit Taneja #define ADV7511_POWER_POWER_DOWN BIT(6)
125c5827789SArchit Taneja
126c5827789SArchit Taneja #define ADV7511_HDMI_CFG_MODE_MASK 0x2
127c5827789SArchit Taneja #define ADV7511_HDMI_CFG_MODE_DVI 0x0
128c5827789SArchit Taneja #define ADV7511_HDMI_CFG_MODE_HDMI 0x2
129c5827789SArchit Taneja
130c5827789SArchit Taneja #define ADV7511_AUDIO_SELECT_I2C 0x0
131c5827789SArchit Taneja #define ADV7511_AUDIO_SELECT_SPDIF 0x1
132c5827789SArchit Taneja #define ADV7511_AUDIO_SELECT_DSD 0x2
133c5827789SArchit Taneja #define ADV7511_AUDIO_SELECT_HBR 0x3
134c5827789SArchit Taneja #define ADV7511_AUDIO_SELECT_DST 0x4
135c5827789SArchit Taneja
136c5827789SArchit Taneja #define ADV7511_I2S_SAMPLE_LEN_16 0x2
137c5827789SArchit Taneja #define ADV7511_I2S_SAMPLE_LEN_20 0x3
138c5827789SArchit Taneja #define ADV7511_I2S_SAMPLE_LEN_18 0x4
139c5827789SArchit Taneja #define ADV7511_I2S_SAMPLE_LEN_22 0x5
140c5827789SArchit Taneja #define ADV7511_I2S_SAMPLE_LEN_19 0x8
141c5827789SArchit Taneja #define ADV7511_I2S_SAMPLE_LEN_23 0x9
142c5827789SArchit Taneja #define ADV7511_I2S_SAMPLE_LEN_24 0xb
143c5827789SArchit Taneja #define ADV7511_I2S_SAMPLE_LEN_17 0xc
144c5827789SArchit Taneja #define ADV7511_I2S_SAMPLE_LEN_21 0xd
145c5827789SArchit Taneja
146c5827789SArchit Taneja #define ADV7511_SAMPLE_FREQ_44100 0x0
147c5827789SArchit Taneja #define ADV7511_SAMPLE_FREQ_48000 0x2
148c5827789SArchit Taneja #define ADV7511_SAMPLE_FREQ_32000 0x3
149c5827789SArchit Taneja #define ADV7511_SAMPLE_FREQ_88200 0x8
150c5827789SArchit Taneja #define ADV7511_SAMPLE_FREQ_96000 0xa
151c5827789SArchit Taneja #define ADV7511_SAMPLE_FREQ_176400 0xc
152c5827789SArchit Taneja #define ADV7511_SAMPLE_FREQ_192000 0xe
153c5827789SArchit Taneja
154c5827789SArchit Taneja #define ADV7511_STATUS_POWER_DOWN_POLARITY BIT(7)
155c5827789SArchit Taneja #define ADV7511_STATUS_HPD BIT(6)
156c5827789SArchit Taneja #define ADV7511_STATUS_MONITOR_SENSE BIT(5)
157c5827789SArchit Taneja #define ADV7511_STATUS_I2S_32BIT_MODE BIT(3)
158c5827789SArchit Taneja
159c5827789SArchit Taneja #define ADV7511_PACKET_ENABLE_N_CTS BIT(8+6)
160c5827789SArchit Taneja #define ADV7511_PACKET_ENABLE_AUDIO_SAMPLE BIT(8+5)
161c5827789SArchit Taneja #define ADV7511_PACKET_ENABLE_AVI_INFOFRAME BIT(8+4)
162c5827789SArchit Taneja #define ADV7511_PACKET_ENABLE_AUDIO_INFOFRAME BIT(8+3)
163c5827789SArchit Taneja #define ADV7511_PACKET_ENABLE_GC BIT(7)
164c5827789SArchit Taneja #define ADV7511_PACKET_ENABLE_SPD BIT(6)
165c5827789SArchit Taneja #define ADV7511_PACKET_ENABLE_MPEG BIT(5)
166c5827789SArchit Taneja #define ADV7511_PACKET_ENABLE_ACP BIT(4)
167c5827789SArchit Taneja #define ADV7511_PACKET_ENABLE_ISRC BIT(3)
168c5827789SArchit Taneja #define ADV7511_PACKET_ENABLE_GM BIT(2)
169c5827789SArchit Taneja #define ADV7511_PACKET_ENABLE_SPARE2 BIT(1)
170c5827789SArchit Taneja #define ADV7511_PACKET_ENABLE_SPARE1 BIT(0)
171c5827789SArchit Taneja
1723dbc84a5SJagan Teki #define ADV7535_REG_POWER2_HPD_OVERRIDE BIT(6)
173c5827789SArchit Taneja #define ADV7511_REG_POWER2_HPD_SRC_MASK 0xc0
174c5827789SArchit Taneja #define ADV7511_REG_POWER2_HPD_SRC_BOTH 0x00
175c5827789SArchit Taneja #define ADV7511_REG_POWER2_HPD_SRC_HPD 0x40
176c5827789SArchit Taneja #define ADV7511_REG_POWER2_HPD_SRC_CEC 0x80
177c5827789SArchit Taneja #define ADV7511_REG_POWER2_HPD_SRC_NONE 0xc0
178c5827789SArchit Taneja #define ADV7511_REG_POWER2_TDMS_ENABLE BIT(4)
179c5827789SArchit Taneja #define ADV7511_REG_POWER2_GATE_INPUT_CLK BIT(0)
180c5827789SArchit Taneja
181c5827789SArchit Taneja #define ADV7511_LOW_REFRESH_RATE_NONE 0x0
182c5827789SArchit Taneja #define ADV7511_LOW_REFRESH_RATE_24HZ 0x1
183c5827789SArchit Taneja #define ADV7511_LOW_REFRESH_RATE_25HZ 0x2
184c5827789SArchit Taneja #define ADV7511_LOW_REFRESH_RATE_30HZ 0x3
185c5827789SArchit Taneja
186c5827789SArchit Taneja #define ADV7511_AUDIO_CFG3_LEN_MASK 0x0f
187c5827789SArchit Taneja #define ADV7511_I2C_FREQ_ID_CFG_RATE_MASK 0xf0
188c5827789SArchit Taneja
189c5827789SArchit Taneja #define ADV7511_AUDIO_SOURCE_I2S 0
190c5827789SArchit Taneja #define ADV7511_AUDIO_SOURCE_SPDIF 1
191c5827789SArchit Taneja
192c5827789SArchit Taneja #define ADV7511_I2S_FORMAT_I2S 0
193c5827789SArchit Taneja #define ADV7511_I2S_FORMAT_RIGHT_J 1
194c5827789SArchit Taneja #define ADV7511_I2S_FORMAT_LEFT_J 2
195ae053fa2SSia Jee Heng #define ADV7511_I2S_IEC958_DIRECT 3
196c5827789SArchit Taneja
197c5827789SArchit Taneja #define ADV7511_PACKET(p, x) ((p) * 0x20 + (x))
198c5827789SArchit Taneja #define ADV7511_PACKET_SDP(x) ADV7511_PACKET(0, x)
199c5827789SArchit Taneja #define ADV7511_PACKET_MPEG(x) ADV7511_PACKET(1, x)
200c5827789SArchit Taneja #define ADV7511_PACKET_ACP(x) ADV7511_PACKET(2, x)
201c5827789SArchit Taneja #define ADV7511_PACKET_ISRC1(x) ADV7511_PACKET(3, x)
202c5827789SArchit Taneja #define ADV7511_PACKET_ISRC2(x) ADV7511_PACKET(4, x)
203c5827789SArchit Taneja #define ADV7511_PACKET_GM(x) ADV7511_PACKET(5, x)
204c5827789SArchit Taneja #define ADV7511_PACKET_SPARE(x) ADV7511_PACKET(6, x)
205c5827789SArchit Taneja
2063b1b9750SHans Verkuil #define ADV7511_REG_CEC_TX_FRAME_HDR 0x00
2073b1b9750SHans Verkuil #define ADV7511_REG_CEC_TX_FRAME_DATA0 0x01
2083b1b9750SHans Verkuil #define ADV7511_REG_CEC_TX_FRAME_LEN 0x10
2093b1b9750SHans Verkuil #define ADV7511_REG_CEC_TX_ENABLE 0x11
2103b1b9750SHans Verkuil #define ADV7511_REG_CEC_TX_RETRY 0x12
2113b1b9750SHans Verkuil #define ADV7511_REG_CEC_TX_LOW_DRV_CNT 0x14
212ab0af093SAlvin Šipraga #define ADV7511_REG_CEC_RX1_FRAME_HDR 0x15
213ab0af093SAlvin Šipraga #define ADV7511_REG_CEC_RX1_FRAME_DATA0 0x16
214ab0af093SAlvin Šipraga #define ADV7511_REG_CEC_RX1_FRAME_LEN 0x25
215ab0af093SAlvin Šipraga #define ADV7511_REG_CEC_RX_STATUS 0x26
216ab0af093SAlvin Šipraga #define ADV7511_REG_CEC_RX2_FRAME_HDR 0x27
217ab0af093SAlvin Šipraga #define ADV7511_REG_CEC_RX2_FRAME_DATA0 0x28
218ab0af093SAlvin Šipraga #define ADV7511_REG_CEC_RX2_FRAME_LEN 0x37
219ab0af093SAlvin Šipraga #define ADV7511_REG_CEC_RX3_FRAME_HDR 0x38
220ab0af093SAlvin Šipraga #define ADV7511_REG_CEC_RX3_FRAME_DATA0 0x39
221ab0af093SAlvin Šipraga #define ADV7511_REG_CEC_RX3_FRAME_LEN 0x48
2223b1b9750SHans Verkuil #define ADV7511_REG_CEC_RX_BUFFERS 0x4a
2233b1b9750SHans Verkuil #define ADV7511_REG_CEC_LOG_ADDR_MASK 0x4b
2243b1b9750SHans Verkuil #define ADV7511_REG_CEC_LOG_ADDR_0_1 0x4c
2253b1b9750SHans Verkuil #define ADV7511_REG_CEC_LOG_ADDR_2 0x4d
2263b1b9750SHans Verkuil #define ADV7511_REG_CEC_CLK_DIV 0x4e
2273b1b9750SHans Verkuil #define ADV7511_REG_CEC_SOFT_RESET 0x50
2283b1b9750SHans Verkuil
2293b1b9750SHans Verkuil #define ADV7533_REG_CEC_OFFSET 0x70
2303b1b9750SHans Verkuil
231c5827789SArchit Taneja enum adv7511_input_clock {
232c5827789SArchit Taneja ADV7511_INPUT_CLOCK_1X,
233c5827789SArchit Taneja ADV7511_INPUT_CLOCK_2X,
234c5827789SArchit Taneja ADV7511_INPUT_CLOCK_DDR,
235c5827789SArchit Taneja };
236c5827789SArchit Taneja
237c5827789SArchit Taneja enum adv7511_input_justification {
238c5827789SArchit Taneja ADV7511_INPUT_JUSTIFICATION_EVENLY = 0,
239c5827789SArchit Taneja ADV7511_INPUT_JUSTIFICATION_RIGHT = 1,
240c5827789SArchit Taneja ADV7511_INPUT_JUSTIFICATION_LEFT = 2,
241c5827789SArchit Taneja };
242c5827789SArchit Taneja
243c5827789SArchit Taneja enum adv7511_input_sync_pulse {
244c5827789SArchit Taneja ADV7511_INPUT_SYNC_PULSE_DE = 0,
245c5827789SArchit Taneja ADV7511_INPUT_SYNC_PULSE_HSYNC = 1,
246c5827789SArchit Taneja ADV7511_INPUT_SYNC_PULSE_VSYNC = 2,
247c5827789SArchit Taneja ADV7511_INPUT_SYNC_PULSE_NONE = 3,
248c5827789SArchit Taneja };
249c5827789SArchit Taneja
250c5827789SArchit Taneja /**
251c5827789SArchit Taneja * enum adv7511_sync_polarity - Polarity for the input sync signals
252c5827789SArchit Taneja * @ADV7511_SYNC_POLARITY_PASSTHROUGH: Sync polarity matches that of
253c5827789SArchit Taneja * the currently configured mode.
254c5827789SArchit Taneja * @ADV7511_SYNC_POLARITY_LOW: Sync polarity is low
255c5827789SArchit Taneja * @ADV7511_SYNC_POLARITY_HIGH: Sync polarity is high
256c5827789SArchit Taneja *
257c5827789SArchit Taneja * If the polarity is set to either LOW or HIGH the driver will configure the
258c5827789SArchit Taneja * ADV7511 to internally invert the sync signal if required to match the sync
259c5827789SArchit Taneja * polarity setting for the currently selected output mode.
260c5827789SArchit Taneja *
261c5827789SArchit Taneja * If the polarity is set to PASSTHROUGH, the ADV7511 will route the signal
262c5827789SArchit Taneja * unchanged. This is used when the upstream graphics core already generates
263c5827789SArchit Taneja * the sync signals with the correct polarity.
264c5827789SArchit Taneja */
265c5827789SArchit Taneja enum adv7511_sync_polarity {
266c5827789SArchit Taneja ADV7511_SYNC_POLARITY_PASSTHROUGH,
267c5827789SArchit Taneja ADV7511_SYNC_POLARITY_LOW,
268c5827789SArchit Taneja ADV7511_SYNC_POLARITY_HIGH,
269c5827789SArchit Taneja };
270c5827789SArchit Taneja
271c5827789SArchit Taneja /**
272c5827789SArchit Taneja * struct adv7511_link_config - Describes adv7511 hardware configuration
273c5827789SArchit Taneja * @input_color_depth: Number of bits per color component (8, 10 or 12)
274c5827789SArchit Taneja * @input_colorspace: The input colorspace (RGB, YUV444, YUV422)
275c5827789SArchit Taneja * @input_clock: The input video clock style (1x, 2x, DDR)
276c5827789SArchit Taneja * @input_style: The input component arrangement variant
277c5827789SArchit Taneja * @input_justification: Video input format bit justification
278c5827789SArchit Taneja * @clock_delay: Clock delay for the input clock (in ps)
279c5827789SArchit Taneja * @embedded_sync: Video input uses BT.656-style embedded sync
280c5827789SArchit Taneja * @sync_pulse: Select the sync pulse
281c5827789SArchit Taneja * @vsync_polarity: vsync input signal configuration
282c5827789SArchit Taneja * @hsync_polarity: hsync input signal configuration
283c5827789SArchit Taneja */
284c5827789SArchit Taneja struct adv7511_link_config {
285c5827789SArchit Taneja unsigned int input_color_depth;
286c5827789SArchit Taneja enum hdmi_colorspace input_colorspace;
287c5827789SArchit Taneja enum adv7511_input_clock input_clock;
288c5827789SArchit Taneja unsigned int input_style;
289c5827789SArchit Taneja enum adv7511_input_justification input_justification;
290c5827789SArchit Taneja
291c5827789SArchit Taneja int clock_delay;
292c5827789SArchit Taneja
293c5827789SArchit Taneja bool embedded_sync;
294c5827789SArchit Taneja enum adv7511_input_sync_pulse sync_pulse;
295c5827789SArchit Taneja enum adv7511_sync_polarity vsync_polarity;
296c5827789SArchit Taneja enum adv7511_sync_polarity hsync_polarity;
297c5827789SArchit Taneja };
298c5827789SArchit Taneja
299c5827789SArchit Taneja /**
300c5827789SArchit Taneja * enum adv7511_csc_scaling - Scaling factor for the ADV7511 CSC
301c5827789SArchit Taneja * @ADV7511_CSC_SCALING_1: CSC results are not scaled
302c5827789SArchit Taneja * @ADV7511_CSC_SCALING_2: CSC results are scaled by a factor of two
303c5827789SArchit Taneja * @ADV7511_CSC_SCALING_4: CSC results are scalled by a factor of four
304c5827789SArchit Taneja */
305c5827789SArchit Taneja enum adv7511_csc_scaling {
306c5827789SArchit Taneja ADV7511_CSC_SCALING_1 = 0,
307c5827789SArchit Taneja ADV7511_CSC_SCALING_2 = 1,
308c5827789SArchit Taneja ADV7511_CSC_SCALING_4 = 2,
309c5827789SArchit Taneja };
310c5827789SArchit Taneja
311c5827789SArchit Taneja /**
312c5827789SArchit Taneja * struct adv7511_video_config - Describes adv7511 hardware configuration
313c5827789SArchit Taneja * @csc_enable: Whether to enable color space conversion
314c5827789SArchit Taneja * @csc_scaling_factor: Color space conversion scaling factor
315c5827789SArchit Taneja * @csc_coefficents: Color space conversion coefficents
316c5827789SArchit Taneja * @hdmi_mode: Whether to use HDMI or DVI output mode
317c5827789SArchit Taneja * @avi_infoframe: HDMI infoframe
318c5827789SArchit Taneja */
319c5827789SArchit Taneja struct adv7511_video_config {
320c5827789SArchit Taneja bool csc_enable;
321c5827789SArchit Taneja enum adv7511_csc_scaling csc_scaling_factor;
322c5827789SArchit Taneja const uint16_t *csc_coefficents;
323c5827789SArchit Taneja
324c5827789SArchit Taneja bool hdmi_mode;
325c5827789SArchit Taneja struct hdmi_avi_infoframe avi_infoframe;
326c5827789SArchit Taneja };
327c5827789SArchit Taneja
3282437e7cdSArchit Taneja enum adv7511_type {
3292437e7cdSArchit Taneja ADV7511,
3302437e7cdSArchit Taneja ADV7533,
3318501fe4bSBogdan Togorean ADV7535,
3322437e7cdSArchit Taneja };
3332437e7cdSArchit Taneja
3343b1b9750SHans Verkuil #define ADV7511_MAX_ADDRS 3
3353b1b9750SHans Verkuil
3362437e7cdSArchit Taneja struct adv7511 {
3372437e7cdSArchit Taneja struct i2c_client *i2c_main;
3382437e7cdSArchit Taneja struct i2c_client *i2c_edid;
339680532c5SKieran Bingham struct i2c_client *i2c_packet;
3402437e7cdSArchit Taneja struct i2c_client *i2c_cec;
3412437e7cdSArchit Taneja
3422437e7cdSArchit Taneja struct regmap *regmap;
3432437e7cdSArchit Taneja struct regmap *regmap_cec;
3440aae7623SAlvin Šipraga unsigned int reg_cec_offset;
3452437e7cdSArchit Taneja enum drm_connector_status status;
3462437e7cdSArchit Taneja bool powered;
3472437e7cdSArchit Taneja
34878fa479dSArchit Taneja struct drm_display_mode curr_mode;
34978fa479dSArchit Taneja
3502437e7cdSArchit Taneja unsigned int f_tmds;
35153c515beSJohn Stultz unsigned int f_audio;
35253c515beSJohn Stultz unsigned int audio_source;
3532437e7cdSArchit Taneja
3542437e7cdSArchit Taneja unsigned int current_edid_segment;
3552437e7cdSArchit Taneja uint8_t edid_buf[256];
3562437e7cdSArchit Taneja bool edid_read;
3572437e7cdSArchit Taneja
3582437e7cdSArchit Taneja wait_queue_head_t wq;
359518cb705SJohn Stultz struct work_struct hpd_work;
360518cb705SJohn Stultz
3612437e7cdSArchit Taneja struct drm_bridge bridge;
3622437e7cdSArchit Taneja struct drm_connector connector;
3632437e7cdSArchit Taneja
3642437e7cdSArchit Taneja bool embedded_sync;
3652437e7cdSArchit Taneja enum adv7511_sync_polarity vsync_polarity;
3662437e7cdSArchit Taneja enum adv7511_sync_polarity hsync_polarity;
3672437e7cdSArchit Taneja bool rgb;
3682437e7cdSArchit Taneja
3692437e7cdSArchit Taneja struct gpio_desc *gpio_pd;
3702437e7cdSArchit Taneja
3715b06ba23SArchit Taneja struct regulator_bulk_data *supplies;
3725b06ba23SArchit Taneja unsigned int num_supplies;
3735b06ba23SArchit Taneja
3741e4d58cdSArchit Taneja /* ADV7533 DSI RX related params */
3751e4d58cdSArchit Taneja struct device_node *host_node;
3761e4d58cdSArchit Taneja struct mipi_dsi_device *dsi;
3771e4d58cdSArchit Taneja u8 num_dsi_lanes;
37878fa479dSArchit Taneja bool use_timing_gen;
3791e4d58cdSArchit Taneja
3802437e7cdSArchit Taneja enum adv7511_type type;
38153c515beSJohn Stultz struct platform_device *audio_pdev;
3823b1b9750SHans Verkuil
3833b1b9750SHans Verkuil struct cec_adapter *cec_adap;
3843b1b9750SHans Verkuil u8 cec_addr[ADV7511_MAX_ADDRS];
3853b1b9750SHans Verkuil u8 cec_valid_addrs;
3863b1b9750SHans Verkuil bool cec_enabled_adap;
3873b1b9750SHans Verkuil struct clk *cec_clk;
3883b1b9750SHans Verkuil u32 cec_clk_freq;
3892437e7cdSArchit Taneja };
3902437e7cdSArchit Taneja
3913b1b9750SHans Verkuil #ifdef CONFIG_DRM_I2C_ADV7511_CEC
3921b6fba45SHans Verkuil int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511);
3933b1b9750SHans Verkuil void adv7511_cec_irq_process(struct adv7511 *adv7511, unsigned int irq1);
3941b6fba45SHans Verkuil #else
adv7511_cec_init(struct device * dev,struct adv7511 * adv7511)3951b6fba45SHans Verkuil static inline int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511)
3961b6fba45SHans Verkuil {
3971d22b603SAlvin Šipraga regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL,
3981b6fba45SHans Verkuil ADV7511_CEC_CTRL_POWER_DOWN);
3991b6fba45SHans Verkuil return 0;
4001b6fba45SHans Verkuil }
4013b1b9750SHans Verkuil #endif
4023b1b9750SHans Verkuil
4032437e7cdSArchit Taneja void adv7533_dsi_power_on(struct adv7511 *adv);
4042437e7cdSArchit Taneja void adv7533_dsi_power_off(struct adv7511 *adv);
405*9a0cdcd6SAbhinav Kumar enum drm_mode_status adv7533_mode_valid(struct adv7511 *adv,
406*9a0cdcd6SAbhinav Kumar const struct drm_display_mode *mode);
4072437e7cdSArchit Taneja int adv7533_patch_registers(struct adv7511 *adv);
4083b1b9750SHans Verkuil int adv7533_patch_cec_registers(struct adv7511 *adv);
4091e4d58cdSArchit Taneja int adv7533_attach_dsi(struct adv7511 *adv);
4101e4d58cdSArchit Taneja int adv7533_parse_dt(struct device_node *np, struct adv7511 *adv);
4112437e7cdSArchit Taneja
41253c515beSJohn Stultz #ifdef CONFIG_DRM_I2C_ADV7511_AUDIO
41353c515beSJohn Stultz int adv7511_audio_init(struct device *dev, struct adv7511 *adv7511);
41453c515beSJohn Stultz void adv7511_audio_exit(struct adv7511 *adv7511);
41553c515beSJohn Stultz #else /*CONFIG_DRM_I2C_ADV7511_AUDIO */
adv7511_audio_init(struct device * dev,struct adv7511 * adv7511)41653c515beSJohn Stultz static inline int adv7511_audio_init(struct device *dev, struct adv7511 *adv7511)
41753c515beSJohn Stultz {
41853c515beSJohn Stultz return 0;
41953c515beSJohn Stultz }
adv7511_audio_exit(struct adv7511 * adv7511)42053c515beSJohn Stultz static inline void adv7511_audio_exit(struct adv7511 *adv7511)
42153c515beSJohn Stultz {
42253c515beSJohn Stultz }
42353c515beSJohn Stultz #endif /* CONFIG_DRM_I2C_ADV7511_AUDIO */
42453c515beSJohn Stultz
425c5827789SArchit Taneja #endif /* __DRM_I2C_ADV7511_H__ */
426