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/openbmc/u-boot/cmd/x86/
H A Dmtrr.c1 // SPDX-License-Identifier: GPL-2.0+
24 printf("Reg Valid Write-type %-16s %-16s %-16s\n", "Base ||", in do_mtrr_list()
25 "Mask ||", "Size ||"); in do_mtrr_list()
28 uint64_t base, mask, size; in do_mtrr_list() local
29 bool valid; in do_mtrr_list() local
32 mask = native_read_msr(MTRR_PHYS_MASK_MSR(i)); in do_mtrr_list()
33 size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1); in do_mtrr_list()
34 size |= (1 << 12) - 1; in do_mtrr_list()
36 valid = mask & MTRR_PHYS_MASK_VALID; in do_mtrr_list()
38 printf("%d %-5s %-12s %016llx %016llx %016llx\n", i, in do_mtrr_list()
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/openbmc/u-boot/arch/arm/mach-imx/mx7ulp/
H A Dscg.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/imx-regs.h>
22 reg = readl(&scg1_regs->sosccsr); in scg_src_get_rate()
28 reg = readl(&scg1_regs->firccsr); in scg_src_get_rate()
34 reg = readl(&scg1_regs->sirccsr); in scg_src_get_rate()
40 reg = readl(&scg1_regs->rtccsr); in scg_src_get_rate()
55 u32 shift, mask; in scg_sircdiv_get_rate() local
59 mask = SCG_SIRCDIV_DIV1_MASK; in scg_sircdiv_get_rate()
63 mask = SCG_SIRCDIV_DIV2_MASK; in scg_sircdiv_get_rate()
67 mask = SCG_SIRCDIV_DIV3_MASK; in scg_sircdiv_get_rate()
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/openbmc/u-boot/drivers/phy/marvell/
H A Dcomphy_mux.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Marvell International Ltd.
15 * is valid for specific lane. If the type is not valid,
23 int lane, opt, valid; in comphy_mux_check_config() local
30 if (comphy_map_data->type == PHY_TYPE_IGNORE) in comphy_mux_check_config()
33 mux_opt = mux_data->mux_values; in comphy_mux_check_config()
34 for (opt = 0, valid = 0; opt < mux_data->max_lane_values; in comphy_mux_check_config()
36 if (mux_opt->type == comphy_map_data->type) { in comphy_mux_check_config()
37 valid = 1; in comphy_mux_check_config()
41 if (valid == 0) { in comphy_mux_check_config()
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/openbmc/phosphor-networkd/src/
H A Dncsi_netlink_main.cpp1 // SPDX-License-Identifier: Apache-2.0
2 // SPDX-FileCopyrightText: Copyright 2018 IBM Corporation
10 #include <phosphor-logging/lg2.hpp>
129 auto payloadStr = (options)["oem-payload"]; in main()
139 // up for the ncsi-cmd operation, which has these as separate arguments. in main()
149 "ncsi-cmd", in main()
150 "-i", in main()
152 "-p", in main()
158 args.push_back("-c"); in main()
176 lg2::debug("ncsi-netlink [..] -o is deprecated by ncsi-cmd"); in main()
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.core_prefetch2 ---------------------------------
7 Here 0x02 can be replaced with any valid value except Mask[0] bit. It
8 represents 64 bit mask. The 64-bit Mask has one bit for each core.
9 Mask[0] = core0
10 Mask[1] = core1
11 Mask[2] = core2
13 If the bit is set ('b1) in the mask, then prefetch is disabled for
16 core0 prefetch should not be disabled i.e. Mask[0] should never be set.
17 Setting Mask[0] may lead to undefined behavior.
20 There is no function to re-enable prefetch.
/openbmc/u-boot/include/
H A Dfsl_tgec.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
17 u32 mac_addr_0; /* Lower 32 bits of 48-bit MAC address */
18 u32 mac_addr_1; /* Upper 16 bits of 48-bit MAC address */
25 u32 tx_ipg_length; /* Transmitter inter-packet-gap register */
26 u32 mac_addr_2; /* Lower 32 bits of the 2nd 48-bit MAC addr */
27 u32 mac_addr_3; /* Upper 16 bits of the 2nd 48-bit MAC addr */
29 u32 imask; /* Interrupt mask register */
41 u32 tx_pause_frame_u; /* Tx valid pause frame upper */
42 u32 tx_pause_frame_l; /* Tx valid pause frame lower */
[all …]
H A Dfsl_memac.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Roy Zang <tie-fei.zang@freescale.com>
16 u32 mac_addr_0; /* Lower 32 bits of 48-bit MAC address */
17 u32 mac_addr_1; /* Upper 16 bits of 48-bit MAC address */
23 u32 tx_ipg_length; /* Transmitter inter-packet-gap register */
25 u32 imask; /* interrupt mask register */
27 u32 cl_pause_quanta[4]; /* CL01-CL67 pause quanta register */
28 u32 cl_pause_thresh[4]; /* CL01-CL67 pause thresh register */
45 u32 rx_pause_frame_l; /* Rx valid pause frame upper */
46 u32 rx_pause_frame_u; /* Rx valid pause frame upper */
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H A Dstatus_led.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2000-2004
10 * PCBoot, a status LED is blinking. As soon as a valid BOOTP reply
59 /* led_id_t is unsigned long mask */
62 extern void __led_toggle (led_id_t mask);
63 extern void __led_init (led_id_t mask, int state);
64 extern void __led_set (led_id_t mask, int state);
65 void __led_blink(led_id_t mask, int freq);
/openbmc/openbmc-test-automation/ipmi/
H A Dtest_ipmi_network_configuration.robot48 Valid Value lan_print_output['IP Address'] ["${STATIC_IP}"]
49 Valid Value lan_print_output['Subnet Mask'] ["${NETMASK}"]
50 Valid Value lan_print_output['Default Gateway IP'] ["${GATEWAY}"]
86 Valid Value lan_config['802.1q VLAN ID'] ['Disabled']
99 Valid Value lan_config['802.1q VLAN ID'] ['${vlan_id_for_ipmi}']
100 Valid Value lan_config['IP Address'] ["${STATIC_IP}"]
111 Valid Value lan_config['802.1q VLAN ID'] ['${vlan_id_for_ipmi}']
121 Valid Value lan_config['802.1q VLAN ID'] ['${vlan_id_for_ipmi}']
122 Valid Value lan_config['IP Address'] ['${ip_address}']
123 Valid Value lan_config['Subnet Mask'] ['${subnet_mask}']
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/openbmc/qemu/include/qemu/
H A Dbitops.h9 * See the COPYING.LIB file in the top-level directory.
16 #include "host-utils.h"
28 (((~0ULL) >> (64 - (length))) << (shift))
33 * We provide a set of functions which work on arbitrary-length arrays of
37 * - Bits stored in an array of 'unsigned long': set_bit(), clear_bit(), etc
38 * - Bits stored in an array of 'uint32_t': set_bit32(), clear_bit32(), etc
43 * be some guest-visible register view of the bit array.
63 * set_bit - Set a bit in memory
69 unsigned long mask = BIT_MASK(nr); in set_bit() local
72 *p |= mask; in set_bit()
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H A Dlog.h5 #include "qemu/log-for-trace.h"
31 /* LOG_TRACE (1 << 15) is defined in log-for-trace.h */
35 /* LOG_STRACE is used for user-mode strace logging. */
49 /* log only if a bit is set on the current loglevel mask:
50 * @mask: bit to check in the mask
51 * @fmt: printf-style format string
54 #define qemu_log_mask(MASK, FMT, ...) \ argument
56 if (unlikely(qemu_loglevel_mask(MASK))) { \
61 /* log only if a bit is set on the current loglevel mask
63 * @mask: bit to check in the mask
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/openbmc/qemu/hw/misc/
H A Dpc-testdev.c30 * qemu-system-x86_64 -device pc-testdev -serial stdio \
31 * -device isa-debug-exit,iobase=0xf4,iosize=0x4 \
32 * -kernel /home/lmr/Code/virt-test.git/kvm/unittests/msr.flat
35 * https://git.kernel.org/pub/scm/virt/kvm/kvm-unit-tests.git
58 #define TYPE_TESTDEV "pc-testdev"
78 .valid.min_access_size = 1,
79 .valid.max_access_size = 1,
89 uint32_t mask = ((uint32_t)-1 >> (32 - bits)) << start_bit; in test_ioport_write() local
90 dev->ioport_data &= ~mask; in test_ioport_write()
91 dev->ioport_data |= data << start_bit; in test_ioport_write()
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/openbmc/openbmc/poky/meta/recipes-extended/tcp-wrappers/tcp-wrappers-7.6/
H A D15_match_clarify.patch1 Upstream-Status: Inactive-Upstream [current release is from 1997; no vcs anywhere]
3 diff -ruN tcp_wrappers_7.6.orig/hosts_access.5 tcp_wrappers_7.6/hosts_access.5
4 --- tcp_wrappers_7.6.orig/hosts_access.5 2004-04-25 12:17:59.000000000 +0200
5 +++ tcp_wrappers_7.6/hosts_access.5 2004-04-25 12:17:53.000000000 +0200
6 @@ -89,6 +89,8 @@
7 bitwise AND of the address and the `mask\'. For example, the net/mask
10 +`255.255.255.255\' is not a valid mask value, so a single host can be
/openbmc/u-boot/doc/device-tree-bindings/memory/
H A Dmemory.txt3 The memory binding for U-Boot is as in the ePAPR with the following additions:
6 ID masks. To match a set of board ids, a board-id node may define match-mask
7 and match-value ints to define a mask to apply to the board id, and the value
8 that the result should have for the match to be considered valid. The mask
9 defaults to -1, meaning that the value must fully match the board id.
13 - #address-cells: should be 1.
14 - #size-cells: should be 0.
18 reg - board ID or mask for this subnode
19 memory-banks - list of memory banks in the same format as normal
23 match-mask - A mask to apply to the board id. This must be accompanied by
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/openbmc/qemu/util/
H A Dunicode.c10 * later. See the COPYING file in the top-level directory.
33 * @s: string encoded in modified UTF-8
37 * Convert the modified UTF-8 sequence at the start of @s. Modified
38 * UTF-8 is exactly like UTF-8, except U+0000 is encoded as
50 * sequence is well-formed, and @end is set to @s + 1 + expected
53 * A well-formed sequence is valid unless it encodes a codepoint
56 * overlong sequence "\xC0\x80" is valid.
58 * Conversion succeeds if and only if the sequence is valid.
60 * Returns: the Unicode codepoint on success, -1 on failure.
66 unsigned byte, mask, len, i; in mod_utf8_codepoint() local
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/openbmc/qemu/hw/ppc/
H A Dpnv_homer.c25 #include "hw/qdev-core.h"
26 #include "hw/qdev-properties.h"
52 val = homer->base; in pnv_homer_power8_pba_read()
54 case PBA_BARMASK0: /* P8 homer region mask */ in pnv_homer_power8_pba_read()
55 val = (hmrc->size - 1) & 0x300000; in pnv_homer_power8_pba_read()
60 case PBA_BARMASK3: /* P8 occ common area mask */ in pnv_homer_power8_pba_read()
61 val = (PNV_OCC_COMMON_AREA_SIZE - 1) & 0x700000; in pnv_homer_power8_pba_read()
80 .valid.min_access_size = 8,
81 .valid.max_access_size = 8,
96 homer->get_base = pnv_homer_power8_get_base; in pnv_homer_power8_class_init()
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/openbmc/qemu/hw/intc/
H A Dloongson_ipi_common.c1 /* SPDX-License-Identifier: GPL-2.0-or-later */
27 ret = s->status; in loongson_ipi_core_readl()
30 ret = s->en; in loongson_ipi_core_readl()
39 index = (addr - CORE_BUF_20) >> 2; in loongson_ipi_core_readl()
40 ret = s->buf[index]; in loongson_ipi_core_readl()
60 if (attrs.requester_id >= ipi->num_cpu) { in loongson_ipi_iocsr_readl()
64 s = &ipi->cpu[attrs.requester_id]; in loongson_ipi_iocsr_readl()
72 int i, mask = 0, data = 0; in send_ipi_data() local
73 AddressSpace *iocsr_as = licc->get_iocsr_as(cpu); in send_ipi_data()
80 * bit 27-30 is mask for byte writing, in send_ipi_data()
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/openbmc/phosphor-debug-collector/
H A Dwatch.cpp5 #include <phosphor-logging/elog-errors.hpp>
6 #include <phosphor-logging/lg2.hpp>
30 Watch::Watch(const EventPtr& eventObj, const int flags, const uint32_t mask, in Watch() argument
33 flags(flags), mask(mask), events(events), path(path), fd(inotifyInit()), in Watch()
44 wd = inotify_add_watch(fd(), path.c_str(), mask); in Watch()
45 if (-1 == wd) in Watch()
69 if (-1 == fd) in inotifyInit()
84 if ((revents & userData->events) == 0U) in callback()
113 auto mask = event->mask & userData->mask; in callback() local
115 if (mask != 0U) in callback()
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/openbmc/qemu/hw/pci-host/
H A Dpnv_phb3_pbcq.c4 * Copyright (c) 2014-2020, IBM Corporation.
7 * COPYING file in the top-level directory.
14 #include "hw/pci-host/pnv_phb3_regs.h"
15 #include "hw/pci-host/pnv_phb3.h"
25 (pbcq)->phb->chip_id, (pbcq)->phb->phb_id, ## __VA_ARGS__)
33 return pbcq->nest_regs[offset]; in pnv_pbcq_nest_xscom_read()
42 return pbcq->pci_regs[offset]; in pnv_pbcq_pci_xscom_read()
52 return pnv_phb3_reg_read(pbcq->phb, in pnv_pbcq_spci_xscom_read()
53 pbcq->spci_regs[PBCQ_SPCI_ASB_ADDR], 8); in pnv_pbcq_spci_xscom_read()
55 return pbcq->spci_regs[offset]; in pnv_pbcq_spci_xscom_read()
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/openbmc/u-boot/arch/arm/mach-mvebu/serdes/a38x/
H A Dseq_exec.c1 // SPDX-License-Identifier: GPL-2.0
32 u32 unit_base_reg, unit_offset, data, mask, reg_data, reg_addr; in write_op_execute() local
35 data = params->data[data_arr_idx]; in write_op_execute()
36 mask = params->mask; in write_op_execute()
43 CHECK_STATUS(hws_get_ext_base_addr(serdes_num, params->unit_base_reg, in write_op_execute()
44 params->unit_offset, in write_op_execute()
51 printf("Write: 0x%x: 0x%x (mask 0x%x) - ", reg_addr, data, mask); in write_op_execute()
55 reg_data &= (~mask); in write_op_execute()
58 data &= mask; in write_op_execute()
63 printf(" - 0x%x\n", reg_data); in write_op_execute()
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/openbmc/qemu/hw/riscv/
H A Driscv-iommu-hpm.c2 * RISC-V IOMMU - Hardware Performance Monitor (HPM) helpers
4 * Copyright (C) 2022-2023 Rivos Inc.
22 #include "riscv-iommu-hpm.h"
23 #include "riscv-iommu.h"
24 #include "riscv-iommu-bits.h"
27 /* For now we assume IOMMU HPM frequency to be 1GHz so 1-cycle is of 1-ns. */
39 const uint64_t ctr_prev = s->hpmcycle_prev; in riscv_iommu_hpmcycle_read()
40 const uint64_t ctr_val = s->hpmcycle_val; in riscv_iommu_hpmcycle_read()
54 return (ctr_val + get_cycles() - ctr_prev) | in riscv_iommu_hpmcycle_read()
63 cntr_val = ldq_le_p(&s->regs_rw[RISCV_IOMMU_REG_IOHPMCTR_BASE + off]); in hpm_incr_ctr()
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/openbmc/qemu/docs/system/s390x/
H A Dvfio-ap.rst7 ------------
19 -------------------------
51 An AP queue is the means by which an AP command-request message is sent to an
57 which the AP command-request message is to be sent for processing.
63 * NQAP: to enqueue an AP command-request message to a queue
64 * DQAP: to dequeue an AP command-reply message from a queue
73 ----------------------------------------------
82 * The AP Mask (APM) field is a bit mask that identifies the AP adapters assigned
83 to the KVM guest. Each bit in the mask, from left to right, corresponds to
84 an APID from 0-255. If a bit is set, the corresponding adapter is valid for
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/openbmc/u-boot/drivers/misc/
H A Dstatus_led.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2000-2003
13 * U-Boot, a status LED is blinking. As soon as a valid BOOTP reply
19 /* ------------------------------------------------------------------------- */
22 led_id_t mask; member
81 __led_init (ld->mask, ld->state); in status_led_init()
95 if (ld->state != CONFIG_LED_STATUS_BLINKING) in status_led_tick()
98 if (++ld->cnt >= ld->period) { in status_led_tick()
99 __led_toggle (ld->mask); in status_led_tick()
100 ld->cnt -= ld->period; in status_led_tick()
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/openbmc/phosphor-power/phosphor-regulators/test/
H A Dvalidate-regulators-config_tests.cpp8 * http://www.apache.org/licenses/LICENSE-2.0
44 "comments": [ "Config file for a FooBar one-chassis system" ],
140 "../phosphor-regulators/tools/validate-regulators-config.py -s \ in getValidationToolCommand()
141 ../phosphor-regulators/schema/config_schema.json -c "; in getValidationToolCommand()
172 if (returnValue == -1) in runToolForOutputWithCommand()
266 // Valid: Comments property not specified in TEST()
271 // Valid: Comments property specified in TEST()
278 // Valid: and action type specified in TEST()
293 // Valid: compare_presence action type specified in TEST()
302 // Valid: compare_vpd action type specified in TEST()
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/openbmc/qemu/target/ppc/
H A Dmmu_helper.c4 * Copyright (c) 2003-2007 Jocelyn Mayer
25 #include "mmu-hash64.h"
26 #include "mmu-hash32.h"
28 #include "exec/page-protection.h"
32 #include "qemu/error-report.h"
33 #include "qemu/qemu-print.h"
35 #include "mmu-book3s-v3.h"
36 #include "mmu-radix64.h"
37 #include "mmu-booke.h"
38 #include "exec/helper-proto.h"
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