u-boot/include/fsl_tgec.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * Copyright 2009-2011 Freescale Semiconductor, Inc.
17 	u32	mac_addr_0;	/* Lower 32 bits of 48-bit MAC address */
18 	u32	mac_addr_1;	/* Upper 16 bits of 48-bit MAC address */
25 	u32	tx_ipg_length;	/* Transmitter inter-packet-gap register */
26 	u32	mac_addr_2;	/* Lower 32 bits of the 2nd 48-bit MAC addr */
27 	u32	mac_addr_3;	/* Upper 16 bits of the 2nd 48-bit MAC addr */
29 	u32	imask;		/* Interrupt mask register */
41 	u32	tx_pause_frame_u; /* Tx valid pause frame upper */
42 	u32	tx_pause_frame_l; /* Tx valid pause frame lower */
43 	u32	rx_pause_frame_u; /* Rx valid pause frame upper */
44 	u32	rx_pause_frame_l; /* Rx valid pause frame upper */
104 /* EC10G_ID - 10-gigabit ethernet MAC controller ID */
109 /* COMMAND_CONFIG - command and configuration register */
128 /* HASHTABLE_CTRL - Hashtable control register */
132 /* TX_IPG_LENGTH - Transmit inter-packet gap length register */
135 /* IMASK - interrupt mask register */
136 #define IMASK_MDIO_SCAN_EVENT	0x00010000 /* MDIO scan event mask */
137 #define IMASK_MDIO_CMD_CMPL	0x00008000 /* MDIO cmd completion mask */
138 #define IMASK_REM_FAULT		0x00004000 /* remote fault mask */
139 #define IMASK_LOC_FAULT		0x00002000 /* local fault mask */
140 #define IMASK_TX_ECC_ER		0x00001000 /* Tx frame ECC error mask */
141 #define IMASK_TX_FIFO_UNFL	0x00000800 /* Tx FIFO underflow mask */
142 #define IMASK_TX_ER		0x00000200 /* Tx frame error mask */
143 #define IMASK_RX_FIFO_OVFL	0x00000100 /* Rx FIFO overflow mask */
144 #define IMASK_RX_ECC_ER		0x00000080 /* Rx frame ECC error mask */
145 #define IMASK_RX_JAB_FRM	0x00000040 /* Rx jabber frame mask */
146 #define IMASK_RX_OVRSZ_FRM	0x00000020 /* Rx oversized frame mask */
147 #define IMASK_RX_RUNT_FRM	0x00000010 /* Rx runt frame mask */
148 #define IMASK_RX_FRAG_FRM	0x00000008 /* Rx fragment frame mask */
149 #define IMASK_RX_LEN_ER		0x00000004 /* Rx payload length error mask */
150 #define IMASK_RX_CRC_ER		0x00000002 /* Rx CRC error mask */
151 #define IMASK_RX_ALIGN_ER	0x00000001 /* Rx alignment error mask */
155 /* IEVENT - interrupt event register */