1 // SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/imx-regs.h>
22 		reg = readl(&scg1_regs->sosccsr);  in scg_src_get_rate()
28 		reg = readl(&scg1_regs->firccsr);  in scg_src_get_rate()
34 		reg = readl(&scg1_regs->sirccsr);  in scg_src_get_rate()
40 		reg = readl(&scg1_regs->rtccsr);  in scg_src_get_rate()
55 	u32 shift, mask;  in scg_sircdiv_get_rate()  local
59 		mask = SCG_SIRCDIV_DIV1_MASK;  in scg_sircdiv_get_rate()
63 		mask = SCG_SIRCDIV_DIV2_MASK;  in scg_sircdiv_get_rate()
67 		mask = SCG_SIRCDIV_DIV3_MASK;  in scg_sircdiv_get_rate()
74 	reg = readl(&scg1_regs->sirccsr);  in scg_sircdiv_get_rate()
78 	reg = readl(&scg1_regs->sircdiv);  in scg_sircdiv_get_rate()
79 	val = (reg & mask) >> shift;  in scg_sircdiv_get_rate()
85 	rate = rate / (1 << (val - 1));  in scg_sircdiv_get_rate()
93 	u32 shift, mask;  in scg_fircdiv_get_rate()  local
97 		mask = SCG_FIRCDIV_DIV1_MASK;  in scg_fircdiv_get_rate()
101 		mask = SCG_FIRCDIV_DIV2_MASK;  in scg_fircdiv_get_rate()
105 		mask = SCG_FIRCDIV_DIV3_MASK;  in scg_fircdiv_get_rate()
112 	reg = readl(&scg1_regs->firccsr);  in scg_fircdiv_get_rate()
116 	reg = readl(&scg1_regs->fircdiv);  in scg_fircdiv_get_rate()
117 	val = (reg & mask) >> shift;  in scg_fircdiv_get_rate()
123 	rate = rate / (1 << (val - 1));  in scg_fircdiv_get_rate()
131 	u32 shift, mask;  in scg_soscdiv_get_rate()  local
135 		mask = SCG_SOSCDIV_DIV1_MASK;  in scg_soscdiv_get_rate()
139 		mask = SCG_SOSCDIV_DIV2_MASK;  in scg_soscdiv_get_rate()
143 		mask = SCG_SOSCDIV_DIV3_MASK;  in scg_soscdiv_get_rate()
150 	reg = readl(&scg1_regs->sosccsr);  in scg_soscdiv_get_rate()
154 	reg = readl(&scg1_regs->soscdiv);  in scg_soscdiv_get_rate()
155 	val = (reg & mask) >> shift;  in scg_soscdiv_get_rate()
161 	rate = rate / (1 << (val - 1));  in scg_soscdiv_get_rate()
169 	u32 shift, mask, gate, valid;  in scg_apll_pfd_get_rate()  local
174 		valid = SCG_PLL_PFD0_VALID_MASK;  in scg_apll_pfd_get_rate()
175 		mask = SCG_PLL_PFD0_FRAC_MASK;  in scg_apll_pfd_get_rate()
180 		valid = SCG_PLL_PFD1_VALID_MASK;  in scg_apll_pfd_get_rate()
181 		mask = SCG_PLL_PFD1_FRAC_MASK;  in scg_apll_pfd_get_rate()
186 		valid = SCG_PLL_PFD2_VALID_MASK;  in scg_apll_pfd_get_rate()
187 		mask = SCG_PLL_PFD2_FRAC_MASK;  in scg_apll_pfd_get_rate()
192 		valid = SCG_PLL_PFD3_VALID_MASK;  in scg_apll_pfd_get_rate()
193 		mask = SCG_PLL_PFD3_FRAC_MASK;  in scg_apll_pfd_get_rate()
200 	reg = readl(&scg1_regs->apllpfd);  in scg_apll_pfd_get_rate()
201 	if (reg & gate || !(reg & valid))  in scg_apll_pfd_get_rate()
206 	val = (reg & mask) >> shift;  in scg_apll_pfd_get_rate()
219 	u32 shift, mask, gate, valid;  in scg_spll_pfd_get_rate()  local
224 		valid = SCG_PLL_PFD0_VALID_MASK;  in scg_spll_pfd_get_rate()
225 		mask = SCG_PLL_PFD0_FRAC_MASK;  in scg_spll_pfd_get_rate()
230 		valid = SCG_PLL_PFD1_VALID_MASK;  in scg_spll_pfd_get_rate()
231 		mask = SCG_PLL_PFD1_FRAC_MASK;  in scg_spll_pfd_get_rate()
236 		valid = SCG_PLL_PFD2_VALID_MASK;  in scg_spll_pfd_get_rate()
237 		mask = SCG_PLL_PFD2_FRAC_MASK;  in scg_spll_pfd_get_rate()
242 		valid = SCG_PLL_PFD3_VALID_MASK;  in scg_spll_pfd_get_rate()
243 		mask = SCG_PLL_PFD3_FRAC_MASK;  in scg_spll_pfd_get_rate()
250 	reg = readl(&scg1_regs->spllpfd);  in scg_spll_pfd_get_rate()
251 	if (reg & gate || !(reg & valid))  in scg_spll_pfd_get_rate()
256 	val = (reg & mask) >> shift;  in scg_spll_pfd_get_rate()
270 	reg = readl(&scg1_regs->apllcfg);  in scg_apll_get_rate()
298 	reg = readl(&scg1_regs->spllcfg);  in scg_spll_get_rate()
333 	reg = readl(&scg1_regs->ddrccr);  in scg_ddr_get_rate()
341 		reg = readl(&scg1_regs->apllcfg);  in scg_ddr_get_rate()
349 	rate = rate / (1 << (div - 1));  in scg_ddr_get_rate()
356 	u32 shift, mask;  in scg_nic_get_rate()  local
358 	reg = readl(&scg1_regs->niccsr);  in scg_nic_get_rate()
380 		mask = SCG_NICCSR_GPUDIV_MASK;  in scg_nic_get_rate()
386 		mask = SCG_NICCSR_NIC1DIV_MASK;  in scg_nic_get_rate()
393 	val = (reg & mask) >> shift;  in scg_nic_get_rate()
403 		mask = SCG_NICCSR_NIC1EXTDIV_MASK;  in scg_nic_get_rate()
407 		mask = SCG_NICCSR_NIC1BUSDIV_MASK;  in scg_nic_get_rate()
414 	val = (reg & mask) >> shift;  in scg_nic_get_rate()
433 	reg = readl(&scg1_regs->csr);  in scg_sys_get_rate()
480 		reg = readl(&scg1_regs->spllcsr);  in decode_pll()
485 		reg = readl(&scg1_regs->spllcfg);  in decode_pll()
501 		num = readl(&scg1_regs->spllnum);  in decode_pll()
502 		denom = readl(&scg1_regs->splldenom);  in decode_pll()
509 		reg = readl(&scg1_regs->apllcsr);  in decode_pll()
514 		reg = readl(&scg1_regs->apllcfg);  in decode_pll()
530 		num = readl(&scg1_regs->apllnum);  in decode_pll()
531 		denom = readl(&scg1_regs->aplldenom);  in decode_pll()
538 		reg = readl(&scg1_regs->upllcsr);  in decode_pll()
618 	u32 shift, mask, gate, valid;  in scg_enable_pll_pfd()  local
622 		return -EINVAL;  in scg_enable_pll_pfd()
628 		valid = SCG_PLL_PFD0_VALID_MASK;  in scg_enable_pll_pfd()
629 		mask = SCG_PLL_PFD0_FRAC_MASK;  in scg_enable_pll_pfd()
633 			addr = (u32)(&scg1_regs->spllpfd);  in scg_enable_pll_pfd()
635 			addr = (u32)(&scg1_regs->apllpfd);  in scg_enable_pll_pfd()
640 		valid = SCG_PLL_PFD1_VALID_MASK;  in scg_enable_pll_pfd()
641 		mask = SCG_PLL_PFD1_FRAC_MASK;  in scg_enable_pll_pfd()
645 			addr = (u32)(&scg1_regs->spllpfd);  in scg_enable_pll_pfd()
647 			addr = (u32)(&scg1_regs->apllpfd);  in scg_enable_pll_pfd()
652 		valid = SCG_PLL_PFD2_VALID_MASK;  in scg_enable_pll_pfd()
653 		mask = SCG_PLL_PFD2_FRAC_MASK;  in scg_enable_pll_pfd()
657 			addr = (u32)(&scg1_regs->spllpfd);  in scg_enable_pll_pfd()
659 			addr = (u32)(&scg1_regs->apllpfd);  in scg_enable_pll_pfd()
664 		valid = SCG_PLL_PFD3_VALID_MASK;  in scg_enable_pll_pfd()
665 		mask = SCG_PLL_PFD3_FRAC_MASK;  in scg_enable_pll_pfd()
669 			addr = (u32)(&scg1_regs->spllpfd);  in scg_enable_pll_pfd()
671 			addr = (u32)(&scg1_regs->apllpfd);  in scg_enable_pll_pfd()
674 		return -EINVAL;  in scg_enable_pll_pfd()
683 	reg &= ~mask;  in scg_enable_pll_pfd()
684 	reg |= (frac << shift) & mask;  in scg_enable_pll_pfd()
688 	 * Un-gate the PFD  in scg_enable_pll_pfd()
689 	 * (Need un-gate before checking valid, not align with RM)  in scg_enable_pll_pfd()
694 	/* Wait for PFD clock being valid */  in scg_enable_pll_pfd()
697 	} while (!(reg & valid));  in scg_enable_pll_pfd()
714 		return -EPERM;  in scg_enable_usb_pll()
723 	if (!(readl(&usbphy->usb1_pll_480_ctrl) & PLL_USB_LOCK_MASK)) {  in scg_enable_usb_pll()
724 		writel(0x1c00000, &usbphy->usb1_pll_480_ctrl_clr);  in scg_enable_usb_pll()
728 			writel(0xc00000, &usbphy->usb1_pll_480_ctrl_set);  in scg_enable_usb_pll()
732 			writel(0x800000, &usbphy->usb1_pll_480_ctrl_set);  in scg_enable_usb_pll()
736 			writel(0x1400000, &usbphy->usb1_pll_480_ctrl_set);  in scg_enable_usb_pll()
740 			writel(0xc00000, &usbphy->usb1_pll_480_ctrl_set);  in scg_enable_usb_pll()
746 		       &usbphy->usb1_pll_480_ctrl_set);  in scg_enable_usb_pll()
752 		writel(PLL_USB_PWR_MASK, &usbphy->usb1_pll_480_ctrl_set);  in scg_enable_usb_pll()
755 		while (timeout--) {  in scg_enable_usb_pll()
756 			if (readl(&usbphy->usb1_pll_480_ctrl) &  in scg_enable_usb_pll()
764 			       &usbphy->usb1_pll_480_ctrl_clr);  in scg_enable_usb_pll()
765 			return -ETIME;  in scg_enable_usb_pll()
770 	writel(PLL_USB_BYPASS_MASK, &usbphy->usb1_pll_480_ctrl_clr);  in scg_enable_usb_pll()
774 	       &usbphy->usb1_pll_480_ctrl_set);  in scg_enable_usb_pll()
777 		while (timeout--) {  in scg_enable_usb_pll()
778 			if (readl(&scg1_regs->upllcsr) &  in scg_enable_usb_pll()
787 			return -ETIME;  in scg_enable_usb_pll()
810 	rccr_reg_val = readl(&scg1_regs->rccr);  in scg_a7_rccr_init()
815 	writel(rccr_reg_val, &scg1_regs->rccr);  in scg_a7_rccr_init()
852 	val = readl(&scg1_regs->spllcsr);  in scg_a7_spll_init()
854 	writel(val, &scg1_regs->spllcsr);  in scg_a7_spll_init()
866 	val = readl(&scg1_regs->spllpfd);  in scg_a7_spll_init()
871 	writel(val, &scg1_regs->spllpfd);  in scg_a7_spll_init()
876 	writel(SCG1_SPLL_CFG_NUM_24M_OSC, &scg1_regs->spllcfg);  in scg_a7_spll_init()
879 	val = readl(&scg1_regs->spllcsr);  in scg_a7_spll_init()
881 	writel(val, &scg1_regs->spllcsr);  in scg_a7_spll_init()
884 	while (!(readl(&scg1_regs->spllcsr) & SCG_SPLL_CSR_SPLLVLD_MASK))  in scg_a7_spll_init()
888 	val = readl(&scg1_regs->spllpfd);  in scg_a7_spll_init()
891 	writel(val, &scg1_regs->spllpfd);  in scg_a7_spll_init()
893 	/* Un-gate A7 SPLL PFD0 */  in scg_a7_spll_init()
894 	val = readl(&scg1_regs->spllpfd);  in scg_a7_spll_init()
896 	writel(val, &scg1_regs->spllpfd);  in scg_a7_spll_init()
898 	/* Wait for A7 SPLL PFD0 clock being valid */  in scg_a7_spll_init()
899 	while (!(readl(&scg1_regs->spllpfd) & SCG_PLL_PFD0_VALID_MASK))  in scg_a7_spll_init()
917 	writel(SCG1_DDRCCR_CFG_NUM, &scg1_regs->ddrccr);  in scg_a7_ddrclk_init()
961 	val = readl(&scg1_regs->apllcsr);  in scg_a7_apll_init()
963 	writel(val, &scg1_regs->apllcsr);  in scg_a7_apll_init()
966 	val = readl(&scg1_regs->apllpfd);  in scg_a7_apll_init()
968 	writel(val, &scg1_regs->apllpfd);  in scg_a7_apll_init()
972 	writel(SCG1_APLL_CFG_NUM_24M_OSC, &scg1_regs->apllcfg);  in scg_a7_apll_init()
975 	val = readl(&scg1_regs->apllcsr);  in scg_a7_apll_init()
977 	writel(val, &scg1_regs->apllcsr);  in scg_a7_apll_init()
980 	while (!(readl(&scg1_regs->apllcsr) & SCG_APLL_CSR_APLLVLD_MASK))  in scg_a7_apll_init()
984 	val = readl(&scg1_regs->apllpfd);  in scg_a7_apll_init()
987 	writel(val, &scg1_regs->apllpfd);  in scg_a7_apll_init()
989 	/* Un-gate A7 APLL PFD0 */  in scg_a7_apll_init()
990 	val = readl(&scg1_regs->apllpfd);  in scg_a7_apll_init()
992 	writel(val, &scg1_regs->apllpfd);  in scg_a7_apll_init()
994 	/* Wait for A7 APLL PFD0 clock being valid */  in scg_a7_apll_init()
995 	while (!(readl(&scg1_regs->apllpfd) & SCG_PLL_PFD0_VALID_MASK))  in scg_a7_apll_init()
1010 	while (!(readl(&scg1_regs->firccsr) & SCG_FIRC_CSR_FIRCVLD_MASK))  in scg_a7_firc_init()
1016 			SCG1_FIRCDIV_DIV1_NUM), &scg1_regs->fircdiv);  in scg_a7_firc_init()
1038 	writel(SCG1_NICCCR_CFG_NUM, &scg1_regs->nicccr);  in scg_a7_nicclk_init()
1052 	while (!(readl(&scg1_regs->sosccsr) & SCG_SOSC_CSR_SOSCVLD_MASK))  in scg_a7_soscdiv_init()
1057 	       SCG1_SOSCDIV_DIV1_NUM), &scg1_regs->soscdiv);  in scg_a7_soscdiv_init()
1075 	rccr_reg_val = readl(&scg1_regs->rccr);  in scg_a7_sys_clk_sel()
1078 	writel(rccr_reg_val, &scg1_regs->rccr);  in scg_a7_sys_clk_sel()
1083 	debug("SCG Version: 0x%x\n", readl(&scg1_regs->verid));  in scg_a7_info()
1084 	debug("SCG Parameter: 0x%x\n", readl(&scg1_regs->param));  in scg_a7_info()
1085 	debug("SCG RCCR Value: 0x%x\n", readl(&scg1_regs->rccr));  in scg_a7_info()
1086 	debug("SCG Clock Status: 0x%x\n", readl(&scg1_regs->csr));  in scg_a7_info()