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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dsnps,dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
26 - snps,dwmac-3.610
[all …]
H A Dintel,dwmac-plat.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
17 - intel,keembay-dwmac
19 - compatible
22 - $ref: snps,dwmac.yaml#
27 - items:
28 - enum:
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/openbmc/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_dcb_82599.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
10 * ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter
70 * ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter
77 * Configure Tx Descriptor Arbiter and credits for each traffic class.
88 /* Clear the per-Tx queue credits; we use per-TC instead */ in ixgbe_dcb_config_tx_desc_arbiter_82599()
111 * Configure Tx descriptor plane (recycle mode; WSP) and in ixgbe_dcb_config_tx_desc_arbiter_82599()
121 * ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter
129 * Configure Tx Packet Arbiter and credits for each traffic class.
172 * Configure Tx packet plane (recycle mode; SP; arb delay) and in ixgbe_dcb_config_tx_data_arbiter_82599()
[all …]
H A Dixgbe_dcb_82598.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
10 * ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter
69 * ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter
76 * Configure Tx Descriptor Arbiter and credits for each traffic class.
118 * ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter
125 * Configure Tx Data Arbiter and credits for each traffic class.
159 /* Enable Tx packet buffer division */ in ixgbe_dcb_config_tx_data_arbiter_82598()
168 * ixgbe_dcb_config_pfc_82598 - Config priority flow control
194 /* Configure PFC Tx thresholds per TC */ in ixgbe_dcb_config_pfc_82598()
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsa8540p-ride.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 #include "sa8540p-pmics.dtsi"
17 compatible = "qcom,sa8540p-ride", "qcom,sa8540p";
29 stdout-path = "serial0:115200n8";
34 regulators-0 {
35 compatible = "qcom,pm8150-rpmh-regulators";
36 qcom,pmic-id = "a";
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H A Dsa8775p-ride.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
12 #include "sa8775p-pmics.dtsi"
28 stdout-path = "serial0:115200n8";
33 regulators-0 {
34 compatible = "qcom,pmm8654au-rpmh-regulators";
35 qcom,pmic-id = "a";
38 regulator-name = "vreg_s4a";
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H A Dsa8155p-adp.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
9 #include <dt-bindings/gpio/gpio.h>
16 compatible = "qcom,sa8155p-adp", "qcom,sa8155p";
24 stdout-path = "serial0:115200n8";
27 vreg_3p3: vreg-3p3-regulator {
28 compatible = "regulator-fixed";
29 regulator-name = "vreg_3p3";
30 regulator-min-microvolt = <3300000>;
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/openbmc/qemu/net/
H A Daf-xdp.c10 * See the COPYING file in the top-level directory.
26 #include "qemu/error-report.h"
28 #include "qemu/main-loop.h"
37 struct xsk_ring_prod tx; member
62 /* Set the event-loop handlers for the af-xdp backend. */
65 qemu_set_fd_handler(xsk_socket__fd(s->xsk), in af_xdp_update_fd_handler()
66 s->read_poll ? af_xdp_send : NULL, in af_xdp_update_fd_handler()
67 s->write_poll ? af_xdp_writable : NULL, in af_xdp_update_fd_handler()
74 if (s->read_poll != enable) { in af_xdp_read_poll()
75 s->read_poll = enable; in af_xdp_read_poll()
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/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "rk3588-pinctrl.dtsi"
11 compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
16 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
21 compatible = "rockchip,rk3588-i2s-tdm";
25 clock-names = "mclk_tx", "mclk_rx", "hclk";
26 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
27 assigned-clock-parents = <&cru PLL_AUPLL>;
29 dma-names = "tx";
30 power-domains = <&power RK3588_PD_VO0>;
[all …]
H A Drk3568.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
16 clock-names = "sata", "pmalive", "rxoob";
19 phy-names = "sata-phy";
20 ports-implemented = <0x1>;
21 power-domains = <&power RK3568_PD_PIPE>;
26 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
31 compatible = "rockchip,rk3568-qos", "syscon";
36 compatible = "rockchip,rk3568-qos", "syscon";
41 compatible = "rockchip,rk3568-qos", "syscon";
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/openbmc/linux/arch/arm/boot/dts/axis/
H A Dartpec6.dtsi2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
51 interrupt-parent = <&intc>;
54 #address-cells = <1>;
55 #size-cells = <0>;
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/openbmc/linux/drivers/net/ethernet/intel/fm10k/
H A Dfm10k_common.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
7 * fm10k_get_bus_info_generic - Generic set PCI bus info
17 /* Get the maximum link width and speed from PCIe config space */ in fm10k_get_bus_info_generic()
22 hw->bus_caps.width = fm10k_bus_width_pcie_x1; in fm10k_get_bus_info_generic()
25 hw->bus_caps.width = fm10k_bus_width_pcie_x2; in fm10k_get_bus_info_generic()
28 hw->bus_caps.width = fm10k_bus_width_pcie_x4; in fm10k_get_bus_info_generic()
31 hw->bus_caps.width = fm10k_bus_width_pcie_x8; in fm10k_get_bus_info_generic()
34 hw->bus_caps.width = fm10k_bus_width_unknown; in fm10k_get_bus_info_generic()
40 hw->bus_caps.speed = fm10k_bus_speed_2500; in fm10k_get_bus_info_generic()
[all …]
/openbmc/linux/drivers/net/caif/
H A Dcaif_virtio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson AB 2013
21 #include <linux/dma-mapping.h>
33 /* Defaults used if virtio config space is unavailable */
41 /* struct cfv_napi_contxt - NAPI context info
46 * used to indicate invalid head-id.
53 /* struct cfv_stats - statistic
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/openbmc/linux/drivers/net/ethernet/cadence/
H A Dmacb_main.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2006 Atmel Corporation
10 #include <linux/clk-provider.h>
25 #include <linux/dma-mapping.h>
40 #include <linux/firmware/xlnx-zynqmp.h>
57 * (bp)->rx_ring_size)
63 * (bp)->tx_ring_size)
65 /* level of occupied TX descriptors under which we wake up TX process */
66 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
77 …MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN -…
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/openbmc/linux/drivers/net/ethernet/intel/ice/
H A Dice.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 #include <linux/dma-mapping.h>
110 #define ICE_MAX_RXQS_PER_TC 256 /* Used when setting VSI context per TC Rx queues */
120 #define ICE_MAX_MTU (ICE_AQ_SET_MAC_FRAME_SIZE_MAX - ICE_ETH_PKT_HDR_PAD)
128 #define ICE_TX_DESC(R, i) (&(((struct ice_tx_desc *)((R)->desc))[i]))
129 #define ICE_RX_DESC(R, i) (&(((union ice_32b_rx_flex_desc *)((R)->desc))[i]))
130 #define ICE_TX_CTX_DESC(R, i) (&(((struct ice_tx_ctx_desc *)((R)->desc))[i]))
131 #define ICE_TX_FDIRDESC(R, i) (&(((struct ice_fltr_desc *)((R)->desc))[i]))
157 for ((i) = 0; (i) < (pf)->num_alloc_vsi; (i)++)
159 /* Macros for each Tx/Xdp/Rx ring in a VSI */
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H A Dice_lib.c1 // SPDX-License-Identifier: GPL-2.0
14 * ice_vsi_type_str - maps VSI type enum to string equivalents
38 * ice_vsi_ctrl_all_rx_rings - Start or stop a VSI's Rx rings
55 ice_flush(&vsi->back->hw); in ice_vsi_ctrl_all_rx_rings()
67 * ice_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the VSI
75 struct ice_pf *pf = vsi->back; in ice_vsi_alloc_arrays()
79 if (vsi->type == ICE_VSI_CHNL) in ice_vsi_alloc_arrays()
82 /* allocate memory for both Tx and Rx ring pointers */ in ice_vsi_alloc_arrays()
83 vsi->tx_rings = devm_kcalloc(dev, vsi->alloc_txq, in ice_vsi_alloc_arrays()
84 sizeof(*vsi->tx_rings), GFP_KERNEL); in ice_vsi_alloc_arrays()
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/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Dstmmac_platform.c1 // SPDX-License-Identifier: GPL-2.0-only
5 Copyright (C) 2007-2011 STMicroelectronics Ltd
26 * dwmac1000_validate_mcast_bins - validates the number of Multicast filter bins
57 * dwmac1000_validate_ucast_entries - validate the Unicast address entries
88 * stmmac_axi_setup - parse DT parameters for programming the AXI register
91 * if required, from device-tree the AXI internal register can be tuned
99 np = of_parse_phandle(pdev->dev.of_node, "snps,axi-config", 0); in stmmac_axi_setup()
103 axi = devm_kzalloc(&pdev->dev, sizeof(*axi), GFP_KERNEL); in stmmac_axi_setup()
106 return ERR_PTR(-ENOMEM); in stmmac_axi_setup()
109 axi->axi_lpi_en = of_property_read_bool(np, "snps,lpi_en"); in stmmac_axi_setup()
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/openbmc/linux/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/
H A Doverview.rst16 DPAA2 is a hardware architecture designed for high-speeed network
23 DPAA2 hardware resources. The MC provides an object-based abstraction for
25 The MC uses DPAA2 hardware resources such as queues, buffer pools, and
28 The MC provides memory-mapped I/O command interfaces (MC portals)
34 +--------------------------------------+
38 +-----------------------------|--------+
41 | config,use,destroy)
44 +------------------------| mc portal |-+
46 | +- - - - - - - - - - - - -V- - -+ |
50 | +- - - - - - - - - - - - - - - -+ |
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/openbmc/u-boot/arch/arm/dts/
H A Dkeystone-k2hk-netcp.dtsi12 compatible = "ti,keystone-navigator-qmss";
13 dma-coherent;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 queue-range = <0 0x4000>;
23 #address-cells = <1>;
24 #size-cells = <1>;
27 managed-queues = <0 0x2000>;
34 reg-names = "peek", "status", "config",
39 managed-queues = <0x2000 0x2000>;
[all …]
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drv1126.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rv1126-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rockchip,rv1126-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
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/openbmc/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2hk-netcp.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 queue-range = <0 0x4000>;
20 #address-cells = <1>;
21 #size-cells = <1>;
24 managed-queues = <0 0x2000>;
[all …]
/openbmc/linux/drivers/net/ethernet/cavium/thunder/
H A Dnicvf_main.c1 // SPDX-License-Identifier: GPL-2.0-only
37 #define MAX_XDP_MTU (1530 - ETH_HLEN - VLAN_HLEN * 2)
77 if (nic->sqs_mode) in nicvf_netdev_qidx()
78 return qidx + ((nic->sqs_id + 1) * MAX_CMP_QUEUES_PER_QS); in nicvf_netdev_qidx()
95 writeq_relaxed(val, nic->reg_base + offset); in nicvf_reg_write()
100 return readq_relaxed(nic->reg_base + offset); in nicvf_reg_read()
106 void __iomem *addr = nic->reg_base + offset; in nicvf_queue_reg_write()
113 void __iomem *addr = nic->reg_base + offset; in nicvf_queue_reg_read()
118 /* VF -> PF mailbox communication */
132 mutex_lock(&nic->rx_mode_mtx); in nicvf_send_msg_to_pf()
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/openbmc/linux/drivers/net/ethernet/cavium/liquidio/
H A Docteon_config.h7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
25 /*--------------------------CONFIG VALUES------------------------*/
120 /* Macros to get octeon config params */
121 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq)
122 #define CFG_GET_IQ_MAX_Q(cfg) ((cfg)->iq.max_iqs)
123 #define CFG_GET_IQ_PENDING_LIST_SIZE(cfg) ((cfg)->iq.pending_list_size)
124 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type)
125 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min)
126 #define CFG_GET_IQ_DB_TIMEOUT(cfg) ((cfg)->iq.db_timeout)
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/openbmc/linux/drivers/net/wireless/intel/iwlegacy/
H A D4965.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
8 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 /* tx queue */
56 /* tx */
79 * Acquire il->lock before calling this function !
83 * il4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
84 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
87 * NOTE: Acquire il->lock before calling this function !
181 * The first queue used for block-ack aggregation is #7 (4965 only).
[all …]
/openbmc/linux/drivers/net/ethernet/freescale/
H A Dfec.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC
8 * (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
9 * (C) Copyright 2000-2001, Lineo (www.lineo.com)
23 #include <dt-bindings/firmware/imx/rsrc.h>
48 #define FEC_TXIC0 0x0f0 /* Tx Interrupt Coalescing for ring 0 */
49 #define FEC_TXIC1 0x0f4 /* Tx Interrupt Coalescing for ring 1 */
50 #define FEC_TXIC2 0x0f8 /* Tx Interrupt Coalescing for ring 2 */
81 #define FEC_X_DES_ACTIVE_1 0x1e4 /* Tx descriptor active for ring 1 */
83 #define FEC_X_DES_ACTIVE_2 0x1ec /* Tx descriptor active for ring 2 */
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