1 /* SPDX-License-Identifier: GPL-2.0 */
2 /****************************************************************************/
3 
4 /*
5  *	fec.h  --  Fast Ethernet Controller for Motorola ColdFire SoC
6  *		   processors.
7  *
8  *	(C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
9  *	(C) Copyright 2000-2001, Lineo (www.lineo.com)
10  */
11 
12 /****************************************************************************/
13 #ifndef FEC_H
14 #define	FEC_H
15 /****************************************************************************/
16 
17 #include <linux/clocksource.h>
18 #include <linux/net_tstamp.h>
19 #include <linux/pm_qos.h>
20 #include <linux/bpf.h>
21 #include <linux/ptp_clock_kernel.h>
22 #include <linux/timecounter.h>
23 #include <dt-bindings/firmware/imx/rsrc.h>
24 #include <linux/firmware/imx/sci.h>
25 #include <net/xdp.h>
26 
27 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
28     defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
29     defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
30 /*
31  *	Just figures, Motorola would have to change the offsets for
32  *	registers in the same peripheral device on different models
33  *	of the ColdFire!
34  */
35 #define FEC_IEVENT		0x004 /* Interrupt event reg */
36 #define FEC_IMASK		0x008 /* Interrupt mask reg */
37 #define FEC_R_DES_ACTIVE_0	0x010 /* Receive descriptor reg */
38 #define FEC_X_DES_ACTIVE_0	0x014 /* Transmit descriptor reg */
39 #define FEC_ECNTRL		0x024 /* Ethernet control reg */
40 #define FEC_MII_DATA		0x040 /* MII manage frame reg */
41 #define FEC_MII_SPEED		0x044 /* MII speed control reg */
42 #define FEC_MIB_CTRLSTAT	0x064 /* MIB control/status reg */
43 #define FEC_R_CNTRL		0x084 /* Receive control reg */
44 #define FEC_X_CNTRL		0x0c4 /* Transmit Control reg */
45 #define FEC_ADDR_LOW		0x0e4 /* Low 32bits MAC address */
46 #define FEC_ADDR_HIGH		0x0e8 /* High 16bits MAC address */
47 #define FEC_OPD			0x0ec /* Opcode + Pause duration */
48 #define FEC_TXIC0		0x0f0 /* Tx Interrupt Coalescing for ring 0 */
49 #define FEC_TXIC1		0x0f4 /* Tx Interrupt Coalescing for ring 1 */
50 #define FEC_TXIC2		0x0f8 /* Tx Interrupt Coalescing for ring 2 */
51 #define FEC_RXIC0		0x100 /* Rx Interrupt Coalescing for ring 0 */
52 #define FEC_RXIC1		0x104 /* Rx Interrupt Coalescing for ring 1 */
53 #define FEC_RXIC2		0x108 /* Rx Interrupt Coalescing for ring 2 */
54 #define FEC_HASH_TABLE_HIGH	0x118 /* High 32bits hash table */
55 #define FEC_HASH_TABLE_LOW	0x11c /* Low 32bits hash table */
56 #define FEC_GRP_HASH_TABLE_HIGH	0x120 /* High 32bits hash table */
57 #define FEC_GRP_HASH_TABLE_LOW	0x124 /* Low 32bits hash table */
58 #define FEC_X_WMRK		0x144 /* FIFO transmit water mark */
59 #define FEC_R_BOUND		0x14c /* FIFO receive bound reg */
60 #define FEC_R_FSTART		0x150 /* FIFO receive start reg */
61 #define FEC_R_DES_START_1	0x160 /* Receive descriptor ring 1 */
62 #define FEC_X_DES_START_1	0x164 /* Transmit descriptor ring 1 */
63 #define FEC_R_BUFF_SIZE_1	0x168 /* Maximum receive buff ring1 size */
64 #define FEC_R_DES_START_2	0x16c /* Receive descriptor ring 2 */
65 #define FEC_X_DES_START_2	0x170 /* Transmit descriptor ring 2 */
66 #define FEC_R_BUFF_SIZE_2	0x174 /* Maximum receive buff ring2 size */
67 #define FEC_R_DES_START_0	0x180 /* Receive descriptor ring */
68 #define FEC_X_DES_START_0	0x184 /* Transmit descriptor ring */
69 #define FEC_R_BUFF_SIZE_0	0x188 /* Maximum receive buff size */
70 #define FEC_R_FIFO_RSFL		0x190 /* Receive FIFO section full threshold */
71 #define FEC_R_FIFO_RSEM		0x194 /* Receive FIFO section empty threshold */
72 #define FEC_R_FIFO_RAEM		0x198 /* Receive FIFO almost empty threshold */
73 #define FEC_R_FIFO_RAFL		0x19c /* Receive FIFO almost full threshold */
74 #define FEC_FTRL		0x1b0 /* Frame truncation receive length*/
75 #define FEC_RACC		0x1c4 /* Receive Accelerator function */
76 #define FEC_RCMR_1		0x1c8 /* Receive classification match ring 1 */
77 #define FEC_RCMR_2		0x1cc /* Receive classification match ring 2 */
78 #define FEC_DMA_CFG_1		0x1d8 /* DMA class configuration for ring 1 */
79 #define FEC_DMA_CFG_2		0x1dc /* DMA class Configuration for ring 2 */
80 #define FEC_R_DES_ACTIVE_1	0x1e0 /* Rx descriptor active for ring 1 */
81 #define FEC_X_DES_ACTIVE_1	0x1e4 /* Tx descriptor active for ring 1 */
82 #define FEC_R_DES_ACTIVE_2	0x1e8 /* Rx descriptor active for ring 2 */
83 #define FEC_X_DES_ACTIVE_2	0x1ec /* Tx descriptor active for ring 2 */
84 #define FEC_QOS_SCHEME		0x1f0 /* Set multi queues Qos scheme */
85 #define FEC_LPI_SLEEP		0x1f4 /* Set IEEE802.3az LPI Sleep Ts time */
86 #define FEC_LPI_WAKE		0x1f8 /* Set IEEE802.3az LPI Wake Tw time */
87 #define FEC_MIIGSK_CFGR		0x300 /* MIIGSK Configuration reg */
88 #define FEC_MIIGSK_ENR		0x308 /* MIIGSK Enable reg */
89 
90 #define BM_MIIGSK_CFGR_MII		0x00
91 #define BM_MIIGSK_CFGR_RMII		0x01
92 #define BM_MIIGSK_CFGR_FRCONT_10M	0x40
93 
94 #define RMON_T_DROP		0x200 /* Count of frames not cntd correctly */
95 #define RMON_T_PACKETS		0x204 /* RMON TX packet count */
96 #define RMON_T_BC_PKT		0x208 /* RMON TX broadcast pkts */
97 #define RMON_T_MC_PKT		0x20c /* RMON TX multicast pkts */
98 #define RMON_T_CRC_ALIGN	0x210 /* RMON TX pkts with CRC align err */
99 #define RMON_T_UNDERSIZE	0x214 /* RMON TX pkts < 64 bytes, good CRC */
100 #define RMON_T_OVERSIZE		0x218 /* RMON TX pkts > MAX_FL bytes good CRC */
101 #define RMON_T_FRAG		0x21c /* RMON TX pkts < 64 bytes, bad CRC */
102 #define RMON_T_JAB		0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */
103 #define RMON_T_COL		0x224 /* RMON TX collision count */
104 #define RMON_T_P64		0x228 /* RMON TX 64 byte pkts */
105 #define RMON_T_P65TO127		0x22c /* RMON TX 65 to 127 byte pkts */
106 #define RMON_T_P128TO255	0x230 /* RMON TX 128 to 255 byte pkts */
107 #define RMON_T_P256TO511	0x234 /* RMON TX 256 to 511 byte pkts */
108 #define RMON_T_P512TO1023	0x238 /* RMON TX 512 to 1023 byte pkts */
109 #define RMON_T_P1024TO2047	0x23c /* RMON TX 1024 to 2047 byte pkts */
110 #define RMON_T_P_GTE2048	0x240 /* RMON TX pkts > 2048 bytes */
111 #define RMON_T_OCTETS		0x244 /* RMON TX octets */
112 #define IEEE_T_DROP		0x248 /* Count of frames not counted crtly */
113 #define IEEE_T_FRAME_OK		0x24c /* Frames tx'd OK */
114 #define IEEE_T_1COL		0x250 /* Frames tx'd with single collision */
115 #define IEEE_T_MCOL		0x254 /* Frames tx'd with multiple collision */
116 #define IEEE_T_DEF		0x258 /* Frames tx'd after deferral delay */
117 #define IEEE_T_LCOL		0x25c /* Frames tx'd with late collision */
118 #define IEEE_T_EXCOL		0x260 /* Frames tx'd with excesv collisions */
119 #define IEEE_T_MACERR		0x264 /* Frames tx'd with TX FIFO underrun */
120 #define IEEE_T_CSERR		0x268 /* Frames tx'd with carrier sense err */
121 #define IEEE_T_SQE		0x26c /* Frames tx'd with SQE err */
122 #define IEEE_T_FDXFC		0x270 /* Flow control pause frames tx'd */
123 #define IEEE_T_OCTETS_OK	0x274 /* Octet count for frames tx'd w/o err */
124 #define RMON_R_PACKETS		0x284 /* RMON RX packet count */
125 #define RMON_R_BC_PKT		0x288 /* RMON RX broadcast pkts */
126 #define RMON_R_MC_PKT		0x28c /* RMON RX multicast pkts */
127 #define RMON_R_CRC_ALIGN	0x290 /* RMON RX pkts with CRC alignment err */
128 #define RMON_R_UNDERSIZE	0x294 /* RMON RX pkts < 64 bytes, good CRC */
129 #define RMON_R_OVERSIZE		0x298 /* RMON RX pkts > MAX_FL bytes good CRC */
130 #define RMON_R_FRAG		0x29c /* RMON RX pkts < 64 bytes, bad CRC */
131 #define RMON_R_JAB		0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */
132 #define RMON_R_RESVD_O		0x2a4 /* Reserved */
133 #define RMON_R_P64		0x2a8 /* RMON RX 64 byte pkts */
134 #define RMON_R_P65TO127		0x2ac /* RMON RX 65 to 127 byte pkts */
135 #define RMON_R_P128TO255	0x2b0 /* RMON RX 128 to 255 byte pkts */
136 #define RMON_R_P256TO511	0x2b4 /* RMON RX 256 to 511 byte pkts */
137 #define RMON_R_P512TO1023	0x2b8 /* RMON RX 512 to 1023 byte pkts */
138 #define RMON_R_P1024TO2047	0x2bc /* RMON RX 1024 to 2047 byte pkts */
139 #define RMON_R_P_GTE2048	0x2c0 /* RMON RX pkts > 2048 bytes */
140 #define RMON_R_OCTETS		0x2c4 /* RMON RX octets */
141 #define IEEE_R_DROP		0x2c8 /* Count frames not counted correctly */
142 #define IEEE_R_FRAME_OK		0x2cc /* Frames rx'd OK */
143 #define IEEE_R_CRC		0x2d0 /* Frames rx'd with CRC err */
144 #define IEEE_R_ALIGN		0x2d4 /* Frames rx'd with alignment err */
145 #define IEEE_R_MACERR		0x2d8 /* Receive FIFO overflow count */
146 #define IEEE_R_FDXFC		0x2dc /* Flow control pause frames rx'd */
147 #define IEEE_R_OCTETS_OK	0x2e0 /* Octet cnt for frames rx'd w/o err */
148 
149 #else
150 
151 #define FEC_ECNTRL		0x000 /* Ethernet control reg */
152 #define FEC_IEVENT		0x004 /* Interrupt even reg */
153 #define FEC_IMASK		0x008 /* Interrupt mask reg */
154 #define FEC_IVEC		0x00c /* Interrupt vec status reg */
155 #define FEC_R_DES_ACTIVE_0	0x010 /* Receive descriptor reg */
156 #define FEC_R_DES_ACTIVE_1	FEC_R_DES_ACTIVE_0
157 #define FEC_R_DES_ACTIVE_2	FEC_R_DES_ACTIVE_0
158 #define FEC_X_DES_ACTIVE_0	0x014 /* Transmit descriptor reg */
159 #define FEC_X_DES_ACTIVE_1	FEC_X_DES_ACTIVE_0
160 #define FEC_X_DES_ACTIVE_2	FEC_X_DES_ACTIVE_0
161 #define FEC_MII_DATA		0x040 /* MII manage frame reg */
162 #define FEC_MII_SPEED		0x044 /* MII speed control reg */
163 #define FEC_R_BOUND		0x08c /* FIFO receive bound reg */
164 #define FEC_R_FSTART		0x090 /* FIFO receive start reg */
165 #define FEC_X_WMRK		0x0a4 /* FIFO transmit water mark */
166 #define FEC_X_FSTART		0x0ac /* FIFO transmit start reg */
167 #define FEC_R_CNTRL		0x104 /* Receive control reg */
168 #define FEC_MAX_FRM_LEN		0x108 /* Maximum frame length reg */
169 #define FEC_X_CNTRL		0x144 /* Transmit Control reg */
170 #define FEC_ADDR_LOW		0x3c0 /* Low 32bits MAC address */
171 #define FEC_ADDR_HIGH		0x3c4 /* High 16bits MAC address */
172 #define FEC_GRP_HASH_TABLE_HIGH	0x3c8 /* High 32bits hash table */
173 #define FEC_GRP_HASH_TABLE_LOW	0x3cc /* Low 32bits hash table */
174 #define FEC_R_DES_START_0	0x3d0 /* Receive descriptor ring */
175 #define FEC_R_DES_START_1	FEC_R_DES_START_0
176 #define FEC_R_DES_START_2	FEC_R_DES_START_0
177 #define FEC_X_DES_START_0	0x3d4 /* Transmit descriptor ring */
178 #define FEC_X_DES_START_1	FEC_X_DES_START_0
179 #define FEC_X_DES_START_2	FEC_X_DES_START_0
180 #define FEC_R_BUFF_SIZE_0	0x3d8 /* Maximum receive buff size */
181 #define FEC_R_BUFF_SIZE_1	FEC_R_BUFF_SIZE_0
182 #define FEC_R_BUFF_SIZE_2	FEC_R_BUFF_SIZE_0
183 #define FEC_FIFO_RAM		0x400 /* FIFO RAM buffer */
184 /* Not existed in real chip
185  * Just for pass build.
186  */
187 #define FEC_RCMR_1		0xfff
188 #define FEC_RCMR_2		0xfff
189 #define FEC_DMA_CFG_1		0xfff
190 #define FEC_DMA_CFG_2		0xfff
191 #define FEC_TXIC0		0xfff
192 #define FEC_TXIC1		0xfff
193 #define FEC_TXIC2		0xfff
194 #define FEC_RXIC0		0xfff
195 #define FEC_RXIC1		0xfff
196 #define FEC_RXIC2		0xfff
197 #define FEC_LPI_SLEEP		0xfff
198 #define FEC_LPI_WAKE		0xfff
199 #endif /* CONFIG_M5272 */
200 
201 
202 /*
203  *	Define the buffer descriptor structure.
204  *
205  *	Evidently, ARM SoCs have the FEC block generated in a
206  *	little endian mode so adjust endianness accordingly.
207  */
208 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
209 #define fec32_to_cpu le32_to_cpu
210 #define fec16_to_cpu le16_to_cpu
211 #define cpu_to_fec32 cpu_to_le32
212 #define cpu_to_fec16 cpu_to_le16
213 #define __fec32 __le32
214 #define __fec16 __le16
215 
216 struct bufdesc {
217 	__fec16 cbd_datlen;	/* Data length */
218 	__fec16 cbd_sc;		/* Control and status info */
219 	__fec32 cbd_bufaddr;	/* Buffer address */
220 };
221 #else
222 #define fec32_to_cpu be32_to_cpu
223 #define fec16_to_cpu be16_to_cpu
224 #define cpu_to_fec32 cpu_to_be32
225 #define cpu_to_fec16 cpu_to_be16
226 #define __fec32 __be32
227 #define __fec16 __be16
228 
229 struct bufdesc {
230 	__fec16	cbd_sc;		/* Control and status info */
231 	__fec16	cbd_datlen;	/* Data length */
232 	__fec32	cbd_bufaddr;	/* Buffer address */
233 };
234 #endif
235 
236 struct bufdesc_ex {
237 	struct bufdesc desc;
238 	__fec32 cbd_esc;
239 	__fec32 cbd_prot;
240 	__fec32 cbd_bdu;
241 	__fec32 ts;
242 	__fec16 res0[4];
243 };
244 
245 /*
246  *	The following definitions courtesy of commproc.h, which where
247  *	Copyright (c) 1997 Dan Malek (dmalek@jlc.net).
248  */
249 #define BD_SC_EMPTY	((ushort)0x8000)	/* Receive is empty */
250 #define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
251 #define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
252 #define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
253 #define BD_SC_CM	((ushort)0x0200)	/* Continuous mode */
254 #define BD_SC_ID	((ushort)0x0100)	/* Rec'd too many idles */
255 #define BD_SC_P		((ushort)0x0100)	/* xmt preamble */
256 #define BD_SC_BR	((ushort)0x0020)	/* Break received */
257 #define BD_SC_FR	((ushort)0x0010)	/* Framing error */
258 #define BD_SC_PR	((ushort)0x0008)	/* Parity error */
259 #define BD_SC_OV	((ushort)0x0002)	/* Overrun */
260 #define BD_SC_CD	((ushort)0x0001)	/* ?? */
261 
262 /* Buffer descriptor control/status used by Ethernet receive.
263  */
264 #define BD_ENET_RX_EMPTY	((ushort)0x8000)
265 #define BD_ENET_RX_WRAP		((ushort)0x2000)
266 #define BD_ENET_RX_INTR		((ushort)0x1000)
267 #define BD_ENET_RX_LAST		((ushort)0x0800)
268 #define BD_ENET_RX_FIRST	((ushort)0x0400)
269 #define BD_ENET_RX_MISS		((ushort)0x0100)
270 #define BD_ENET_RX_LG		((ushort)0x0020)
271 #define BD_ENET_RX_NO		((ushort)0x0010)
272 #define BD_ENET_RX_SH		((ushort)0x0008)
273 #define BD_ENET_RX_CR		((ushort)0x0004)
274 #define BD_ENET_RX_OV		((ushort)0x0002)
275 #define BD_ENET_RX_CL		((ushort)0x0001)
276 #define BD_ENET_RX_STATS	((ushort)0x013f)	/* All status bits */
277 
278 /* Enhanced buffer descriptor control/status used by Ethernet receive */
279 #define BD_ENET_RX_VLAN		0x00000004
280 
281 /* Buffer descriptor control/status used by Ethernet transmit.
282  */
283 #define BD_ENET_TX_READY	((ushort)0x8000)
284 #define BD_ENET_TX_PAD		((ushort)0x4000)
285 #define BD_ENET_TX_WRAP		((ushort)0x2000)
286 #define BD_ENET_TX_INTR		((ushort)0x1000)
287 #define BD_ENET_TX_LAST		((ushort)0x0800)
288 #define BD_ENET_TX_TC		((ushort)0x0400)
289 #define BD_ENET_TX_DEF		((ushort)0x0200)
290 #define BD_ENET_TX_HB		((ushort)0x0100)
291 #define BD_ENET_TX_LC		((ushort)0x0080)
292 #define BD_ENET_TX_RL		((ushort)0x0040)
293 #define BD_ENET_TX_RCMASK	((ushort)0x003c)
294 #define BD_ENET_TX_UN		((ushort)0x0002)
295 #define BD_ENET_TX_CSL		((ushort)0x0001)
296 #define BD_ENET_TX_STATS	((ushort)0x0fff)	/* All status bits */
297 
298 /* enhanced buffer descriptor control/status used by Ethernet transmit */
299 #define BD_ENET_TX_INT		0x40000000
300 #define BD_ENET_TX_TS		0x20000000
301 #define BD_ENET_TX_PINS		0x10000000
302 #define BD_ENET_TX_IINS		0x08000000
303 
304 
305 /* This device has up to three irqs on some platforms */
306 #define FEC_IRQ_NUM		3
307 
308 /* Maximum number of queues supported
309  * ENET with AVB IP can support up to 3 independent tx queues and rx queues.
310  * User can point the queue number that is less than or equal to 3.
311  */
312 #define FEC_ENET_MAX_TX_QS	3
313 #define FEC_ENET_MAX_RX_QS	3
314 
315 #define FEC_R_DES_START(X)	(((X) == 1) ? FEC_R_DES_START_1 : \
316 				(((X) == 2) ? \
317 					FEC_R_DES_START_2 : FEC_R_DES_START_0))
318 #define FEC_X_DES_START(X)	(((X) == 1) ? FEC_X_DES_START_1 : \
319 				(((X) == 2) ? \
320 					FEC_X_DES_START_2 : FEC_X_DES_START_0))
321 #define FEC_R_BUFF_SIZE(X)	(((X) == 1) ? FEC_R_BUFF_SIZE_1 : \
322 				(((X) == 2) ? \
323 					FEC_R_BUFF_SIZE_2 : FEC_R_BUFF_SIZE_0))
324 
325 #define FEC_DMA_CFG(X)		(((X) == 2) ? FEC_DMA_CFG_2 : FEC_DMA_CFG_1)
326 
327 #define DMA_CLASS_EN		(1 << 16)
328 #define FEC_RCMR(X)		(((X) == 2) ? FEC_RCMR_2 : FEC_RCMR_1)
329 #define IDLE_SLOPE_MASK		0xffff
330 #define IDLE_SLOPE_1		0x200 /* BW fraction: 0.5 */
331 #define IDLE_SLOPE_2		0x200 /* BW fraction: 0.5 */
332 #define IDLE_SLOPE(X)		(((X) == 1) ?				\
333 				(IDLE_SLOPE_1 & IDLE_SLOPE_MASK) :	\
334 				(IDLE_SLOPE_2 & IDLE_SLOPE_MASK))
335 #define RCMR_MATCHEN		(0x1 << 16)
336 #define RCMR_CMP_CFG(v, n)	(((v) & 0x7) <<  (n << 2))
337 #define RCMR_CMP_1		(RCMR_CMP_CFG(0, 0) | RCMR_CMP_CFG(1, 1) | \
338 				RCMR_CMP_CFG(2, 2) | RCMR_CMP_CFG(3, 3))
339 #define RCMR_CMP_2		(RCMR_CMP_CFG(4, 0) | RCMR_CMP_CFG(5, 1) | \
340 				RCMR_CMP_CFG(6, 2) | RCMR_CMP_CFG(7, 3))
341 #define RCMR_CMP(X)		(((X) == 1) ? RCMR_CMP_1 : RCMR_CMP_2)
342 #define FEC_TX_BD_FTYPE(X)	(((X) & 0xf) << 20)
343 
344 /* The number of Tx and Rx buffers.  These are allocated from the page
345  * pool.  The code may assume these are power of two, so it it best
346  * to keep them that size.
347  * We don't need to allocate pages for the transmitter.  We just use
348  * the skbuffer directly.
349  */
350 
351 #define FEC_ENET_XDP_HEADROOM	(XDP_PACKET_HEADROOM)
352 #define FEC_ENET_RX_PAGES	256
353 #define FEC_ENET_RX_FRSIZE	(PAGE_SIZE - FEC_ENET_XDP_HEADROOM \
354 		- SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
355 #define FEC_ENET_RX_FRPPG	(PAGE_SIZE / FEC_ENET_RX_FRSIZE)
356 #define RX_RING_SIZE		(FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
357 #define FEC_ENET_TX_FRSIZE	2048
358 #define FEC_ENET_TX_FRPPG	(PAGE_SIZE / FEC_ENET_TX_FRSIZE)
359 #define TX_RING_SIZE		1024	/* Must be power of two */
360 #define TX_RING_MOD_MASK	511	/*   for this to work */
361 
362 #define BD_ENET_RX_INT		0x00800000
363 #define BD_ENET_RX_PTP		((ushort)0x0400)
364 #define BD_ENET_RX_ICE		0x00000020
365 #define BD_ENET_RX_PCR		0x00000010
366 #define FLAG_RX_CSUM_ENABLED	(BD_ENET_RX_ICE | BD_ENET_RX_PCR)
367 #define FLAG_RX_CSUM_ERROR	(BD_ENET_RX_ICE | BD_ENET_RX_PCR)
368 
369 /* Interrupt events/masks. */
370 #define FEC_ENET_HBERR  ((uint)0x80000000)      /* Heartbeat error */
371 #define FEC_ENET_BABR   ((uint)0x40000000)      /* Babbling receiver */
372 #define FEC_ENET_BABT   ((uint)0x20000000)      /* Babbling transmitter */
373 #define FEC_ENET_GRA    ((uint)0x10000000)      /* Graceful stop complete */
374 #define FEC_ENET_TXF_0	((uint)0x08000000)	/* Full frame transmitted */
375 #define FEC_ENET_TXF_1	((uint)0x00000008)	/* Full frame transmitted */
376 #define FEC_ENET_TXF_2	((uint)0x00000080)	/* Full frame transmitted */
377 #define FEC_ENET_TXB    ((uint)0x04000000)      /* A buffer was transmitted */
378 #define FEC_ENET_RXF_0	((uint)0x02000000)	/* Full frame received */
379 #define FEC_ENET_RXF_1	((uint)0x00000002)	/* Full frame received */
380 #define FEC_ENET_RXF_2	((uint)0x00000020)	/* Full frame received */
381 #define FEC_ENET_RXB    ((uint)0x01000000)      /* A buffer was received */
382 #define FEC_ENET_MII    ((uint)0x00800000)      /* MII interrupt */
383 #define FEC_ENET_EBERR  ((uint)0x00400000)      /* SDMA bus error */
384 #define FEC_ENET_WAKEUP	((uint)0x00020000)	/* Wakeup request */
385 #define FEC_ENET_TXF	(FEC_ENET_TXF_0 | FEC_ENET_TXF_1 | FEC_ENET_TXF_2)
386 #define FEC_ENET_RXF	(FEC_ENET_RXF_0 | FEC_ENET_RXF_1 | FEC_ENET_RXF_2)
387 #define FEC_ENET_RXF_GET(X)	(((X) == 0) ? FEC_ENET_RXF_0 :	\
388 				(((X) == 1) ? FEC_ENET_RXF_1 :	\
389 				FEC_ENET_RXF_2))
390 #define FEC_ENET_TS_AVAIL       ((uint)0x00010000)
391 #define FEC_ENET_TS_TIMER       ((uint)0x00008000)
392 
393 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF)
394 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
395 
396 #define FEC_ENET_TXC_DLY	((uint)0x00010000)
397 #define FEC_ENET_RXC_DLY	((uint)0x00020000)
398 
399 /* ENET interrupt coalescing macro define */
400 #define FEC_ITR_CLK_SEL		(0x1 << 30)
401 #define FEC_ITR_EN		(0x1 << 31)
402 #define FEC_ITR_ICFT(X)		(((X) & 0xff) << 20)
403 #define FEC_ITR_ICTT(X)		((X) & 0xffff)
404 #define FEC_ITR_ICFT_DEFAULT	200  /* Set 200 frame count threshold */
405 #define FEC_ITR_ICTT_DEFAULT	1000 /* Set 1000us timer threshold */
406 
407 #define FEC_VLAN_TAG_LEN	0x04
408 #define FEC_ETHTYPE_LEN		0x02
409 
410 /* Controller is ENET-MAC */
411 #define FEC_QUIRK_ENET_MAC		(1 << 0)
412 /* Controller needs driver to swap frame */
413 #define FEC_QUIRK_SWAP_FRAME		(1 << 1)
414 /* Controller uses gasket */
415 #define FEC_QUIRK_USE_GASKET		(1 << 2)
416 /* Controller has GBIT support */
417 #define FEC_QUIRK_HAS_GBIT		(1 << 3)
418 /* Controller has extend desc buffer */
419 #define FEC_QUIRK_HAS_BUFDESC_EX	(1 << 4)
420 /* Controller has hardware checksum support */
421 #define FEC_QUIRK_HAS_CSUM		(1 << 5)
422 /* Controller has hardware vlan support */
423 #define FEC_QUIRK_HAS_VLAN		(1 << 6)
424 /* ENET IP errata ERR006358
425  *
426  * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
427  * detected as not set during a prior frame transmission, then the
428  * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
429  * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
430  * frames not being transmitted until there is a 0-to-1 transition on
431  * ENET_TDAR[TDAR].
432  */
433 #define FEC_QUIRK_ERR006358		(1 << 7)
434 /* ENET IP hw AVB
435  *
436  * i.MX6SX ENET IP add Audio Video Bridging (AVB) feature support.
437  * - Two class indicators on receive with configurable priority
438  * - Two class indicators and line speed timer on transmit allowing
439  *   implementation class credit based shapers externally
440  * - Additional DMA registers provisioned to allow managing up to 3
441  *   independent rings
442  */
443 #define FEC_QUIRK_HAS_AVB		(1 << 8)
444 /* There is a TDAR race condition for mutliQ when the software sets TDAR
445  * and the UDMA clears TDAR simultaneously or in a small window (2-4 cycles).
446  * This will cause the udma_tx and udma_tx_arbiter state machines to hang.
447  * The issue exist at i.MX6SX enet IP.
448  */
449 #define FEC_QUIRK_ERR007885		(1 << 9)
450 /* ENET Block Guide/ Chapter for the iMX6SX (PELE) address one issue:
451  * After set ENET_ATCR[Capture], there need some time cycles before the counter
452  * value is capture in the register clock domain.
453  * The wait-time-cycles is at least 6 clock cycles of the slower clock between
454  * the register clock and the 1588 clock. The 1588 ts_clk is fixed to 25Mhz,
455  * register clock is 66Mhz, so the wait-time-cycles must be greater than 240ns
456  * (40ns * 6).
457  */
458 #define FEC_QUIRK_BUG_CAPTURE		(1 << 10)
459 /* Controller has only one MDIO bus */
460 #define FEC_QUIRK_SINGLE_MDIO		(1 << 11)
461 /* Controller supports RACC register */
462 #define FEC_QUIRK_HAS_RACC		(1 << 12)
463 /* Controller supports interrupt coalesc */
464 #define FEC_QUIRK_HAS_COALESCE		(1 << 13)
465 /* Interrupt doesn't wake CPU from deep idle */
466 #define FEC_QUIRK_ERR006687		(1 << 14)
467 /* The MIB counters should be cleared and enabled during
468  * initialisation.
469  */
470 #define FEC_QUIRK_MIB_CLEAR		(1 << 15)
471 /* Only i.MX25/i.MX27/i.MX28 controller supports FRBR,FRSR registers,
472  * those FIFO receive registers are resolved in other platforms.
473  */
474 #define FEC_QUIRK_HAS_FRREG		(1 << 16)
475 
476 /* Some FEC hardware blocks need the MMFR cleared at setup time to avoid
477  * the generation of an MII event. This must be avoided in the older
478  * FEC blocks where it will stop MII events being generated.
479  */
480 #define FEC_QUIRK_CLEAR_SETUP_MII	(1 << 17)
481 
482 /* Some link partners do not tolerate the momentary reset of the REF_CLK
483  * frequency when the RNCTL register is cleared by hardware reset.
484  */
485 #define FEC_QUIRK_NO_HARD_RESET		(1 << 18)
486 
487 /* i.MX6SX ENET IP supports multiple queues (3 queues), use this quirk to
488  * represents this ENET IP.
489  */
490 #define FEC_QUIRK_HAS_MULTI_QUEUES	(1 << 19)
491 
492 /* i.MX8MQ ENET IP version add new feature to support IEEE 802.3az EEE
493  * standard. For the transmission, MAC supply two user registers to set
494  * Sleep (TS) and Wake (TW) time.
495  */
496 #define FEC_QUIRK_HAS_EEE		(1 << 20)
497 
498 /* i.MX8QM ENET IP version add new feture to generate delayed TXC/RXC
499  * as an alternative option to make sure it works well with various PHYs.
500  * For the implementation of delayed clock, ENET takes synchronized 250MHz
501  * clocks to generate 2ns delay.
502  */
503 #define FEC_QUIRK_DELAYED_CLKS_SUPPORT	(1 << 21)
504 
505 /* i.MX8MQ SoC integration mix wakeup interrupt signal into "int2" interrupt line. */
506 #define FEC_QUIRK_WAKEUP_FROM_INT2	(1 << 22)
507 
508 /* i.MX6Q adds pm_qos support */
509 #define FEC_QUIRK_HAS_PMQOS			BIT(23)
510 
511 /* Not all FEC hardware block MDIOs support accesses in C45 mode.
512  * Older blocks in the ColdFire parts do not support it.
513  */
514 #define FEC_QUIRK_HAS_MDIO_C45		BIT(24)
515 
516 struct bufdesc_prop {
517 	int qid;
518 	/* Address of Rx and Tx buffers */
519 	struct bufdesc	*base;
520 	struct bufdesc	*last;
521 	struct bufdesc	*cur;
522 	void __iomem	*reg_desc_active;
523 	dma_addr_t	dma;
524 	unsigned short ring_size;
525 	unsigned char dsize;
526 	unsigned char dsize_log2;
527 };
528 
529 struct fec_enet_priv_txrx_info {
530 	int	offset;
531 	struct	page *page;
532 	struct  sk_buff *skb;
533 };
534 
535 enum {
536 	RX_XDP_REDIRECT = 0,
537 	RX_XDP_PASS,
538 	RX_XDP_DROP,
539 	RX_XDP_TX,
540 	RX_XDP_TX_ERRORS,
541 	TX_XDP_XMIT,
542 	TX_XDP_XMIT_ERRORS,
543 
544 	/* The following must be the last one */
545 	XDP_STATS_TOTAL,
546 };
547 
548 enum fec_txbuf_type {
549 	FEC_TXBUF_T_SKB,
550 	FEC_TXBUF_T_XDP_NDO,
551 	FEC_TXBUF_T_XDP_TX,
552 };
553 
554 struct fec_tx_buffer {
555 	void *buf_p;
556 	enum fec_txbuf_type type;
557 };
558 
559 struct fec_enet_priv_tx_q {
560 	struct bufdesc_prop bd;
561 	unsigned char *tx_bounce[TX_RING_SIZE];
562 	struct fec_tx_buffer tx_buf[TX_RING_SIZE];
563 
564 	unsigned short tx_stop_threshold;
565 	unsigned short tx_wake_threshold;
566 
567 	struct bufdesc	*dirty_tx;
568 	char *tso_hdrs;
569 	dma_addr_t tso_hdrs_dma;
570 };
571 
572 struct fec_enet_priv_rx_q {
573 	struct bufdesc_prop bd;
574 	struct  fec_enet_priv_txrx_info rx_skb_info[RX_RING_SIZE];
575 
576 	/* page_pool */
577 	struct page_pool *page_pool;
578 	struct xdp_rxq_info xdp_rxq;
579 	u32 stats[XDP_STATS_TOTAL];
580 
581 	/* rx queue number, in the range 0-7 */
582 	u8 id;
583 };
584 
585 struct fec_stop_mode_gpr {
586 	struct regmap *gpr;
587 	u8 reg;
588 	u8 bit;
589 };
590 
591 /* The FEC buffer descriptors track the ring buffers.  The rx_bd_base and
592  * tx_bd_base always point to the base of the buffer descriptors.  The
593  * cur_rx and cur_tx point to the currently available buffer.
594  * The dirty_tx tracks the current buffer that is being sent by the
595  * controller.  The cur_tx and dirty_tx are equal under both completely
596  * empty and completely full conditions.  The empty/ready indicator in
597  * the buffer descriptor determines the actual condition.
598  */
599 struct fec_enet_private {
600 	/* Hardware registers of the FEC device */
601 	void __iomem *hwp;
602 
603 	struct net_device *netdev;
604 
605 	struct clk *clk_ipg;
606 	struct clk *clk_ahb;
607 	struct clk *clk_ref;
608 	struct clk *clk_enet_out;
609 	struct clk *clk_ptp;
610 	struct clk *clk_2x_txclk;
611 
612 	bool ptp_clk_on;
613 	struct mutex ptp_clk_mutex;
614 	unsigned int num_tx_queues;
615 	unsigned int num_rx_queues;
616 
617 	/* The saved address of a sent-in-place packet/buffer, for skfree(). */
618 	struct fec_enet_priv_tx_q *tx_queue[FEC_ENET_MAX_TX_QS];
619 	struct fec_enet_priv_rx_q *rx_queue[FEC_ENET_MAX_RX_QS];
620 
621 	unsigned int total_tx_ring_size;
622 	unsigned int total_rx_ring_size;
623 
624 	struct	platform_device *pdev;
625 
626 	int	dev_id;
627 
628 	/* Phylib and MDIO interface */
629 	struct	mii_bus *mii_bus;
630 	uint	phy_speed;
631 	phy_interface_t	phy_interface;
632 	struct device_node *phy_node;
633 	bool	rgmii_txc_dly;
634 	bool	rgmii_rxc_dly;
635 	bool	rpm_active;
636 	int	link;
637 	int	full_duplex;
638 	int	speed;
639 	int	irq[FEC_IRQ_NUM];
640 	bool	bufdesc_ex;
641 	int	pause_flag;
642 	int	wol_flag;
643 	int	wake_irq;
644 	u32	quirks;
645 
646 	struct	napi_struct napi;
647 	int	csum_flags;
648 
649 	struct work_struct tx_timeout_work;
650 
651 	struct ptp_clock *ptp_clock;
652 	struct ptp_clock_info ptp_caps;
653 	spinlock_t tmreg_lock;
654 	struct cyclecounter cc;
655 	struct timecounter tc;
656 	u32 cycle_speed;
657 	int hwts_rx_en;
658 	int hwts_tx_en;
659 	struct delayed_work time_keep;
660 	struct regulator *reg_phy;
661 	struct fec_stop_mode_gpr stop_gpr;
662 	struct pm_qos_request pm_qos_req;
663 
664 	unsigned int tx_align;
665 	unsigned int rx_align;
666 
667 	/* hw interrupt coalesce */
668 	unsigned int rx_pkts_itr;
669 	unsigned int rx_time_itr;
670 	unsigned int tx_pkts_itr;
671 	unsigned int tx_time_itr;
672 	unsigned int itr_clk_rate;
673 
674 	/* tx lpi eee mode */
675 	struct ethtool_eee eee;
676 	unsigned int clk_ref_rate;
677 
678 	/* ptp clock period in ns*/
679 	unsigned int ptp_inc;
680 
681 	/* pps  */
682 	int pps_channel;
683 	unsigned int reload_period;
684 	int pps_enable;
685 	unsigned int next_counter;
686 	struct hrtimer perout_timer;
687 	u64 perout_stime;
688 
689 	struct imx_sc_ipc *ipc_handle;
690 
691 	/* XDP BPF Program */
692 	struct bpf_prog *xdp_prog;
693 
694 	u64 ethtool_stats[];
695 };
696 
697 void fec_ptp_init(struct platform_device *pdev, int irq_idx);
698 void fec_ptp_stop(struct platform_device *pdev);
699 void fec_ptp_start_cyclecounter(struct net_device *ndev);
700 int fec_ptp_set(struct net_device *ndev, struct kernel_hwtstamp_config *config,
701 		struct netlink_ext_ack *extack);
702 void fec_ptp_get(struct net_device *ndev, struct kernel_hwtstamp_config *config);
703 
704 /****************************************************************************/
705 #endif /* FEC_H */
706