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/openbmc/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_arria10_socdk_qspi.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
15 compatible = "micron,mt25qu02g", "jedec,spi-nor";
17 spi-max-frequency = <100000000>;
19 m25p,fast-read;
20 cdns,page-size = <256>;
21 cdns,block-size = <16>;
22 cdns,read-delay = <3>;
[all …]
H A Dsocfpga_cyclone5_vining_fpga.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
12 compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga";
16 stdout-path = "serial0:115200n8";
34 gpio-keys {
35 compatible = "gpio-keys";
68 regulator-usb-nrst {
69 compatible = "regulator-fixed";
70 regulator-name = "usb_nrst";
[all …]
H A Dsocfpga_cyclone5_socrates.dts1 // SPDX-License-Identifier: GPL-2.0+
10 compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga";
18 stdout-path = "serial0:115200n8";
27 leds: gpio-leds {
32 phy-mode = "rgmii";
54 compatible = "gpio-leds";
59 linux,default-trigger = "heartbeat";
81 #address-cells = <1>;
82 #size-cells = <1>;
83 compatible = "micron,n25q256a", "jedec,spi-nor";
[all …]
H A Dsocfpga_arria5_socdk.dts1 // SPDX-License-Identifier: GPL-2.0+
10 compatible = "altr,socfpga-arria5-socdk", "altr,socfpga-arria5", "altr,socfpga";
14 stdout-path = "serial0:115200n8";
31 compatible = "gpio-leds";
32 led-hps0 {
37 led-hps1 {
42 led-hps2 {
47 led-hps3 {
54 compatible = "regulator-fixed";
55 regulator-name = "3.3V";
[all …]
H A Dsocfpga_cyclone5_sodia.dts1 // SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
12 compatible = "macnica,sodia", "altr,socfpga-cyclone5", "altr,socfpga";
16 stdout-path = "serial0:115200n8";
30 compatible = "regulator-fixed";
31 regulator-name = "3.3V";
32 regulator-min-microvolt = <3300000>;
33 regulator-max-microvolt = <3300000>;
36 leds: gpio-leds {
[all …]
H A Dsocfpga_cyclone5_socdk.dts1 // SPDX-License-Identifier: GPL-2.0+
10 compatible = "altr,socfpga-cyclone5-socdk", "altr,socfpga-cyclone5", "altr,socfpga";
14 stdout-path = "serial0:115200n8";
31 compatible = "gpio-leds";
32 led-hps0 {
37 led-hps1 {
42 led-hps2 {
47 led-hps3 {
54 compatible = "regulator-fixed";
55 regulator-name = "3.3V";
[all …]
H A Dsocfpga_cyclone5_sockit.dts1 // SPDX-License-Identifier: GPL-2.0+
10 compatible = "terasic,socfpga-cyclone5-sockit", "altr,socfpga-cyclone5", "altr,socfpga";
14 stdout-path = "serial0:115200n8";
31 compatible = "gpio-leds";
36 linux,default-trigger = "heartbeat";
42 linux,default-trigger = "heartbeat";
48 linux,default-trigger = "heartbeat";
54 linux,default-trigger = "heartbeat";
58 gpio-keys {
59 compatible = "gpio-keys";
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsocfpga_cyclone5_vining_fpga.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
12 compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga";
16 stdout-path = "serial0:115200n8";
34 gpio-keys {
35 compatible = "gpio-keys";
56 regulator-usb-nrst {
57 compatible = "regulator-fixed";
58 regulator-name = "usb_nrst";
[all …]
H A Dstv0991.dts1 /dts-v1/;
6 #address-cells = <1>;
7 #size-cells = <1>;
10 stdout-path = &uart0;
29 compatible = "cdns,qspi-nor";
30 #address-cells = <1>;
31 #size-cells = <0>;
35 cdns,fifo-depth = <256>;
36 cdns,fifo-width = <4>;
37 cdns,trigger-address = <0x40000000>;
[all …]
H A Dsocfpga_cyclone5_socrates.dts1 // SPDX-License-Identifier: GPL-2.0+
10 compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga";
18 stdout-path = "serial0:115200n8";
27 leds: gpio-leds {
32 phy-mode = "rgmii";
54 compatible = "gpio-leds";
59 linux,default-trigger = "heartbeat";
79 u-boot,dm-pre-reloc;
82 #address-cells = <1>;
83 #size-cells = <1>;
[all …]
H A Dkeystone-k2g-ice.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
7 /dts-v1/;
9 #include "keystone-k2g.dtsi"
12 compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone";
16 stdout-path = &uart0;
41 compatible = "s25fl256s1", "spi-flash";
43 spi-tx-bus-width = <1>;
44 spi-rx-bus-width = <4>;
45 spi-max-frequency = <96000000>;
[all …]
H A Dsocfpga_cyclone5_sr1500.dts1 // SPDX-License-Identifier: GPL-2.0+
10 compatible = "anonymous,socfpga-sr1500", "altr,socfpga-cyclone5", "altr,socfpga";
14 stdout-path = "serial0:115200n8";
32 u-boot,dm-pre-reloc;
38 phy-mode = "rgmii";
54 bank-name = "porta";
58 bank-name = "portb";
62 bank-name = "portc";
67 speed-mode = <0>;
72 speed-mode = <0>;
[all …]
H A Dsocfpga_cyclone5_is1.dts1 // SPDX-License-Identifier: GPL-2.0+
10 compatible = "anonymous,socfpga-is1", "altr,socfpga-cyclone5", "altr,socfpga";
14 stdout-path = "serial0:115200n8";
28 regulator_3_3v: 3-3-v-regulator {
29 compatible = "regulator-fixed";
30 regulator-name = "3.3V";
31 regulator-min-microvolt = <3300000>;
32 regulator-max-microvolt = <3300000>;
36 u-boot,dm-pre-reloc;
42 phy-mode = "rgmii";
[all …]
H A Dsocfpga_arria5_socdk.dts1 // SPDX-License-Identifier: GPL-2.0+
10 compatible = "altr,socfpga-arria5", "altr,socfpga";
14 stdout-path = "serial0:115200n8";
31 compatible = "gpio-leds";
53 regulator_3_3v: 3-3-v-regulator {
54 compatible = "regulator-fixed";
55 regulator-name = "3.3V";
56 regulator-min-microvolt = <3300000>;
57 regulator-max-microvolt = <3300000>;
63 phy-mode = "rgmii";
[all …]
H A Dkeystone-k2g-evm.dts10 /dts-v1/;
12 #include "keystone-k2g.dtsi"
15 compatible = "ti,k2g-evm","ti,keystone";
19 stdout-path = &uart0;
30 ethphy0: ethernet-phy@0 {
32 phy-mode = "rgmii-id";
42 compatible = "nop-phy";
55 compatible = "nop-phy";
65 phy-handle = <&ethphy0>;
76 #address-cells = <1>;
[all …]
H A Dsocfpga_cyclone5_socdk.dts1 // SPDX-License-Identifier: GPL-2.0+
10 compatible = "altr,socfpga-cyclone5-socdk", "altr,socfpga-cyclone5", "altr,socfpga";
14 stdout-path = "serial0:115200n8";
31 compatible = "gpio-leds";
53 regulator_3_3v: 3-3-v-regulator {
54 compatible = "regulator-fixed";
55 regulator-name = "3.3V";
56 regulator-min-microvolt = <3300000>;
57 regulator-max-microvolt = <3300000>;
67 phy-mode = "rgmii";
[all …]
H A Dsocfpga_cyclone5_sockit.dts1 // SPDX-License-Identifier: GPL-2.0+
10 compatible = "terasic,socfpga-cyclone5-sockit", "altr,socfpga-cyclone5", "altr,socfpga";
14 stdout-path = "serial0:115200n8";
31 compatible = "gpio-leds";
36 linux,default-trigger = "heartbeat";
42 linux,default-trigger = "heartbeat";
48 linux,default-trigger = "heartbeat";
54 linux,default-trigger = "heartbeat";
58 gpio-keys {
59 compatible = "gpio-keys";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dcdns,qspi-nor-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for the Cadence QSPI controller.
10 See spi-peripheral-props.yaml for more info.
13 - Vaishnav Achath <vaishnav.a@ti.com>
16 # cdns,qspi-nor.yaml
17 cdns,read-delay:
22 cdns,tshsl-ns:
[all …]
/openbmc/u-boot/doc/device-tree-bindings/spi/
H A Dspi-cadence.txt2 --------------------------------------------
5 - compatible : should be "cdns,qspi-nor"
6 - reg : 1.Physical base address and size of SPI registers map.
8 - clocks : Clock phandles (see clock bindings for details).
9 - cdns,fifo-depth : Size of the data FIFO in words.
10 - cdns,fifo-width : Bus width of the data FIFO in bytes.
11 - cdns,trigger-address : 32-bit indirect AHB trigger address.
12 - cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
13 - status : enable in requried dts.
16 --------------------------
[all …]
/openbmc/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_n5x_socdk.dts1 // SPDX-License-Identifier: GPL-2.0
9 compatible = "intel,n5x-socdk", "intel,socfpga-agilex";
19 stdout-path = "serial0:115200n8";
29 sdram_edac: memory-controller@f87f8000 {
30 compatible = "snps,ddrc-3.80a";
39 compatible = "intel,easic-n5x-clkmgr";
44 phy-mode = "rgmii";
45 phy-handle = <&phy0>;
47 max-frame-size = <9000>;
50 #address-cells = <1>;
[all …]
H A Dsocfpga_agilex_socdk.dts1 // SPDX-License-Identifier: GPL-2.0
9 compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex";
19 stdout-path = "serial0:115200n8";
23 compatible = "gpio-leds";
53 phy-mode = "rgmii";
54 phy-handle = <&phy0>;
56 max-frame-size = <9000>;
59 #address-cells = <1>;
60 #size-cells = <0>;
61 compatible = "snps,dwmac-mdio";
[all …]
/openbmc/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10_socdk_nand.dts1 // SPDX-License-Identifier: GPL-2.0-only
10 compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10";
20 stdout-path = "serial0:115200n8";
24 compatible = "gpio-leds";
25 led-hps0 {
30 led-hps1 {
35 led-hps2 {
47 ref_033v: regulator-v-ref {
48 compatible = "regulator-fixed";
49 regulator-name = "0.33V";
[all …]
H A Dsocfpga_stratix10_socdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
10 compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10";
20 stdout-path = "serial0:115200n8";
24 compatible = "gpio-leds";
25 led-hps0 {
30 led-hps1 {
35 led-hps2 {
47 ref_033v: regulator-v-ref {
48 compatible = "regulator-fixed";
49 regulator-name = "0.33V";
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-j721s2-som-p0.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include "k3-j721s2.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
22 reserved_memory: reserved-memory {
23 #address-cells = <2>;
24 #size-cells = <2>;
30 no-map;
34 mux0: mux-controller {
[all …]
H A Dk3-am642-tqma64xxl.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany.
7 #include "k3-am642.dtsi"
18 /* 1G RAM - default variant */
23 reserved-memory {
24 #address-cells = <2>;
25 #size-cells = <2>;
31 no-map;
34 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
[all …]

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