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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Damlogic,meson-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
20 - amlogic,meson6-dwmac
21 - amlogic,meson8b-dwmac
22 - amlogic,meson8m2-dwmac
23 - amlogic,meson-gxbb-dwmac
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/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-meson8b.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
52 * timing tuning.
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
73 /* Defined for adding a delay to the input RX_CLK for better timing.
112 data = readl(dwmac->regs + reg); in meson8b_dwmac_mask_bits()
116 writel(data, dwmac->regs + reg); in meson8b_dwmac_mask_bits()
129 snprintf(clk_name, sizeof(clk_name), "%s#%s", dev_name(dwmac->dev), in meson8b_dwmac_register_clk()
138 hw->init = &init; in meson8b_dwmac_register_clk()
140 return devm_clk_register(dwmac->dev, hw); in meson8b_dwmac_register_clk()
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H A Ddwmac-mediatek.c1 // SPDX-License-Identifier: GPL-2.0
114 int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0; in mt2712_set_interface()
115 int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0; in mt2712_set_interface()
119 switch (plat->phy_mode) { in mt2712_set_interface()
133 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_set_interface()
134 return -EINVAL; in mt2712_set_interface()
137 regmap_write(plat->peri_regmap, PERI_ETH_PHY_INTF_SEL, intf_val); in mt2712_set_interface()
144 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt2712_delay_ps2stage()
146 switch (plat->phy_mode) { in mt2712_delay_ps2stage()
150 mac_delay->tx_delay /= 550; in mt2712_delay_ps2stage()
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/openbmc/linux/drivers/gpu/drm/sti/
H A Dsti_awg_utils.c1 // SPDX-License-Identifier: GPL-2.0
11 #define AWG_DELAY (-5)
48 if (fwparams->instruction_offset >= AWG_MAX_INST) { in awg_generate_instr()
50 return -EINVAL; in awg_generate_instr()
57 arg--; /* pixel adjustment */ in awg_generate_instr()
58 arg_tmp--; in awg_generate_instr()
105 return -EINVAL; in awg_generate_instr()
108 arg_tmp = arg_tmp - arg; in awg_generate_instr()
113 fwparams->ram_code[fwparams->instruction_offset] = in awg_generate_instr()
115 fwparams->instruction_offset++; in awg_generate_instr()
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/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dst,sta350.txt7 - compatible: "st,sta350"
8 - reg: the I2C address of the device for I2C
9 - reset-gpios: a GPIO spec for the reset pin. If specified, it will be
12 - power-down-gpios: a GPIO spec for the power down pin. If specified,
16 - vdd-dig-supply: regulator spec, providing 3.3V
17 - vdd-pll-supply: regulator spec, providing 3.3V
18 - vcc-supply: regulator spec, providing 5V - 26V
22 - st,output-conf: number, Selects the output configuration:
23 0: 2-channel (full-bridge) power, 2-channel data-out
24 1: 2 (half-bridge). 1 (full-bridge) on-board power
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/openbmc/linux/drivers/video/backlight/
H A Dtdo24m.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * tdo24m - SPI-based drivers for Toppoly TDO24M series LCD panels
45 #define CMD_NULL (-1)
92 CMD1(0xd1, 0x01), /* CKV timing control on/off */
93 CMD2(0xd2, 0x14, 0x00), /* CKV 1,2 timing control */
94 CMD2(0xd3, 0x1a, 0x0f), /* OEV timing control */
95 CMD2(0xd4, 0x1f, 0xaf), /* ASW timing control (1) */
96 CMD1(0xd5, 0x14), /* ASW timing control (2) */
105 CMD1(0xd8, 0x01), /* CKV timing control on/off */
106 CMD2(0xd9, 0x00, 0x08), /* CKV 1,2 timing control */
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/openbmc/linux/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_10nm.c2 * SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
15 * DSI PLL 10nm - clock diagram (eg: DSI0):
20 * +---------+ | +----------+ | +----+
21 * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
22 * +---------+ | +----------+ | +----+
26 * | | +----+ | |\ dsi0_pclk_mux
27 * | |--| /2 |--o--| \ |
28 * | | +----+ | \ | +---------+
29 …* | --------------| |--o--| div_7_4 |-- dsi0_phy_pll_…
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/openbmc/linux/net/mac80211/
H A Dmesh_sync.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012, Pavel Zubarev <pavel.zubarev@gmail.com>
4 * Copyright 2011-2012, Marco Porsch <marco.porsch@s2005.tu-chemnitz.de>
5 * Copyright 2011-2012, cozybit Inc.
11 #include "driver-ops.h"
14 * which we do no TSF adjustment.
20 * introduced by TSF adjustment latency.
37 * mesh_peer_tbtt_adjusting - check if an mp is currently adjusting its TBTT
44 (cfg->meshconf_cap & IEEE80211_MESHCONF_CAPAB_TBTT_ADJUSTING); in mesh_peer_tbtt_adjusting()
49 struct ieee80211_local *local = sdata->local; in mesh_sync_adjust_tsf()
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/openbmc/u-boot/drivers/ram/
H A Dk3-am654-ddrss.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
14 #include <power-domain.h>
18 #include "k3-am654-ddrss.h"
26 * struct am654_ddrss_desc - Description of ddrss integration.
60 #define ddrss_ctl_writel(off, val) ddrss_writel(ddrss->ddrss_ctl_cfg, off, val)
61 #define ddrss_ctl_readl(off) ddrss_readl(ddrss->ddrss_ctl_cfg, off)
69 * am654_ddrss_dram_wait_for_init_complete() - Wait for init to complete
93 return -EINVAL; in am654_ddrss_dram_wait_for_init_complt()
97 ddrss->ddrss_ctl_cfg + DDRSS_DDRCTL_STAT, LDELAY)) in am654_ddrss_dram_wait_for_init_complt()
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/openbmc/linux/drivers/mmc/host/
H A Dsdhci-xenon-phy.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Date: 2016-8-24
17 #include "sdhci-pltfm.h"
18 #include "sdhci-xenon.h"
87 * according to board actual timing.
120 /* Offset of Timing Adjust register */
130 /* Offset of Logic Timing Adjust register */
134 /* value in Logic Timing Adjustment register */
209 params = devm_kzalloc(mmc_dev(host->mmc), sizeof(*params), GFP_KERNEL); in xenon_alloc_emmc_phy()
211 return -ENOMEM; in xenon_alloc_emmc_phy()
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H A Dsdhci-xenon.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Date: 2016-8-24
22 #include "sdhci-pltfm.h"
23 #include "sdhci-xenon.h"
42 dev_err(mmc_dev(host->mmc), "Internal clock never stabilised.\n"); in xenon_enable_internal_clk()
43 return -ETIMEDOUT; in xenon_enable_internal_clk()
51 /* Set SDCLK-off-while-idle */
92 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; in xenon_enable_sdhc()
97 host->mmc->caps &= ~MMC_CAP_BUS_WIDTH_TEST; in xenon_enable_sdhc()
138 /* Disable the Re-Tuning Request functionality */ in xenon_retune_setup()
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/openbmc/linux/arch/arm/boot/dts/amlogic/
H A Dmeson8m2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
14 compatible = "amlogic,meson8m2-clkc", "amlogic,meson8-clkc";
19 /delete-node/ video-lut@20;
21 canvas: video-lut@48 {
22 compatible = "amlogic,meson8m2-canvas", "amlogic,canvas";
28 compatible = "amlogic,meson8m2-dwmac", "snps,dwmac";
35 clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
37 reset-names = "stmmaceth";
41 compatible = "amlogic,meson8m2-aobus-pinctrl",
42 "amlogic,meson8-aobus-pinctrl";
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/openbmc/u-boot/Documentation/devicetree/bindings/ram/
H A Dfsl,mpc83xx-mem-controller.txt3 This driver supplies support for the embedded RAM controller on MCP83xx-series
13 - compatible: Must be "fsl,mpc83xx-mem-controller"
14 - reg: The address of the RAM controller's register space
15 - #address-cells: Must be 2
16 - #size-cells: Must be 1
17 - driver_software_override: DDR driver software override is enabled (1) or
19 - p_impedance_override: DDR driver software p-impedance override; possible
26 - n_impedance_override: DDR driver software n-impedance override; possible
33 - odt_termination_value: ODT termination value for I/Os; possible values:
36 - ddr_type: Selects voltage level for DDR pads; possible
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/openbmc/u-boot/drivers/video/
H A Dlogicore_dp_tx.c1 // SPDX-License-Identifier: GPL-2.0+
31 /* The maximum pre-emphasis level is 3 */
42 * enum link_training_states - States for link training state machine
62 * struct aux_transaction - Description of an AUX channel transaction
76 * struct main_stream_attributes - Main stream attributes
87 * to the native internal 16-bit datapath
150 * struct link_config - Description of link configuration
162 * @pe_level: Pre-emphasis/cursor level for each lane
177 * struct dp_tx - Private data structure of LogiCore DP TX devices
186 * @lane_status_ajd_reqs: Lane status and adjustment requests information for
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/openbmc/linux/include/linux/
H A Dtimex.h28 * Added defines for hybrid phase/frequency-lock loop.
32 * defines for PPS phase-lock loop.
46 * 1995-08-13 Torsten Duwe
47 * kernel PLL updated to 1994-12-13 specs (rfc-1589)
48 * 1997-08-30 Ulrich Windl
50 * 2004-08-12 Christoph Lameter
59 #define ADJ_OFFSET_SINGLESHOT 0x0001 /* old-fashioned adjtime */
60 #define ADJ_OFFSET_READONLY 0x2000 /* read-only adjtime */
73 * when an interrupt takes places versus a high speed, fine-grained
74 * timing source or cycle counter. Since it will be occurred on every
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/openbmc/linux/drivers/net/wireless/intel/iwlegacy/
H A D4965.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
8 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
15 #include <linux/dma-mapping.h>
29 * il_verify_inst_sparse - verify runtime uCode image in card vs. host,
44 /* read data comes through single port, auto-incr addr */ in il4965_verify_inst_sparse()
50 ret = -EIO; in il4965_verify_inst_sparse()
61 * il4965_verify_inst_full - verify runtime uCode image in card vs. host,
77 for (; len > 0; len -= sizeof(u32), image++) { in il4965_verify_inst_full()
78 /* read data comes through single port, auto-incr addr */ in il4965_verify_inst_full()
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/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_intf.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
101 struct dpu_hw_blk_reg_map *c = &ctx->hw; in dpu_hw_intf_setup_timing_engine()
119 if (ctx->cap->type == INTF_DP) in dpu_hw_intf_setup_timing_engine()
122 hsync_period = p->hsync_pulse_width + p->h_back_porch + p->width + in dpu_hw_intf_setup_timing_engine()
123 p->h_front_porch; in dpu_hw_intf_setup_timing_engine()
124 vsync_period = p->vsync_pulse_width + p->v_back_porch + p->height + in dpu_hw_intf_setup_timing_engine()
125 p->v_front_porch; in dpu_hw_intf_setup_timing_engine()
127 display_v_start = ((p->vsync_pulse_width + p->v_back_porch) * in dpu_hw_intf_setup_timing_engine()
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/openbmc/linux/kernel/time/
H A Dclocksource.c1 // SPDX-License-Identifier: GPL-2.0+
20 #include "tick-internal.h"
25 u64 delta = clocksource_delta(end, start, cs->mask); in cycles_to_nsec_safe()
27 if (likely(delta < cs->max_cycles)) in cycles_to_nsec_safe()
28 return clocksource_cyc2ns(delta, cs->mult, cs->shift); in cycles_to_nsec_safe()
30 return mul_u64_u32_shr(delta, cs->mult, cs->shift); in cycles_to_nsec_safe()
34 * clocks_calc_mult_shift - calculate mult/shift factors for scaled math of clocks
69 sftacc--; in clocks_calc_mult_shift()
76 for (sft = 32; sft > 0; sft--) { in clocks_calc_mult_shift()
88 /*[Clocksource internal variables]---------
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/openbmc/linux/drivers/clocksource/
H A Dtimer-cadence-ttc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2013 Xilinx
23 * This driver configures the 2 16/32-bit count-up timers as follows:
30 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
34 * obtained from device tree. The pre-scaler of 32 is used.
55 * Setup the timers to use pre-scaling, using a fixed value for now that will
60 #define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
67 * struct ttc_timer - This definition defines local timer structure
105 * ttc_set_interval - Set the timer interval value
115 /* Disable the counter, set the counter value and re-enable counter */ in ttc_set_interval()
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/openbmc/linux/drivers/media/i2c/
H A Dks0127.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * for the Matrox Marvel G200,G400 and Rainbow Runner-G series
20 * V1.1 Gerard v.d. Horst Added some debugoutput, reset the video-standard
31 #include <media/v4l2-device.h>
258 table[KS_UVOFFH] = 0x00; /* UV Offset Adjustment High */ in init_reg_defaults()
259 table[KS_UVOFFL] = 0x00; /* UV Offset Adjustment Low */ in init_reg_defaults()
260 table[KS_UGAIN] = 0x00; /* U Component Gain Adjustment */ in init_reg_defaults()
261 table[KS_VGAIN] = 0x00; /* V Component Gain Adjustment */ in init_reg_defaults()
265 table[KS_POLCTL] = 0x41; /* Timing Signal Polarity Control */ in init_reg_defaults()
281 /* Command Register F, update -immediately- */ in init_reg_defaults()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_types.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
60 * (access to non-DC registers will hang FPGA) */
146 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
148 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
231 /* native display timing*/
236 *_not_ related to the Reduced Blanking adjustment*/
244 /* this timing should be used only in tiled mode*/
249 Must be zero for wired displays and non-zero for
287 /* these timing might not work, least important*/
342 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */
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/openbmc/linux/drivers/net/wireless/intel/iwlwifi/dvm/
H A Drxon.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
9 #include "iwl-trans.h"
10 #include "iwl-modparams.h"
21 memset(&ctx->staging, 0, sizeof(ctx->staging)); in iwl_connection_init_rx_config()
23 if (!ctx->vif) { in iwl_connection_init_rx_config()
24 ctx->staging.dev_type = ctx->unused_devtype; in iwl_connection_init_rx_config()
26 switch (ctx->vif->type) { in iwl_connection_init_rx_config()
28 ctx->staging.dev_type = ctx->ap_devtype; in iwl_connection_init_rx_config()
32 ctx->staging.dev_type = ctx->station_devtype; in iwl_connection_init_rx_config()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_resource.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
80 * relatively the same independent from timing used.
86 #define UNABLE_TO_SPLIT -1
206 init_data->num_virtual_links, dc); in dc_create_resource_pool()
210 init_data->num_virtual_links, dc); in dc_create_resource_pool()
214 init_data->num_virtual_links, dc); in dc_create_resource_pool()
219 init_data->num_virtual_links, dc); in dc_create_resource_pool()
223 init_data->num_virtual_links, dc); in dc_create_resource_pool()
227 init_data->num_virtual_links, dc); in dc_create_resource_pool()
231 init_data->num_virtual_links, dc); in dc_create_resource_pool()
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/openbmc/linux/arch/s390/kernel/
H A Dtime.c1 // SPDX-License-Identifier: GPL-2.0
61 u64 clock_comparator_max = -1ULL;
111 * Scheduler clock - returns current time in nanosec units.
123 sec = clk->us; in ext_to_timespec64()
125 nsec = ((clk->sus + (rem << 12)) * 125) >> 9; in ext_to_timespec64()
126 xt->tv_sec = sec; in ext_to_timespec64()
127 xt->tv_nsec = nsec; in ext_to_timespec64()
136 cd->event_handler(cd); in clock_comparator_work()
161 cd->name = "comparator"; in init_cpu_timer()
162 cd->features = CLOCK_EVT_FEAT_ONESHOT; in init_cpu_timer()
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/openbmc/linux/drivers/gpu/drm/radeon/
H A Dradeon_legacy_tv.c1 // SPDX-License-Identifier: MIT
16 #define MAX_H_POSITION 5 /* Range: [-5..5], negative is on the left, 0 is default, positive is on t…
17 #define MAX_V_POSITION 5 /* Range: [-5..5], negative is up, 0 is default, positive is down */
25 * Indexes in h. code timing table for horizontal line position adjustment
33 #define MAX_H_SIZE 5 /* Range: [-5..5], negative is smaller, positive is larger */
172 { /* NTSC timing for 27 Mhz ref clk */
187 { /* PAL timing for 27 Mhz ref clk */
202 { /* NTSC timing for 14 Mhz ref clk */
217 { /* PAL timing for 14 Mhz ref clk */
239 struct drm_device *dev = radeon_encoder->base.dev; in radeon_legacy_tv_get_std_mode()
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