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/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dezchip,nps400-timer0.txt5 - compatible : should be "ezchip,nps400-timer0"
7 Clocks required for compatible = "ezchip,nps400-timer0":
14 compatible = "ezchip,nps400-timer0";
H A Dsnps,arc-timer.txt4 - Two identical copies TIMER0 and TIMER1 exist in ARC cores and historically
5 TIMER0 used as clockevent provider (true for all ARC cores)
17 timer0 {
H A Dactions,owl-timer.txt10 "timer0", "timer1", "timer2", "timer3"
20 interrupt-names = "timer0", "timer1";
H A Darm,sp804.yaml56 be 1 or 3 clocks. With 3 clocks, the order is timer0 clock, timer1
91 timer0: timer@fc800000 {
H A Dmarvell,orion-timer.txt6 - interrupts: should contain the interrupts for Timer0 and Timer1
H A Dingenic,tcu.yaml177 - const: timer0
289 clock-names = "timer0", "timer1", "timer2", "timer3",
H A Dcirrus,clps711x-timer.txt13 timer0 = &timer1;
/openbmc/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Dtimer.c12 static struct timer_regs *timer0 = (struct timer_regs *)TIMER0_BASE; variable
49 lpc32xx_timer_reset(timer0, CONFIG_SYS_HZ); in timer_init()
50 lpc32xx_timer_count(timer0, 1); in timer_init()
57 return readl(&timer0->tc) - base; in get_timer()
/openbmc/linux/arch/arc/boot/dts/
H A Dskeleton.dtsi30 /* TIMER0 with interrupt for clockevent */
31 timer0 {
H A Dskeleton_hs.dtsi25 /* TIMER0 with interrupt for clockevent */
26 timer0 {
H A Dskeleton_hs_idu.dtsi43 /* TIMER0 with interrupt for clockevent */
44 timer0 {
/openbmc/u-boot/arch/nds32/dts/
H A Dag101p.dts17 tick-timer = &timer0;
51 timer0: timer@98400000 { label
H A Dae3xx.dts18 tick-timer = &timer0;
59 timer0: timer@f0400000 { label
/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-lpc18xx.c170 [FUNC_TIMER0] = "timer0",
254 LPC_P(1,12, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, SDMMC, 0, ND);
255 LPC_P(1,13, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, SDMMC, 0, ND);
256 LPC_P(1,14, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, R, 0, ND);
257 LPC_P(1,15, GPIO, UART2, SGPIO, ENET, TIMER0, R, R, R, 0, ND);
258 LPC_P(1,16, GPIO, UART2, SGPIO,ENET_ALT,TIMER0, R, R, ENET, 0, ND);
259 LPC_P(1,17, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, HD);
260 LPC_P(1,18, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, ND);
262 LPC_P(1,20, GPIO, SSP1, R, ENET, TIMER0, R, SGPIO, R, 0, ND);
326 LPC_P(8,0, GPIO, USB0, R, MCTRL, SGPIO, R, R, TIMER0, 0, HD);
[all …]
/openbmc/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10_swvp.dts16 timer0 = &timer0;
/openbmc/linux/drivers/clocksource/
H A Darc_timer.c7 /* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1, Each can be
9 * We've designated TIMER0 for clockevents and TIMER1 for clocksource
270 .name = "ARC Timer0",
342 "Timer0 (per-cpu-tick)", evt); in arc_clockevent_setup()
H A DKconfig180 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
181 where TIMER0 serves as clockevent and TIMER1 serves as clocksource.
289 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
291 TIMER0 serves as clockevent while TIMER1 provides clocksource.
/openbmc/linux/arch/mips/loongson64/
H A Dhpet.c95 /* enables the timer0 to generate a periodic interrupt */ in hpet_set_state_periodic()
137 * set timer0 type in hpet_set_state_oneshot()
181 /* clear the TIMER0 irq status register */ in hpet_irq_handler()
/openbmc/linux/drivers/pci/hotplug/
H A Dcpcihp_zt5550.c113 * Disable timer0, timer1 and ENUM interrupts in zt5550_hc_config()
115 dbg("disabling timer0, timer1 and ENUM interrupts"); in zt5550_hc_config()
117 dbg("disabled timer0, timer1 and ENUM interrupts"); in zt5550_hc_config()
/openbmc/linux/arch/arm/boot/dts/intel/axm/
H A Daxm55xx.dtsi21 timer = &timer0;
147 timer0: timer@2010091000 { label
/openbmc/linux/include/dt-bindings/pinctrl/
H A Dk210-fpioa.h204 #define K210_PCF_TIMER0_TOGGLE1 190 /* TIMER0 Toggle Output 1 */
205 #define K210_PCF_TIMER0_TOGGLE2 191 /* TIMER0 Toggle Output 2 */
206 #define K210_PCF_TIMER0_TOGGLE3 192 /* TIMER0 Toggle Output 3 */
207 #define K210_PCF_TIMER0_TOGGLE4 193 /* TIMER0 Toggle Output 4 */
/openbmc/u-boot/arch/arm/mach-highbank/
H A Dtimer.c23 * Setup timer0 in timer_init()
/openbmc/linux/arch/mips/cobalt/
H A Dtime.c26 * using GT64111 timer0. in plat_time_init()
/openbmc/qemu/hw/avr/
H A Datmega.c29 TIMER0, TIMER1, TIMER2, TIMER3, TIMER4, TIMER5, enumerator
35 #define TIMER(n) (n + TIMER0)
73 [TIMER0] = { 0x44, POWER0, 5, 0x6e, 0x35, false },
93 [TIMER0] = { 0x44, POWER0, 5, 0x6e, 0x35, false },
/openbmc/linux/arch/arm/mach-spear/
H A Dtime.c26 * We would use TIMER0 and TIMER1 as clockevent and clocksource.
27 * Timer0 and Timer1 both belong to same gpt block in cpu subbsystem. Further

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