1d2912cb1SThomas Gleixner// SPDX-License-Identifier: GPL-2.0-only 22e8cd938SVineet Gupta/* 32e8cd938SVineet Gupta * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com) 42e8cd938SVineet Gupta */ 52e8cd938SVineet Gupta 62e8cd938SVineet Gupta/ { 72e8cd938SVineet Gupta compatible = "snps,arc"; 82e8cd938SVineet Gupta #address-cells = <1>; 92e8cd938SVineet Gupta #size-cells = <1>; 102e8cd938SVineet Gupta chosen { }; 112e8cd938SVineet Gupta aliases { }; 122e8cd938SVineet Gupta 132e8cd938SVineet Gupta cpus { 142e8cd938SVineet Gupta #address-cells = <1>; 152e8cd938SVineet Gupta #size-cells = <0>; 162e8cd938SVineet Gupta 172e8cd938SVineet Gupta cpu@0 { 182e8cd938SVineet Gupta device_type = "cpu"; 192e8cd938SVineet Gupta compatible = "snps,archs38"; 202e8cd938SVineet Gupta reg = <0>; 21854c11e2SVlad Zakharov clocks = <&core_clk>; 222e8cd938SVineet Gupta }; 232e8cd938SVineet Gupta }; 242e8cd938SVineet Gupta 257ec9f34aSVineet Gupta /* TIMER0 with interrupt for clockevent */ 267ec9f34aSVineet Gupta timer0 { 277ec9f34aSVineet Gupta compatible = "snps,arc-timer"; 287ec9f34aSVineet Gupta interrupts = <16>; 297ec9f34aSVineet Gupta interrupt-parent = <&core_intc>; 307ec9f34aSVineet Gupta clocks = <&core_clk>; 317ec9f34aSVineet Gupta }; 327ec9f34aSVineet Gupta 337ec9f34aSVineet Gupta /* 64-bit Local RTC: preferred clocksource for UP */ 347ec9f34aSVineet Gupta rtc { 357ec9f34aSVineet Gupta compatible = "snps,archs-timer-rtc"; 367ec9f34aSVineet Gupta clocks = <&core_clk>; 377ec9f34aSVineet Gupta }; 387ec9f34aSVineet Gupta 397ec9f34aSVineet Gupta /* TIMER1 for free running clocksource: Fallback if rtc not found */ 407ec9f34aSVineet Gupta timer1 { 417ec9f34aSVineet Gupta compatible = "snps,arc-timer"; 427ec9f34aSVineet Gupta clocks = <&core_clk>; 437ec9f34aSVineet Gupta }; 447ec9f34aSVineet Gupta 452e8cd938SVineet Gupta memory { 462e8cd938SVineet Gupta device_type = "memory"; 472e8cd938SVineet Gupta reg = <0x80000000 0x10000000>; /* 256M */ 482e8cd938SVineet Gupta }; 492e8cd938SVineet Gupta}; 50