xref: /openbmc/qemu/hw/avr/atmega.c (revision 235948bf)
1 /*
2  * QEMU ATmega MCU
3  *
4  * Copyright (c) 2019-2020 Philippe Mathieu-Daudé
5  *
6  * This work is licensed under the terms of the GNU GPLv2 or later.
7  * See the COPYING file in the top-level directory.
8  * SPDX-License-Identifier: GPL-2.0-or-later
9  */
10 
11 #include "qemu/osdep.h"
12 #include "qemu/module.h"
13 #include "qemu/units.h"
14 #include "qapi/error.h"
15 #include "exec/memory.h"
16 #include "exec/address-spaces.h"
17 #include "sysemu/sysemu.h"
18 #include "hw/qdev-properties.h"
19 #include "hw/sysbus.h"
20 #include "qom/object.h"
21 #include "hw/misc/unimp.h"
22 #include "atmega.h"
23 
24 enum AtmegaPeripheral {
25     POWER0, POWER1,
26     GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF,
27     GPIOG, GPIOH, GPIOI, GPIOJ, GPIOK, GPIOL,
28     USART0, USART1, USART2, USART3,
29     TIMER0, TIMER1, TIMER2, TIMER3, TIMER4, TIMER5,
30     PERIFMAX
31 };
32 
33 #define GPIO(n)     (n + GPIOA)
34 #define USART(n)    (n + USART0)
35 #define TIMER(n)    (n + TIMER0)
36 #define POWER(n)    (n + POWER0)
37 
38 typedef struct {
39     uint16_t addr;
40     enum AtmegaPeripheral power_index;
41     uint8_t power_bit;
42     /* timer specific */
43     uint16_t intmask_addr;
44     uint16_t intflag_addr;
45     bool is_timer16;
46 } peripheral_cfg;
47 
48 struct AtmegaMcuClass {
49     /*< private >*/
50     SysBusDeviceClass parent_class;
51     /*< public >*/
52     const char *uc_name;
53     const char *cpu_type;
54     size_t flash_size;
55     size_t eeprom_size;
56     size_t sram_size;
57     size_t io_size;
58     size_t gpio_count;
59     size_t adc_count;
60     const uint8_t *irq;
61     const peripheral_cfg *dev;
62 };
63 typedef struct AtmegaMcuClass AtmegaMcuClass;
64 
65 DECLARE_CLASS_CHECKERS(AtmegaMcuClass, ATMEGA_MCU,
66                        TYPE_ATMEGA_MCU)
67 
68 static const peripheral_cfg dev168_328[PERIFMAX] = {
69     [USART0]        = {  0xc0, POWER0, 1 },
70     [TIMER2]        = {  0xb0, POWER0, 6, 0x70, 0x37, false },
71     [TIMER1]        = {  0x80, POWER0, 3, 0x6f, 0x36, true },
72     [POWER0]        = {  0x64 },
73     [TIMER0]        = {  0x44, POWER0, 5, 0x6e, 0x35, false },
74     [GPIOD]         = {  0x29 },
75     [GPIOC]         = {  0x26 },
76     [GPIOB]         = {  0x23 },
77 }, dev1280_2560[PERIFMAX] = {
78     [USART3]        = { 0x130, POWER1, 2 },
79     [TIMER5]        = { 0x120, POWER1, 5, 0x73, 0x3a, true },
80     [GPIOL]         = { 0x109 },
81     [GPIOK]         = { 0x106 },
82     [GPIOJ]         = { 0x103 },
83     [GPIOH]         = { 0x100 },
84     [USART2]        = {  0xd0, POWER1, 1 },
85     [USART1]        = {  0xc8, POWER1, 0 },
86     [USART0]        = {  0xc0, POWER0, 1 },
87     [TIMER2]        = {  0xb0, POWER0, 6, 0x70, 0x37, false }, /* TODO async */
88     [TIMER4]        = {  0xa0, POWER1, 4, 0x72, 0x39, true },
89     [TIMER3]        = {  0x90, POWER1, 3, 0x71, 0x38, true },
90     [TIMER1]        = {  0x80, POWER0, 3, 0x6f, 0x36, true },
91     [POWER1]        = {  0x65 },
92     [POWER0]        = {  0x64 },
93     [TIMER0]        = {  0x44, POWER0, 5, 0x6e, 0x35, false },
94     [GPIOG]         = {  0x32 },
95     [GPIOF]         = {  0x2f },
96     [GPIOE]         = {  0x2c },
97     [GPIOD]         = {  0x29 },
98     [GPIOC]         = {  0x26 },
99     [GPIOB]         = {  0x23 },
100     [GPIOA]         = {  0x20 },
101 };
102 
103 enum AtmegaIrq {
104     USART0_RXC_IRQ, USART0_DRE_IRQ, USART0_TXC_IRQ,
105     USART1_RXC_IRQ, USART1_DRE_IRQ, USART1_TXC_IRQ,
106     USART2_RXC_IRQ, USART2_DRE_IRQ, USART2_TXC_IRQ,
107     USART3_RXC_IRQ, USART3_DRE_IRQ, USART3_TXC_IRQ,
108     TIMER0_CAPT_IRQ, TIMER0_COMPA_IRQ, TIMER0_COMPB_IRQ,
109         TIMER0_COMPC_IRQ, TIMER0_OVF_IRQ,
110     TIMER1_CAPT_IRQ, TIMER1_COMPA_IRQ, TIMER1_COMPB_IRQ,
111         TIMER1_COMPC_IRQ, TIMER1_OVF_IRQ,
112     TIMER2_CAPT_IRQ, TIMER2_COMPA_IRQ, TIMER2_COMPB_IRQ,
113         TIMER2_COMPC_IRQ, TIMER2_OVF_IRQ,
114     TIMER3_CAPT_IRQ, TIMER3_COMPA_IRQ, TIMER3_COMPB_IRQ,
115         TIMER3_COMPC_IRQ, TIMER3_OVF_IRQ,
116     TIMER4_CAPT_IRQ, TIMER4_COMPA_IRQ, TIMER4_COMPB_IRQ,
117         TIMER4_COMPC_IRQ, TIMER4_OVF_IRQ,
118     TIMER5_CAPT_IRQ, TIMER5_COMPA_IRQ, TIMER5_COMPB_IRQ,
119         TIMER5_COMPC_IRQ, TIMER5_OVF_IRQ,
120     IRQ_COUNT
121 };
122 
123 #define USART_IRQ_COUNT     3
124 #define USART_RXC_IRQ(n)    (n * USART_IRQ_COUNT + USART0_RXC_IRQ)
125 #define USART_DRE_IRQ(n)    (n * USART_IRQ_COUNT + USART0_DRE_IRQ)
126 #define USART_TXC_IRQ(n)    (n * USART_IRQ_COUNT + USART0_TXC_IRQ)
127 #define TIMER_IRQ_COUNT     5
128 #define TIMER_CAPT_IRQ(n)   (n * TIMER_IRQ_COUNT + TIMER0_CAPT_IRQ)
129 #define TIMER_COMPA_IRQ(n)  (n * TIMER_IRQ_COUNT + TIMER0_COMPA_IRQ)
130 #define TIMER_COMPB_IRQ(n)  (n * TIMER_IRQ_COUNT + TIMER0_COMPB_IRQ)
131 #define TIMER_COMPC_IRQ(n)  (n * TIMER_IRQ_COUNT + TIMER0_COMPC_IRQ)
132 #define TIMER_OVF_IRQ(n)    (n * TIMER_IRQ_COUNT + TIMER0_OVF_IRQ)
133 
134 static const uint8_t irq168_328[IRQ_COUNT] = {
135     [TIMER2_COMPA_IRQ]      = 8,
136     [TIMER2_COMPB_IRQ]      = 9,
137     [TIMER2_OVF_IRQ]        = 10,
138     [TIMER1_CAPT_IRQ]       = 11,
139     [TIMER1_COMPA_IRQ]      = 12,
140     [TIMER1_COMPB_IRQ]      = 13,
141     [TIMER1_OVF_IRQ]        = 14,
142     [TIMER0_COMPA_IRQ]      = 15,
143     [TIMER0_COMPB_IRQ]      = 16,
144     [TIMER0_OVF_IRQ]        = 17,
145     [USART0_RXC_IRQ]        = 19,
146     [USART0_DRE_IRQ]        = 20,
147     [USART0_TXC_IRQ]        = 21,
148 }, irq1280_2560[IRQ_COUNT] = {
149     [TIMER2_COMPA_IRQ]      = 14,
150     [TIMER2_COMPB_IRQ]      = 15,
151     [TIMER2_OVF_IRQ]        = 16,
152     [TIMER1_CAPT_IRQ]       = 17,
153     [TIMER1_COMPA_IRQ]      = 18,
154     [TIMER1_COMPB_IRQ]      = 19,
155     [TIMER1_COMPC_IRQ]      = 20,
156     [TIMER1_OVF_IRQ]        = 21,
157     [TIMER0_COMPA_IRQ]      = 22,
158     [TIMER0_COMPB_IRQ]      = 23,
159     [TIMER0_OVF_IRQ]        = 24,
160     [USART0_RXC_IRQ]        = 26,
161     [USART0_DRE_IRQ]        = 27,
162     [USART0_TXC_IRQ]        = 28,
163     [TIMER3_CAPT_IRQ]       = 32,
164     [TIMER3_COMPA_IRQ]      = 33,
165     [TIMER3_COMPB_IRQ]      = 34,
166     [TIMER3_COMPC_IRQ]      = 35,
167     [TIMER3_OVF_IRQ]        = 36,
168     [USART1_RXC_IRQ]        = 37,
169     [USART1_DRE_IRQ]        = 38,
170     [USART1_TXC_IRQ]        = 39,
171     [TIMER4_CAPT_IRQ]       = 42,
172     [TIMER4_COMPA_IRQ]      = 43,
173     [TIMER4_COMPB_IRQ]      = 44,
174     [TIMER4_COMPC_IRQ]      = 45,
175     [TIMER4_OVF_IRQ]        = 46,
176     [TIMER5_CAPT_IRQ]       = 47,
177     [TIMER5_COMPA_IRQ]      = 48,
178     [TIMER5_COMPB_IRQ]      = 49,
179     [TIMER5_COMPC_IRQ]      = 50,
180     [TIMER5_OVF_IRQ]        = 51,
181     [USART2_RXC_IRQ]        = 52,
182     [USART2_DRE_IRQ]        = 53,
183     [USART2_TXC_IRQ]        = 54,
184     [USART3_RXC_IRQ]        = 55,
185     [USART3_DRE_IRQ]        = 56,
186     [USART3_TXC_IRQ]        = 57,
187 };
188 
connect_peripheral_irq(const AtmegaMcuClass * k,SysBusDevice * dev,int dev_irqn,DeviceState * cpu,unsigned peripheral_index)189 static void connect_peripheral_irq(const AtmegaMcuClass *k,
190                                    SysBusDevice *dev, int dev_irqn,
191                                    DeviceState *cpu,
192                                    unsigned peripheral_index)
193 {
194     int cpu_irq = k->irq[peripheral_index];
195 
196     if (!cpu_irq) {
197         return;
198     }
199     /* FIXME move that to avr_cpu_set_int() once 'sample' board is removed */
200     assert(cpu_irq >= 2);
201     cpu_irq -= 2;
202 
203     sysbus_connect_irq(dev, dev_irqn, qdev_get_gpio_in(cpu, cpu_irq));
204 }
205 
connect_power_reduction_gpio(AtmegaMcuState * s,const AtmegaMcuClass * k,DeviceState * cpu,unsigned peripheral_index)206 static void connect_power_reduction_gpio(AtmegaMcuState *s,
207                                          const AtmegaMcuClass *k,
208                                          DeviceState *cpu,
209                                          unsigned peripheral_index)
210 {
211     unsigned power_index = k->dev[peripheral_index].power_index;
212     assert(k->dev[power_index].addr);
213     sysbus_connect_irq(SYS_BUS_DEVICE(&s->pwr[power_index - POWER0]),
214                        k->dev[peripheral_index].power_bit,
215                        qdev_get_gpio_in(cpu, 0));
216 }
217 
atmega_realize(DeviceState * dev,Error ** errp)218 static void atmega_realize(DeviceState *dev, Error **errp)
219 {
220     AtmegaMcuState *s = ATMEGA_MCU(dev);
221     const AtmegaMcuClass *mc = ATMEGA_MCU_GET_CLASS(dev);
222     DeviceState *cpudev;
223     SysBusDevice *sbd;
224     char *devname;
225     size_t i;
226 
227     assert(mc->io_size <= 0x200);
228 
229     if (!s->xtal_freq_hz) {
230         error_setg(errp, "\"xtal-frequency-hz\" property must be provided.");
231         return;
232     }
233 
234     /* CPU */
235     object_initialize_child(OBJECT(dev), "cpu", &s->cpu, mc->cpu_type);
236 
237     object_property_set_uint(OBJECT(&s->cpu), "init-sp",
238                              mc->io_size + mc->sram_size - 1, &error_abort);
239 
240     qdev_realize(DEVICE(&s->cpu), NULL, &error_abort);
241     cpudev = DEVICE(&s->cpu);
242 
243     /* SRAM */
244     memory_region_init_ram(&s->sram, OBJECT(dev), "sram", mc->sram_size,
245                            &error_abort);
246     memory_region_add_subregion(get_system_memory(),
247                                 OFFSET_DATA + mc->io_size, &s->sram);
248 
249     /* Flash */
250     memory_region_init_rom(&s->flash, OBJECT(dev),
251                            "flash", mc->flash_size, &error_fatal);
252     memory_region_add_subregion(get_system_memory(), OFFSET_CODE, &s->flash);
253 
254     /*
255      * I/O
256      *
257      * 0x00 - 0x1f: Registers
258      * 0x20 - 0x5f: I/O memory
259      * 0x60 - 0xff: Extended I/O
260      */
261     s->io = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
262     qdev_prop_set_string(s->io, "name", "I/O");
263     qdev_prop_set_uint64(s->io, "size", mc->io_size);
264     sysbus_realize_and_unref(SYS_BUS_DEVICE(s->io), &error_fatal);
265     sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->io), 0, OFFSET_DATA, -1234);
266 
267     /* Power Reduction */
268     for (i = 0; i < POWER_MAX; i++) {
269         int idx = POWER(i);
270         if (!mc->dev[idx].addr) {
271             continue;
272         }
273         devname = g_strdup_printf("power%zu", i);
274         object_initialize_child(OBJECT(dev), devname, &s->pwr[i],
275                                 TYPE_AVR_MASK);
276         sysbus_realize(SYS_BUS_DEVICE(&s->pwr[i]), &error_abort);
277         sysbus_mmio_map(SYS_BUS_DEVICE(&s->pwr[i]), 0,
278                         OFFSET_DATA + mc->dev[idx].addr);
279         g_free(devname);
280     }
281 
282     /* GPIO */
283     for (i = 0; i < GPIO_MAX; i++) {
284         int idx = GPIO(i);
285         if (!mc->dev[idx].addr) {
286             continue;
287         }
288         devname = g_strdup_printf("atmega-gpio-%c", 'a' + (char)i);
289         create_unimplemented_device(devname,
290                                     OFFSET_DATA + mc->dev[idx].addr, 3);
291         g_free(devname);
292     }
293 
294     /* USART */
295     for (i = 0; i < USART_MAX; i++) {
296         int idx = USART(i);
297         if (!mc->dev[idx].addr) {
298             continue;
299         }
300         devname = g_strdup_printf("usart%zu", i);
301         object_initialize_child(OBJECT(dev), devname, &s->usart[i],
302                                 TYPE_AVR_USART);
303         qdev_prop_set_chr(DEVICE(&s->usart[i]), "chardev", serial_hd(i));
304         sbd = SYS_BUS_DEVICE(&s->usart[i]);
305         sysbus_realize(sbd, &error_abort);
306         sysbus_mmio_map(sbd, 0, OFFSET_DATA + mc->dev[USART(i)].addr);
307         connect_peripheral_irq(mc, sbd, 0, cpudev, USART_RXC_IRQ(i));
308         connect_peripheral_irq(mc, sbd, 1, cpudev, USART_DRE_IRQ(i));
309         connect_peripheral_irq(mc, sbd, 2, cpudev, USART_TXC_IRQ(i));
310         connect_power_reduction_gpio(s, mc, DEVICE(&s->usart[i]), idx);
311         g_free(devname);
312     }
313 
314     /* Timer */
315     for (i = 0; i < TIMER_MAX; i++) {
316         int idx = TIMER(i);
317         if (!mc->dev[idx].addr) {
318             continue;
319         }
320         if (!mc->dev[idx].is_timer16) {
321             create_unimplemented_device("avr-timer8",
322                                         OFFSET_DATA + mc->dev[idx].addr, 5);
323             create_unimplemented_device("avr-timer8-intmask",
324                                         OFFSET_DATA
325                                         + mc->dev[idx].intmask_addr, 1);
326             create_unimplemented_device("avr-timer8-intflag",
327                                         OFFSET_DATA
328                                         + mc->dev[idx].intflag_addr, 1);
329             continue;
330         }
331         devname = g_strdup_printf("timer%zu", i);
332         object_initialize_child(OBJECT(dev), devname, &s->timer[i],
333                                 TYPE_AVR_TIMER16);
334         object_property_set_uint(OBJECT(&s->timer[i]), "cpu-frequency-hz",
335                                  s->xtal_freq_hz, &error_abort);
336         sbd = SYS_BUS_DEVICE(&s->timer[i]);
337         sysbus_realize(sbd, &error_abort);
338         sysbus_mmio_map(sbd, 0, OFFSET_DATA + mc->dev[idx].addr);
339         sysbus_mmio_map(sbd, 1, OFFSET_DATA + mc->dev[idx].intmask_addr);
340         sysbus_mmio_map(sbd, 2, OFFSET_DATA + mc->dev[idx].intflag_addr);
341         connect_peripheral_irq(mc, sbd, 0, cpudev, TIMER_CAPT_IRQ(i));
342         connect_peripheral_irq(mc, sbd, 1, cpudev, TIMER_COMPA_IRQ(i));
343         connect_peripheral_irq(mc, sbd, 2, cpudev, TIMER_COMPB_IRQ(i));
344         connect_peripheral_irq(mc, sbd, 3, cpudev, TIMER_COMPC_IRQ(i));
345         connect_peripheral_irq(mc, sbd, 4, cpudev, TIMER_OVF_IRQ(i));
346         connect_power_reduction_gpio(s, mc, DEVICE(&s->timer[i]), idx);
347         g_free(devname);
348     }
349 
350     create_unimplemented_device("avr-twi",          OFFSET_DATA + 0x0b8, 6);
351     create_unimplemented_device("avr-adc",          OFFSET_DATA + 0x078, 8);
352     create_unimplemented_device("avr-ext-mem-ctrl", OFFSET_DATA + 0x074, 2);
353     create_unimplemented_device("avr-watchdog",     OFFSET_DATA + 0x060, 1);
354     create_unimplemented_device("avr-spi",          OFFSET_DATA + 0x04c, 3);
355     create_unimplemented_device("avr-eeprom",       OFFSET_DATA + 0x03f, 3);
356 }
357 
358 static Property atmega_props[] = {
359     DEFINE_PROP_UINT64("xtal-frequency-hz", AtmegaMcuState,
360                        xtal_freq_hz, 0),
361     DEFINE_PROP_END_OF_LIST()
362 };
363 
atmega_class_init(ObjectClass * oc,void * data)364 static void atmega_class_init(ObjectClass *oc, void *data)
365 {
366     DeviceClass *dc = DEVICE_CLASS(oc);
367 
368     dc->realize = atmega_realize;
369     device_class_set_props(dc, atmega_props);
370     /* Reason: Mapped at fixed location on the system bus */
371     dc->user_creatable = false;
372 }
373 
atmega168_class_init(ObjectClass * oc,void * data)374 static void atmega168_class_init(ObjectClass *oc, void *data)
375 {
376     AtmegaMcuClass *amc = ATMEGA_MCU_CLASS(oc);
377 
378     amc->cpu_type = AVR_CPU_TYPE_NAME("avr5");
379     amc->flash_size = 16 * KiB;
380     amc->eeprom_size = 512;
381     amc->sram_size = 1 * KiB;
382     amc->io_size = 256;
383     amc->gpio_count = 23;
384     amc->adc_count = 6;
385     amc->irq = irq168_328;
386     amc->dev = dev168_328;
387 };
388 
atmega328_class_init(ObjectClass * oc,void * data)389 static void atmega328_class_init(ObjectClass *oc, void *data)
390 {
391     AtmegaMcuClass *amc = ATMEGA_MCU_CLASS(oc);
392 
393     amc->cpu_type = AVR_CPU_TYPE_NAME("avr5");
394     amc->flash_size = 32 * KiB;
395     amc->eeprom_size = 1 * KiB;
396     amc->sram_size = 2 * KiB;
397     amc->io_size = 256;
398     amc->gpio_count = 23;
399     amc->adc_count = 6;
400     amc->irq = irq168_328;
401     amc->dev = dev168_328;
402 };
403 
atmega1280_class_init(ObjectClass * oc,void * data)404 static void atmega1280_class_init(ObjectClass *oc, void *data)
405 {
406     AtmegaMcuClass *amc = ATMEGA_MCU_CLASS(oc);
407 
408     amc->cpu_type = AVR_CPU_TYPE_NAME("avr51");
409     amc->flash_size = 128 * KiB;
410     amc->eeprom_size = 4 * KiB;
411     amc->sram_size = 8 * KiB;
412     amc->io_size = 512;
413     amc->gpio_count = 86;
414     amc->adc_count = 16;
415     amc->irq = irq1280_2560;
416     amc->dev = dev1280_2560;
417 };
418 
atmega2560_class_init(ObjectClass * oc,void * data)419 static void atmega2560_class_init(ObjectClass *oc, void *data)
420 {
421     AtmegaMcuClass *amc = ATMEGA_MCU_CLASS(oc);
422 
423     amc->cpu_type = AVR_CPU_TYPE_NAME("avr6");
424     amc->flash_size = 256 * KiB;
425     amc->eeprom_size = 4 * KiB;
426     amc->sram_size = 8 * KiB;
427     amc->io_size = 512;
428     amc->gpio_count = 54;
429     amc->adc_count = 16;
430     amc->irq = irq1280_2560;
431     amc->dev = dev1280_2560;
432 };
433 
434 static const TypeInfo atmega_mcu_types[] = {
435     {
436         .name           = TYPE_ATMEGA168_MCU,
437         .parent         = TYPE_ATMEGA_MCU,
438         .class_init     = atmega168_class_init,
439     }, {
440         .name           = TYPE_ATMEGA328_MCU,
441         .parent         = TYPE_ATMEGA_MCU,
442         .class_init     = atmega328_class_init,
443     }, {
444         .name           = TYPE_ATMEGA1280_MCU,
445         .parent         = TYPE_ATMEGA_MCU,
446         .class_init     = atmega1280_class_init,
447     }, {
448         .name           = TYPE_ATMEGA2560_MCU,
449         .parent         = TYPE_ATMEGA_MCU,
450         .class_init     = atmega2560_class_init,
451     }, {
452         .name           = TYPE_ATMEGA_MCU,
453         .parent         = TYPE_SYS_BUS_DEVICE,
454         .instance_size  = sizeof(AtmegaMcuState),
455         .class_size     = sizeof(AtmegaMcuClass),
456         .class_init     = atmega_class_init,
457         .abstract       = true,
458     }
459 };
460 
461 DEFINE_TYPES(atmega_mcu_types)
462