xref: /openbmc/u-boot/arch/nds32/dts/ae3xx.dts (revision d01806a8)
1b841b6e9Srick/dts-v1/;
2b841b6e9Srick/ {
3b841b6e9Srick	compatible = "nds32 ae3xx";
4b841b6e9Srick	#address-cells = <1>;
5b841b6e9Srick	#size-cells = <1>;
6b841b6e9Srick	interrupt-parent = <&intc>;
7b841b6e9Srick
8b841b6e9Srick	aliases {
9b841b6e9Srick		uart0 = &serial0;
10be71a179Srick		ethernet0 = &mac0;
117b1a50b7Srick		spi0 = &spi;
12b841b6e9Srick	} ;
13b841b6e9Srick
14b841b6e9Srick	chosen {
15b841b6e9Srick		/* bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug bootmem_debug memblock=debug loglevel=7"; */
16b841b6e9Srick		bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7";
17b841b6e9Srick		stdout-path = "uart0:38400n8";
18b841b6e9Srick		tick-timer = &timer0;
19b841b6e9Srick	};
20b841b6e9Srick
21b841b6e9Srick	memory@0 {
22b841b6e9Srick		device_type = "memory";
23b841b6e9Srick		reg = <0x00000000 0x40000000>;
24b841b6e9Srick	};
25b841b6e9Srick
267b1a50b7Srick	spiclk: virt_100mhz {
277b1a50b7Srick		#clock-cells = <0>;
287b1a50b7Srick		compatible = "fixed-clock";
297b1a50b7Srick		clock-frequency = <100000000>;
307b1a50b7Srick	};
317b1a50b7Srick
32b841b6e9Srick	cpus {
33b841b6e9Srick		#address-cells = <1>;
34b841b6e9Srick		#size-cells = <0>;
35b841b6e9Srick		cpu@0 {
36b841b6e9Srick			compatible = "andestech,n13";
37b841b6e9Srick			reg = <0>;
38b841b6e9Srick			/* FIXME: to fill correct frqeuency */
39b841b6e9Srick			clock-frequency = <60000000>;
40b841b6e9Srick		};
41b841b6e9Srick	};
42b841b6e9Srick
43b841b6e9Srick	intc: interrupt-controller {
44b841b6e9Srick		compatible = "andestech,atnointc010";
45b841b6e9Srick		#interrupt-cells = <1>;
46b841b6e9Srick		interrupt-controller;
47b841b6e9Srick	};
48b841b6e9Srick
49b841b6e9Srick	serial0: serial@f0300000 {
50b841b6e9Srick		compatible = "andestech,uart16550", "ns16550a";
51b841b6e9Srick		reg = <0xf0300000 0x1000>;
52b841b6e9Srick		interrupts = <7 4>;
53b841b6e9Srick		clock-frequency = <14745600>;
54b841b6e9Srick		reg-shift = <2>;
55b841b6e9Srick		reg-offset = <32>;
56b841b6e9Srick		no-loopback-test = <1>;
57b841b6e9Srick	};
58b841b6e9Srick
59b841b6e9Srick	timer0: timer@f0400000 {
60b841b6e9Srick		compatible = "andestech,atcpit100";
61b841b6e9Srick		reg = <0xf0400000 0x1000>;
62b841b6e9Srick		interrupts = <2 4>;
63b841b6e9Srick		clock-frequency = <30000000>;
64b841b6e9Srick	};
65b841b6e9Srick
66be71a179Srick	mac0: mac@e0100000 {
67be71a179Srick		compatible = "andestech,atmac100";
68be71a179Srick		reg = <0xe0100000 0x1000>;
69be71a179Srick		interrupts = <25 4>;
70be71a179Srick	};
71be71a179Srick
72febcd976SRick Chen	mmc0: mmc@f0e00000 {
73*866ab879SRick Chen		compatible = "andestech,atfsdc010";
74febcd976SRick Chen		max-frequency = <100000000>;
75febcd976SRick Chen		fifo-depth = <0x10>;
76febcd976SRick Chen		reg = <0xf0e00000 0x1000>;
77febcd976SRick Chen		interrupts = <17 4>;
78febcd976SRick Chen	};
79febcd976SRick Chen
80b841b6e9Srick	nor@0,0 {
81b841b6e9Srick		compatible = "cfi-flash";
82b841b6e9Srick		reg = <0x88000000 0x1000>;
83b841b6e9Srick		bank-width = <2>;
84b841b6e9Srick		device-width = <1>;
85b841b6e9Srick	};
86b841b6e9Srick
877b1a50b7Srick	spi: spi@f0b00000 {
887b1a50b7Srick		compatible = "andestech,atcspi200";
897b1a50b7Srick		reg = <0xf0b00000 0x1000>;
907b1a50b7Srick		#address-cells = <1>;
917b1a50b7Srick		#size-cells = <0>;
927b1a50b7Srick		num-cs = <1>;
937b1a50b7Srick		clocks = <&spiclk>;
947b1a50b7Srick		interrupts = <3 4>;
957b1a50b7Srick			flash@0 {
967b1a50b7Srick			compatible = "spi-flash";
977b1a50b7Srick			spi-max-frequency = <50000000>;
987b1a50b7Srick			reg = <0>;
997b1a50b7Srick			spi-cpol;
1007b1a50b7Srick			spi-cpha;
1017b1a50b7Srick		};
1027b1a50b7Srick	};
103b841b6e9Srick};
104