Searched +full:tegra210 +full:- +full:xusb (Results 1 – 25 of 32) sorted by relevance
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1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/usb/nvidia,tegra210-xusb.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: NVIDIA Tegra210 xHCI controller10 - Thierry Reding <thierry.reding@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>14 exposed by the Tegra XUSB pad controller.18 const: nvidia,tegra210-xusb22 - description: base and length of the xHCI host registers[all …]
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/usb/nvidia,tegra-xudc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: NVIDIA Tegra XUSB device mode controller (XUDC)14 - Nagarjuna Kristam <nkristam@nvidia.com>15 - JC Kuo <jckuo@nvidia.com>16 - Thierry Reding <treding@nvidia.com>21 - enum:22 - nvidia,tegra210-xudc # For Tegra210[all …]
1 # SPDX-License-Identifier: GPL-2.0-only2 obj-$(CONFIG_PHY_TEGRA_XUSB) += phy-tegra-xusb.o4 phy-tegra-xusb-y += xusb.o5 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_124_SOC) += xusb-tegra124.o6 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_132_SOC) += xusb-tegra124.o7 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_210_SOC) += xusb-tegra210.o8 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_186_SOC) += xusb-tegra186.o9 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_194_SOC) += xusb-tegra186.o10 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_234_SOC) += xusb-tegra186.o11 obj-$(CONFIG_PHY_TEGRA194_P2U) += phy-tegra194-p2u.o
1 // SPDX-License-Identifier: GPL-2.0-only3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.13 #include <linux/phy/tegra/xusb.h>22 #include "xusb.h"31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()[all …]
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause3 ---4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: NVIDIA Tegra210 XUSB pad controller10 - Thierry Reding <thierry.reding@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or22 super-speed USB. Other lanes are for various types of low-speed, full-speed[all …]
1 /dts-v1/;3 #include "tegra210.dtsi"6 model = "NVIDIA P2371-2180";7 compatible = "nvidia,p2371-2180", "nvidia,tegra210";10 stdout-path = &uarta;24 pcie-controller@01003000 {37 pinctrl-0 = <&padctl_default>;38 pinctrl-names = "default";41 xusb {42 nvidia,lanes = "otg-1", "otg-2";[all …]
1 #include <dt-bindings/clock/tegra210-car.h>2 #include <dt-bindings/gpio/tegra-gpio.h>3 #include <dt-bindings/memory/tegra210-mc.h>4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>5 #include <dt-bindings/interrupt-controller/arm-gic.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>9 compatible = "nvidia,tegra210";10 interrupt-parent = <&lic>;11 #address-cells = <2>;12 #size-cells = <2>;[all …]
1 Device tree binding for NVIDIA Tegra XUSB pad controller4 NOTE: It turns out that this binding isn't an accurate description of the XUSB7 needed for USB. For the new binding, see ../phy/nvidia,tegra-xusb-padctl.txt.10 The Tegra XUSB pad controller manages a set of lanes, each of which can be14 This document defines the device-specific binding for the XUSB pad controller.16 Refer to pinctrl-bindings.txt in this directory for generic information about17 pin controller device tree bindings and ../phy/phy-bindings.txt for details on21 --------------------22 - compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl".23 Otherwise, must contain '"nvidia,<chip>-xusb-padctl",[all …]
1 # SPDX-License-Identifier: GPL-2.02 obj-$(CONFIG_PINCTRL_TEGRA) += pinctrl-tegra.o3 obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o4 obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o5 obj-$(CONFIG_PINCTRL_TEGRA114) += pinctrl-tegra114.o6 obj-$(CONFIG_PINCTRL_TEGRA124) += pinctrl-tegra124.o7 obj-$(CONFIG_PINCTRL_TEGRA210) += pinctrl-tegra210.o8 obj-$(CONFIG_PINCTRL_TEGRA194) += pinctrl-tegra194.o9 obj-$(CONFIG_PINCTRL_TEGRA234) += pinctrl-tegra234.o10 obj-$(CONFIG_PINCTRL_TEGRA_XUSB) += pinctrl-tegra-xusb.o
1 # SPDX-License-Identifier: GPL-2.0+3 # (C) Copyright 2010-2015 Nvidia Corporation.5 # (C) Copyright 2000-200810 obj-y += spl.o11 obj-y += cpu.o13 obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o16 obj-y += ap.o17 obj-y += board.o board2.o18 obj-y += cache.o19 obj-y += clock.o[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra194-clock.h>3 #include <dt-bindings/gpio/tegra194-gpio.h>4 #include <dt-bindings/interrupt-controller/arm-gic.h>5 #include <dt-bindings/mailbox/tegra186-hsp.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>8 #include <dt-bindings/power/tegra194-powergate.h>9 #include <dt-bindings/reset/tegra194-reset.h>10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra210-car.h>3 #include <dt-bindings/gpio/tegra-gpio.h>4 #include <dt-bindings/memory/tegra210-mc.h>5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>7 #include <dt-bindings/reset/tegra210-car.h>8 #include <dt-bindings/interrupt-controller/arm-gic.h>9 #include <dt-bindings/thermal/tegra124-soctherm.h>10 #include <dt-bindings/soc/tegra-pmc.h>[all …]
1 // SPDX-License-Identifier: GPL-2.03 #include <dt-bindings/clock/tegra234-clock.h>4 #include <dt-bindings/gpio/tegra234-gpio.h>5 #include <dt-bindings/interrupt-controller/arm-gic.h>6 #include <dt-bindings/mailbox/tegra186-hsp.h>7 #include <dt-bindings/memory/tegra234-mc.h>8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>9 #include <dt-bindings/power/tegra234-powergate.h>10 #include <dt-bindings/reset/tegra234-reset.h>11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra186-clock.h>3 #include <dt-bindings/gpio/tegra186-gpio.h>4 #include <dt-bindings/interrupt-controller/arm-gic.h>5 #include <dt-bindings/mailbox/tegra186-hsp.h>6 #include <dt-bindings/memory/tegra186-mc.h>7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>8 #include <dt-bindings/power/tegra186-powergate.h>9 #include <dt-bindings/reset/tegra186-reset.h>10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>[all …]
1 // SPDX-License-Identifier: GPL-2.02 /dts-v1/;4 #include <dt-bindings/input/gpio-keys.h>5 #include <dt-bindings/input/linux-event-codes.h>6 #include <dt-bindings/mfd/max77620.h>8 #include "tegra210.dtsi"12 compatible = "nvidia,p3450-0000", "nvidia,tegra210";22 stdout-path = "serial0:115200n8";33 hvddio-pex-supply = <&vdd_1v8>;34 dvddio-pex-supply = <&vdd_pex_1v05>;[all …]
1 // SPDX-License-Identifier: GPL-2.03 #include <dt-bindings/gpio/tegra-gpio.h>4 #include <dt-bindings/input/input.h>5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>8 model = "NVIDIA Tegra210 P2597 I/O board";9 compatible = "nvidia,p2597", "nvidia,tegra210";23 avdd-dsi-csi-supply = <&vdd_dsi_csi>;33 avdd-io-hdmi-dp-supply = <&avdd_1v05>;34 vdd-hdmi-dp-pll-supply = <&vdd_1v8>;35 hdmi-supply = <&vdd_hdmi>;[all …]
1 // SPDX-License-Identifier: GPL-2.02 /dts-v1/;4 #include <dt-bindings/input/input.h>5 #include <dt-bindings/mfd/max77620.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>8 #include "tegra210.dtsi"12 compatible = "google,smaug-rev8", "google,smaug-rev7",13 "google,smaug-rev6", "google,smaug-rev5",14 "google,smaug-rev4", "google,smaug-rev3",15 "google,smaug-rev2", "google,smaug-rev1",[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.6 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt13 #include "../xusb-padctl-common.h"17 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>34 "xusb",36 "pcie-x1",37 "pcie-x4",74 TEGRA210_LANE("otg-0", 0x004, 0, 0x3, 0, otg),75 TEGRA210_LANE("otg-1", 0x004, 2, 0x3, 0, otg),[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.11 #include <linux/dma-mapping.h>20 #include <linux/phy/tegra/xusb.h>321 return readl(tegra->fpci_base + offset); in fpci_readl()327 writel(value, tegra->fpci_base + offset); in fpci_writel()332 return readl(tegra->ipfs_base + offset); in ipfs_readl()338 writel(value, tegra->ipfs_base + offset); in ipfs_writel()343 return readl(tegra->bar2_base + offset); in bar2_readl()349 writel(value, tegra->bar2_base + offset); in bar2_writel()[all …]
1 // SPDX-License-Identifier: GPL-2.0-only7 #include <linux/clk-provider.h>16 #include "clk-id.h"130 #define MASK(x) (BIT(x) - 1)207 #define XUSB(_name, _parents, _offset, \ macro743 …XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB…744 …XUSB("xusb_host_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TE…745 …XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO…746 …XUSB("xusb_falcon_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESE…747 …XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, te…[all …]
1 /* SPDX-License-Identifier: GPL-2.0+ */3 * (C) Copyright 2010-201410 /* PLL registers - there are several PLLs in the clock controller */18 /* PLL registers - there are several PLLs in the clock controller */38 * Most PLLs use the clk_pll structure, but some have a simpler two-member39 * structure for which we use clk_pll_simple. The reason for this non-75 uint crc_reserved2[8]; /* reserved_2[8], 0x60-7C */85 uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */87 uint crc_reserved20[32]; /* _reserved_20, 0x200-27c */105 uint crc_reserved21[17]; /* _reserved_21, 0x2b0-2f0 */[all …]
1 // SPDX-License-Identifier: GPL-2.07 * Copyright (c) 2008-2009, NVIDIA Corporation.9 * Copyright (c) 2013-2014, NVIDIA Corporation.12 #define pr_fmt(fmt) "tegra-pcie: " fmt21 #include <power-domain.h>33 #include <asm/arch-tegra/xusb-padctl.h>34 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>41 * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be163 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit243 writel(value, pcie->afi.start + offset); in afi_writel()[all …]
1 /* SPDX-License-Identifier: GPL-2.0+ */12 * drivers and board-specific code within U-Boot. It aims to reduce the13 * amount of FDT munging required within U-Boot itself, so that driver code27 #define FDT_ADDR_T_NONE (-1U)32 #define FDT_ADDR_T_NONE (-1U)59 * be equal to: end - start + 1.93 * t: is 1 if the address is aliased (for non-relocatable I/O) below 1MB96 * bbbbbbbb: is the 8-bit Bus Number97 * ddddd: is the 5-bit Device Number98 * fff: is the 3-bit Function Number[all …]
1 // SPDX-License-Identifier: GPL-2.0+30 * good reason why driver-model conversion is infeasible. Examples include36 COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"),37 COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),38 COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),39 COMPAT(NVIDIA_TEGRA124_XUSB_PADCTL, "nvidia,tegra124-xusb-padctl"),40 COMPAT(NVIDIA_TEGRA210_XUSB_PADCTL, "nvidia,tegra210-xusb-padctl"),42 COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"),43 COMPAT(SAMSUNG_EXYNOS_USB_PHY, "samsung,exynos-usb-phy"),44 COMPAT(SAMSUNG_EXYNOS5_USB3_PHY, "samsung,exynos5250-usb3-phy"),[all …]
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