asm/arch-tegra/clk_rst.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
3  *  (C) Copyright 2010-2014
10 /* PLL registers - there are several PLLs in the clock controller */
18 /* PLL registers - there are several PLLs in the clock controller */
38  * Most PLLs use the clk_pll structure, but some have a simpler two-member
39  * structure for which we use clk_pll_simple. The reason for this non-
75 	uint crc_reserved2[8];		/* reserved_2[8],	0x60-7C */
85 	uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0...	0x100-1fc */
87 	uint crc_reserved20[32];	/* _reserved_20,	0x200-27c */
105 	uint crc_reserved21[17];	/* _reserved_21,	0x2b0-2f0 */
109 	uint crc_reserved22[2];		/* _reserved_22,	0x2f8-2fc */
141 	uint crc_reserved33[9];		/* _reserved_33,        0x38c-3ac */
142 	uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW];	/* 0x3B0-0x42C */
182 	uint crs_reserved_50[7];	/* _reserved_50, 0x4CC-0x4E4 */
213 	u32 _rsv32[4];                  /*                    0x560-0x56c */
215 	u32 _rsv32_1[7];		/*                      0x574-58c */
219 	/* Tegra124+ - skip to 0x600 here for new CLK_SOURCE_ regs */
220 	uint _rsrv32_2[25];			/* _0x59C - 0x5FC */
221 	uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x67C */
223 	/* Tegra210 - skip to 0x694 here for new CLK_SOURCE_ regs */
224 	uint crc_reserved61[5];	/* _reserved_61, 0x680 - 0x690 */
229 	uint crc_clk_src_y[TEGRA_CLK_SOURCES_Y]; /* SPARE1, etc, 0x694-0x6D8 */
314  * CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits
316  * the 8-bit cases (the divider_bits value returned by
329 /* Note: See comment for MASK_BITS_31_28 in arch-tegra/clock.h */