Searched +full:tegra20 +full:- +full:dsi (Results 1 – 25 of 31) sorted by relevance
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1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Thierry Reding <thierry.reding@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>16 - enum:17 - nvidia,tegra20-dsi18 - nvidia,tegra30-dsi19 - nvidia,tegra114-dsi[all …]
1 # SPDX-License-Identifier: GPL-2.0-only3 ---4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Thierry Reding <thierry.reding@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>13 description: The host1x top-level node defines a number of children, each19 - enum:20 - nvidia,tegra20-host1x21 - nvidia,tegra30-host1x[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vi.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Thierry Reding <thierry.reding@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>15 pattern: "^vi@[0-9a-f]+$"19 - const: nvidia,tegra20-vi20 - const: nvidia,tegra30-vi21 - const: nvidia,tegra114-vi[all …]
4 - compatible: "nvidia,tegra<chip>-host1x"5 - reg: Physical base address and length of the controller's registers.6 - interrupts: The interrupt outputs from the controller.7 - #address-cells: The number of cells used to represent physical base addresses9 - #size-cells: The number of cells used to represent the size of an address11 - ranges: The mapping of the host1x address space to the CPU address space.12 - clocks: Must contain one entry, for the module clock.13 See ../clocks/clock-bindings.txt for details.14 - resets: Must contain an entry for each entry in reset-names.16 - reset-names: Must include the following entries:[all …]
1 #include <dt-bindings/clock/tegra114-car.h>2 #include <dt-bindings/gpio/tegra-gpio.h>3 #include <dt-bindings/memory/tegra114-mc.h>4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>5 #include <dt-bindings/interrupt-controller/arm-gic.h>11 interrupt-parent = <&lic>;14 compatible = "nvidia,tegra114-host1x", "simple-bus";20 reset-names = "host1x";22 #address-cells = <1>;23 #size-cells = <1>;[all …]
1 #include <dt-bindings/clock/tegra20-car.h>2 #include <dt-bindings/gpio/tegra-gpio.h>3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>4 #include <dt-bindings/interrupt-controller/arm-gic.h>9 compatible = "nvidia,tegra20";10 interrupt-parent = <&lic>;13 compatible = "nvidia,tegra20-host1x", "simple-bus";19 reset-names = "host1x";21 #address-cells = <1>;22 #size-cells = <1>;[all …]
1 #include <dt-bindings/clock/tegra210-car.h>2 #include <dt-bindings/gpio/tegra-gpio.h>3 #include <dt-bindings/memory/tegra210-mc.h>4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>5 #include <dt-bindings/interrupt-controller/arm-gic.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>10 interrupt-parent = <&lic>;11 #address-cells = <2>;12 #size-cells = <2>;14 pcie-controller@01003000 {[all …]
1 #include <dt-bindings/clock/tegra30-car.h>2 #include <dt-bindings/gpio/tegra-gpio.h>3 #include <dt-bindings/memory/tegra30-mc.h>4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>5 #include <dt-bindings/interrupt-controller/arm-gic.h>11 interrupt-parent = <&lic>;13 pcie-controller@00003000 {14 compatible = "nvidia,tegra30-pcie";19 reg-names = "pads", "afi", "cs";22 interrupt-names = "intr", "msi";[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra30-car.h>3 #include <dt-bindings/gpio/tegra-gpio.h>4 #include <dt-bindings/memory/tegra30-mc.h>5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>6 #include <dt-bindings/interrupt-controller/arm-gic.h>7 #include <dt-bindings/soc/tegra-pmc.h>8 #include <dt-bindings/thermal/thermal.h>10 #include "tegra30-peripherals-opp.dtsi"14 interrupt-parent = <&lic>;[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra20-car.h>3 #include <dt-bindings/gpio/tegra-gpio.h>4 #include <dt-bindings/memory/tegra20-mc.h>5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>6 #include <dt-bindings/interrupt-controller/arm-gic.h>7 #include <dt-bindings/soc/tegra-pmc.h>9 #include "tegra20-peripherals-opp.dtsi"12 compatible = "nvidia,tegra20";13 interrupt-parent = <&lic>;[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra114-car.h>3 #include <dt-bindings/gpio/tegra-gpio.h>4 #include <dt-bindings/memory/tegra114-mc.h>5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>6 #include <dt-bindings/interrupt-controller/arm-gic.h>7 #include <dt-bindings/soc/tegra-pmc.h>11 interrupt-parent = <&lic>;12 #address-cells = <1>;13 #size-cells = <1>;[all …]
1 NVIDIA Tegra20 Clock And Reset Controller4 Documentation/devicetree/bindings/clock/clock-bindings.txt10 - compatible : Should be "nvidia,tegra20-car"11 - reg : Should contain CAR registers location and length12 - clocks : Should contain phandle and clock specifiers for two clocks:13 the 32 KHz "32k_in", and the board-specific oscillator "osc".14 - #clock-cells : Should be 1.77 48 dsi167 compatible = "nvidia,tegra20-car";169 #clock-cells = <1>;[all …]
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Thierry Reding <thierry.reding@gmail.com>11 - Jonathan Hunter <jonathanh@nvidia.com>16 - nvidia,tegra20-pmc17 - nvidia,tegra30-pmc18 - nvidia,tegra114-pmc19 - nvidia,tegra124-pmc[all …]
11 supports the built-in GPU, comprised of the gr2d and gr3d engines. Starting15 The drm/tegra driver supports NVIDIA Tegra SoC generations since Tegra20. It18 - A host1x driver that provides infrastructure and access to the host1x21 - A KMS driver that supports the display controllers as well as a number of22 outputs, such as RGB, HDMI, DSI, and DisplayPort.24 - A set of custom userspace IOCTLs that can be used to submit jobs to the40 device using a driver-provided function which will set up the bits specific to48 -------------------------------50 .. kernel-doc:: include/linux/host1x.h52 .. kernel-doc:: drivers/gpu/host1x/bus.c[all …]
1 // SPDX-License-Identifier: GPL-2.0-only7 #include <linux/clk-provider.h>15 #include <dt-bindings/clock/tegra20-car.h>18 #include "clk-id.h"444 { .dev_id = "tegra20-ac97", .dt_id = TEGRA20_CLK_AC97 },445 { .dev_id = "tegra-apbdma", .dt_id = TEGRA20_CLK_APBDMA },446 { .dev_id = "rtc-tegra", .dt_id = TEGRA20_CLK_RTC },448 { .dev_id = "tegra-kbc", .dt_id = TEGRA20_CLK_KBC },450 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_VCP },451 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_BSEA },[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra186-clock.h>3 #include <dt-bindings/gpio/tegra186-gpio.h>4 #include <dt-bindings/interrupt-controller/arm-gic.h>5 #include <dt-bindings/mailbox/tegra186-hsp.h>6 #include <dt-bindings/memory/tegra186-mc.h>7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>8 #include <dt-bindings/power/tegra186-powergate.h>9 #include <dt-bindings/reset/tegra186-reset.h>10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra210-car.h>3 #include <dt-bindings/gpio/tegra-gpio.h>4 #include <dt-bindings/memory/tegra210-mc.h>5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>7 #include <dt-bindings/reset/tegra210-car.h>8 #include <dt-bindings/interrupt-controller/arm-gic.h>9 #include <dt-bindings/thermal/tegra124-soctherm.h>10 #include <dt-bindings/soc/tegra-pmc.h>[all …]
1 // SPDX-License-Identifier: GPL-2.0-only4 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.27 #include <asm/dma-iommu.h>76 struct drm_device *drm = old_state->dev; in tegra_atomic_commit_tail()77 struct tegra_drm *tegra = drm->dev_private; in tegra_atomic_commit_tail()79 if (tegra->hub) { in tegra_atomic_commit_tail()108 return -ENOMEM; in tegra_drm_open()110 idr_init_base(&fpriv->legacy_contexts, 1); in tegra_drm_open()111 xa_init_flags(&fpriv->contexts, XA_FLAGS_ALLOC1); in tegra_drm_open()112 xa_init(&fpriv->syncpoints); in tegra_drm_open()[all …]
1 // SPDX-License-Identifier: GPL-2.0+4 * (C) Copyright 2010-20158 /* Tegra20 Clock control functions */15 #include <asm/arch-tegra/clk_rst.h>16 #include <asm/arch-tegra/timer.h>21 * Clock types that we can use as a source. The Tegra20 has muxes for the40 CLOCK_TYPE_PCMT16, /* CLOCK_TYPE_PCMT with 16-bit divider */45 CLOCK_TYPE_NONE = -1, /* invalid clock type */73 * not in the header file since it is for purely internal use - we want155 PERIPHC_NONE = -1,[all …]
13 to display a command-line console or splash screen. Enabling this24 This driver can be use with "simple-panel" and26 (leds/backlight/pwm-backlight.txt)34 This driver can be used with "simple-panel" and36 (leds/backlight/gpio-backlight.txt)39 bool "Support 8-bit-per-pixel displays"43 Support drawing text and bitmaps onto a 8-bit-per-pixel display.49 bool "Support 16-bit-per-pixel displays"53 Support drawing text and bitmaps onto a 16-bit-per-pixel display.59 bool "Support 32-bit-per-pixel displays"[all …]
1 // SPDX-License-Identifier: GPL-2.0+30 * good reason why driver-model conversion is infeasible. Examples include36 COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"),37 COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),38 COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),39 COMPAT(NVIDIA_TEGRA124_XUSB_PADCTL, "nvidia,tegra124-xusb-padctl"),40 COMPAT(NVIDIA_TEGRA210_XUSB_PADCTL, "nvidia,tegra210-xusb-padctl"),42 COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"),43 COMPAT(SAMSUNG_EXYNOS_USB_PHY, "samsung,exynos-usb-phy"),44 COMPAT(SAMSUNG_EXYNOS5_USB3_PHY, "samsung,exynos5250-usb3-phy"),[all …]
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1 /* SPDX-License-Identifier: GPL-2.0+ */12 * drivers and board-specific code within U-Boot. It aims to reduce the13 * amount of FDT munging required within U-Boot itself, so that driver code27 #define FDT_ADDR_T_NONE (-1U)32 #define FDT_ADDR_T_NONE (-1U)59 * be equal to: end - start + 1.93 * t: is 1 if the address is aliased (for non-relocatable I/O) below 1MB96 * bbbbbbbb: is the 8-bit Bus Number97 * ddddd: is the 5-bit Device Number98 * fff: is the 3-bit Function Number[all …]
1 // SPDX-License-Identifier: GPL-2.0-only6 * Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.12 #define pr_fmt(fmt) "tegra-pmc: " fmt14 #include <linux/arm-smccc.h>16 #include <linux/clk-provider.h>18 #include <linux/clk/clk-conf.h>37 #include <linux/pinctrl/pinconf-generic.h>56 #include <dt-bindings/interrupt-controller/arm-gic.h>57 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>58 #include <dt-bindings/gpio/tegra186-gpio.h>[all …]
1 // SPDX-License-Identifier: GPL-2.0-only21 #include <media/v4l2-dv-timings.h>22 #include <media/v4l2-event.h>23 #include <media/v4l2-fh.h>24 #include <media/v4l2-fwnode.h>25 #include <media/v4l2-ioctl.h>26 #include <media/videobuf2-dma-contig.h>36 * struct tegra_vi_graph_entity - Entity in the video graph72 for (i = offset; i < vi->soc->nformats; ++i) { in tegra_get_format_idx_by_code()73 if (vi->soc->video_formats[i].code == code) in tegra_get_format_idx_by_code()[all …]