mach-tegra/tegra20/clock.c

1 // SPDX-License-Identifier: GPL-2.0+
4  * (C) Copyright 2010-2015
8 /* Tegra20 Clock control functions */
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/timer.h>
21  * Clock types that we can use as a source. The Tegra20 has muxes for the
40 	CLOCK_TYPE_PCMT16,	/* CLOCK_TYPE_PCMT with 16-bit divider */
45 	CLOCK_TYPE_NONE = -1,	/* invalid clock type */
73  * not in the header file since it is for purely internal use - we want
155 	PERIPHC_NONE = -1,
238  *	SPDIF - which is both 0x08 and 0x0c
241 #define NONE(name) (-1)
305 	NONE(DSI),
398 	reg = readl(&clkrst->crc_osc_ctrl);  in clock_get_osc_freq()
411 	assert(internal_id != -1);  in get_periph_source_reg()
412 	return &clkrst->crc_clk_src[internal_id];  in get_periph_source_reg()
421 		return -1;  in get_periph_clock_info()
425 		return -1;  in get_periph_clock_info()
429 		return -1;  in get_periph_clock_info()
432 	 * Special cases here for the clock with a 4-bit source mux and I2C  in get_periph_clock_info()
433 	 * with its 16-bit divisor  in get_periph_clock_info()
476  * @return mux value (0-4, or -1 if not found)
504 	return -1;  in get_periph_clock_source()
511 	u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];  in clock_set_enable()
528 	u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];  in reset_set_enable()
547  * @param clk_id	Clock ID according to tegra20 device tree binding
584 	 * TODO: Can we calculate these values instead of hard-coding?  in clock_early_init()
666 	} while (--timeout);  in tegra_plle_train()
670 		return -ETIMEDOUT;  in tegra_plle_train()
725 	} while (--timeout);  in tegra_plle_enable()
729 		return -ETIMEDOUT;  in tegra_plle_enable()
770 	{ -1, },