| /openbmc/linux/drivers/memory/ |
| H A D | jedec_ddr_data.c | 41 .tRRD = 10000,
62 .tRRD = 10000,
83 .tRRD = 10000,
104 .tRRD = 10000,
125 .tRRD = 2,
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| H A D | of_memory.c | 42 ret |= of_property_read_u32(np, "tRRD-min-tck", &min->tRRD); in of_get_min_tck()
74 ret |= of_property_read_u32(np, "tRRD", &tim->tRRD); in of_do_get_timings()
176 ret |= of_property_read_u32(np, "tRRD-min-tck", &min->tRRD); in of_lpddr3_get_min_tck()
222 ret |= of_property_read_u32(np, "tRRD", &tim->tRRD); in of_lpddr3_do_get_timings()
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| H A D | jedec_ddr.h | 154 u32 tRRD; member
178 u32 tRRD; member
229 u32 tRRD; member
258 u32 tRRD; member
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| /openbmc/linux/arch/arm/boot/dts/ti/omap/ |
| H A D | elpida_ecb240abacn.dtsi | 16 tRRD-min-tck = <2>;
32 tRRD = <10000>;
54 tRRD = <10000>;
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| /openbmc/u-boot/arch/arm/mach-omap2/omap4/ |
| H A D | emif.c | 30 .tRRD = 10,
54 .tRRD = 10,
83 .tRRD = 2,
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| H A D | sdram_elpida.c | 197 .tRRD = 10,
220 .tRRD = 10,
243 .tRRD = 10,
265 .tRRD = 2,
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| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/ |
| H A D | jedec,lpddr2.yaml | 49 tRRD-min-tck:
155 tRRD-min-tck = <2>;
171 tRRD = <10000>;
192 tRRD = <10000>;
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| H A D | jedec,lpddr3.yaml | 123 tRRD-min-tck:
211 tRRD-min-tck = <2>;
235 tRRD = <6000>;
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| H A D | jedec,lpddr2-timings.yaml | 67 tRRD:
127 tRRD = <10000>;
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| H A D | jedec,lpddr3-timings.yaml | 89 tRRD:
149 tRRD = <6000>;
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| /openbmc/u-boot/arch/arm/mach-omap2/omap5/ |
| H A D | emif.c | 31 .tRRD = 10,
60 .tRRD = 2,
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| /openbmc/u-boot/board/work-microwave/work_92105/ |
| H A D | work_92105_spl.c | 30 .trrd = 1,
50 .trrd = 1,
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| /openbmc/u-boot/arch/arm/mach-sunxi/dram_timings/ |
| H A D | ddr2_v3s.c | 12 u8 trrd = max(ns_to_t(10), 2); in mctl_set_timing_params() local
64 writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) | in mctl_set_timing_params()
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| H A D | lpddr3_stock.c | 12 u8 trrd = max(ns_to_t(10), 2); in mctl_set_timing_params() local
63 writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) | in mctl_set_timing_params()
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| H A D | ddr3_1333.c | 12 u8 trrd = max(ns_to_t(10), 4); in mctl_set_timing_params() local
67 writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) | in mctl_set_timing_params()
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| /openbmc/u-boot/drivers/ram/rockchip/ |
| H A D | dmc-rk3368.c | 498 pctl_timing->trrd = max(4u, ps_to_tCK(7500, freq)); in pctl_calc_timings()
523 * The controller can represent tFAW as 4x, 5x or 6x tRRD only. in pctl_calc_timings()
526 * tRRD to allow us to operate on a 6x multiplier for tFAW. in pctl_calc_timings()
529 if (tCK_to_ps(pctl_timing->trrd * 6, freq) < tfaw_as_ps) { in pctl_calc_timings()
530 /* If tFAW is > 6 x tRRD, we need to stretch tRRD */ in pctl_calc_timings()
531 pctl_timing->trrd = ps_to_tCK(DIV_ROUND_UP(40000, 6), freq); in pctl_calc_timings()
533 } else if (tCK_to_ps(pctl_timing->trrd * 5, freq) < tfaw_as_ps) { in pctl_calc_timings()
535 } else if (tCK_to_ps(pctl_timing->trrd * 4, freq) < tfaw_as_ps) { in pctl_calc_timings()
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| /openbmc/u-boot/include/ |
| H A D | spd.h | 43 unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */ member
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| /openbmc/u-boot/doc/device-tree-bindings/misc/ |
| H A D | intel,baytrail-fsp.txt | 85 - fsp,dimm-trrd
148 fsp,dimm-trrd = <6>;
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| /openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | sdram_rk3036.h | 56 u32 trrd; member
253 u32 trrd; member
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| H A D | sdram.h | 59 u32 trrd; member
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| /openbmc/u-boot/arch/arm/mach-imx/mx6/ |
| H A D | ddr.c | 998 u8 tcke, tcksrx, tcksre, trrd; in mx6_lpddr2_cfg() local
1047 trrd = DIV_ROUND_UP(10000, clkper) - 1; in mx6_lpddr2_cfg()
1094 debug("trrd=%d\n", trrd); in mx6_lpddr2_cfg()
1143 mmdc0->mdcfg2 = (trtp << 6) | (twtr << 3) | trrd; in mx6_lpddr2_cfg()
1228 u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd; in mx6_ddr3_cfg() local
1305 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1; in mx6_ddr3_cfg()
1308 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1; in mx6_ddr3_cfg()
1316 trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1; in mx6_ddr3_cfg()
1319 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1; in mx6_ddr3_cfg()
1371 debug("trrd=%d\n", trrd); in mx6_ddr3_cfg()
[all …]
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| /openbmc/u-boot/arch/arm/include/asm/arch-vf610/ |
| H A D | ddrmc-vf610.h | 20 u8 trrd; member
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| /openbmc/u-boot/board/timll/devkit3250/ |
| H A D | devkit3250_spl.c | 37 .trrd = 1,
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| /openbmc/u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 130 struct dram_sun9i_timing tRRD; member
390 const u32 tRRD = MAX(para->tRRD.ck, PS2CYCLES_ROUNDUP(para->tRRD.ps)); in mctl_channel_init() local
549 (MCTL_DIV2(tRRD) << 8) | (MCTL_DIV2(tRP) << 0), in mctl_channel_init()
641 writel((tRC << 26) | (tRRD << 22) | (tRAS << 16) | in mctl_channel_init()
900 .tRRD = { .ck = 4, .ps = 7500 }, in sunxi_dram_init()
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| H A D | dram_sun8i_a83t.c | 94 u8 trrd = max(ns_to_t(10), 4); in auto_set_timing_para() local
146 trrd = max(ns_to_t(10), 2); in auto_set_timing_para()
178 reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0); in auto_set_timing_para()
|