| /openbmc/linux/drivers/eisa/ |
| H A D | eisa.ids | 6 # Marc Zyngier <maz@wild-wind.fr.eu.org>
10 ABP0510 "Advansys ABP-510 ISA SCSI Host Adapter"
11 ABP0540 "Advansys ABP-540/542 ISA SCSI Host Adapter"
12 ABP7401 "AdvanSys ABP-740/742 EISA Single Channel SCSI Host Adapter"
13 ABP7501 "AdvanSys ABP-750/752 EISA Dual Channel SCSI Host Adapter"
14 ACC1200 "ACCTON EtherCombo-32 Ethernet Adapter"
15 ACC120A "ACCTON EtherCombo-32 Ethernet Adapter"
18 ACE1010 "ACME Super Fast System Board"
22 ACE4010 "ACME Tape Controller"
24 ACE6010 "ACME Disk Controller"
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/arm/hisilicon/controller/ |
| H A D | sysctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/hisilicon/controller/sysctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Hisilicon system controller
10 - Wei Xu <xuwei5@hisilicon.com>
13 The Hisilicon system controller is used on many Hisilicon boards, it can be
14 used to assist the slave core startup, reboot the system, etc.
16 There are some variants of the Hisilicon system controller, such as HiP01,
17 Hi3519, Hi6220 system controller, each of them is mostly compatible with the
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| /openbmc/linux/drivers/soc/renesas/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
59 #comment "Renesas ARM SoCs System Type"
67 bool "ARM32 Platform support for R-Car E2"
73 bool "ARM32 Platform support for R-Car H1"
82 bool "ARM32 Platform support for R-Car H2"
90 bool "ARM32 Platform support for R-Car M1A"
95 bool "ARM32 Platform support for R-Car M2-N"
102 bool "ARM32 Platform support for R-Car M2-W"
109 bool "ARM32 Platform support for R-Car V2H"
115 bool "ARM32 Platform support for R-Mobile A1"
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/arm/keystone/ |
| H A D | ti,sci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI controller
10 - Nishanth Menon <nm@ti.com>
15 management of the System on Chip (SoC) system. These include various system
18 An example of such an SoC is K2G, which contains the system control hardware
19 block called Power Management Micro Controller (PMMC). This hardware block is
25 The TI-SCI node describes the Texas Instrument's System Controller entity node.
29 relationship between the TI-SCI parent node to the child node.
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/arm/marvell/ |
| H A D | mvebu-system-controller.txt | 1 MVEBU System Controller
2 -----------------------
7 - compatible: one of:
8 - "marvell,orion-system-controller"
9 - "marvell,armada-370-xp-system-controller"
10 - "marvell,armada-375-system-controller"
11 - reg: Should contain system controller registers location and length.
15 system-controller@d0018200 {
16 compatible = "marvell,armada-370-xp-system-controller";
|
| H A D | ap80x-system-controller.txt | 1 Marvell Armada AP80x System Controller
5 7K/8K/931x SoCs. It contains system controllers, which provide several
6 registers giving access to numerous features: clocks, pin-muxing and
8 these system controllers.
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the AP80x system controller
14 SYSTEM CONTROLLER 0
18 -------
21 The Device Tree node representing the AP806/AP807 system controller
24 - 0: reference clock of CPU cluster 0
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| /openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | berlin,pinctrl.txt | 1 * Pin-controller driver for the Marvell Berlin SoCs
3 Pin control registers are part of both chip controller and system
4 controller register sets. Pin controller nodes should be a sub-node of
5 either the chip controller or system controller node. The pins
9 A pin-controller node should contain subnodes representing the pin group
14 is called a 'function' in the pin-controller subsystem.
17 - compatible: should be one of:
18 "marvell,berlin2-soc-pinctrl",
19 "marvell,berlin2-system-pinctrl",
20 "marvell,berlin2cd-soc-pinctrl",
[all …]
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| /openbmc/u-boot/arch/powerpc/include/asm/ |
| H A D | immap_83xx.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2004-2011 Freescale Semiconductor, Inc.
32 * System configuration registers
47 u32 sgprl; /* System General Purpose Register Low */
48 u32 sgprh; /* System General Purpose Register High */
49 u32 spridr; /* System Part and Revision ID Register */
51 u32 spcr; /* System Priority Configuration Register */
52 u32 sicrl; /* System I/O Configuration Register Low */
53 u32 sicrh; /* System I/O Configuration Register High */
55 u32 sidcr0; /* System I/O Delay Configuration Register 0 */
[all …]
|
| /openbmc/qemu/docs/system/ |
| H A D | target-mips.rst | 1 .. _MIPS-System-emulator:
3 MIPS System emulator
4 --------------------
6 Four executables cover simulation of 32 and 64-bit MIPS systems in both
7 endian options, ``qemu-system-mips``, ``qemu-system-mipsel``
8 ``qemu-system-mips64`` and ``qemu-system-mips64el``. Five different
11 - The MIPS Malta prototype board \"malta\"
13 - An ACER Pica \"pica61\". This machine needs the 64-bit emulator.
15 - MIPS emulator pseudo board \"mipssim\"
17 - A MIPS Magnum R4000 machine \"magnum\". This machine needs the
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/reset/ |
| H A D | ti,sci-reset.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/ti,sci-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI reset controller
10 - Nishanth Menon <nm@ti.com>
13 Some TI SoCs contain a system controller (like the Power Management Micro
14 Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
16 between the host processor running an OS and the system controller happens
17 through a protocol called TI System Control Interface (TI-SCI protocol).
[all …]
|
| /openbmc/u-boot/drivers/reset/ |
| H A D | Kconfig | 1 menu "Reset Controller Support"
7 Enable support for the reset controller driver class. Many hardware
9 reset controller hardware module within the chip. In U-Boot, reset
10 controller drivers allow control over these reset signals. In some
19 Enable support for a test reset controller implementation, which
28 Say Y if you want to control reset signals provided by system config
39 bool "Enable Tegra CAR-based reset driver"
42 Enable support for manipulating Tegra's on-SoC reset signals via
43 direct register access to the Tegra CAR (Clock And Reset controller).
46 bool "Enable Tegra186 BPMP-based reset driver"
[all …]
|
| /openbmc/u-boot/include/ |
| H A D | syscon.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
14 * struct syscon_uc_info - Information stored by the syscon UCLASS_UCLASS
16 * @regmap: Register map for this controller
26 #define syscon_get_ops(dev) ((struct syscon_ops *)(dev)->driver->ops)
30 * We don't support 64-bit machines. If they are so resource-contrained that
34 * Update: 64-bit is now supported and we have an education crisis.
42 * syscon_get_regmap() - Get access to a register map
46 * @return 0 if OK, -ve on error
51 * syscon_get_regmap_by_driver_data() - Look up a controller by its ID
53 * Each system controller can be accessed by its driver data, which is
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|
| /openbmc/linux/Documentation/devicetree/bindings/mfd/ |
| H A D | syscon.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: System Controller Registers R/W
10 System controller node represents a register region containing a set
12 represent as any specific type of device. The typical use-case is
13 for some other node's driver, or platform-specific code, to acquire
20 - Lee Jones <lee@kernel.org>
27 - syscon
30 - compatible
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|
| H A D | ti,j721e-system-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mfd/ti,j721e-system-controller.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI J721e System Controller Registers R/W
12 System controller node represents a register region containing a set
14 represent as any specific type of device. The typical use-case is
15 for some other node's driver, or platform-specific code, to acquire
22 - Kishon Vijay Abraham I <kishon@ti.com>
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/cache/ |
| H A D | socionext,uniphier-system-cache.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier outer cache controller
10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11 controller system. All of them have a level 2 cache controller, and some
12 have a level 3 cache controller as well.
15 - Masahiro Yamada <yamada.masahiro@socionext.com>
19 const: socionext,uniphier-system-cache
[all …]
|
| /openbmc/linux/Documentation/ABI/testing/ |
| H A D | sysfs-devices-edac | 1 What: /sys/devices/system/edac/mc/mc*/reset_counters
3 Contact: linux-edac@vger.kernel.org
4 Description: This write-only control file will zero all the statistical
5 counters for UE and CE errors on the given memory controller.
12 What: /sys/devices/system/edac/mc/mc*/seconds_since_reset
14 Contact: linux-edac@vger.kernel.org
19 What: /sys/devices/system/edac/mc/mc*/mc_name
21 Contact: linux-edac@vger.kernel.org
22 Description: This attribute file displays the type of memory controller
25 What: /sys/devices/system/edac/mc/mc*/size_mb
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|
| /openbmc/u-boot/doc/device-tree-bindings/sysreset/ |
| H A D | ti,sci-sysreset.txt | 1 Texas Instruments TI SCI System Reset Controller
4 Some TI SoCs contain a system controller (like the SYSFW, etc...) that is
6 Communication between the host processor running an OS and the system
7 controller happens through a protocol known as TI SCI [1].
11 System Reset Controller Node
13 The sysreset controller node represents the reset for the overall SoC
18 --------------------
19 - compatible: Must be "ti,sci-sysreset"
22 ----------------
24 compatible = "ti,am654-system-controller";
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|
| /openbmc/linux/drivers/input/touchscreen/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
20 support for the built-in touchscreen.
25 module will be called 88pm860x-ts.
33 ADS7846/TSC2046/AD7873 or ADS7843/AD7843 controller,
34 and your board-specific setup code includes that in its
51 AD7877 controller, and your board-specific initialization
60 tristate "Analog Devices AD7879-1/AD7889-1 touchscreen interface"
63 the AD7879-1/AD7889-1 controller.
75 Say Y here if you have AD7879-1/AD7889-1 hooked to an I2C bus.
78 module will be called ad7879-i2c.
[all …]
|
| /openbmc/linux/drivers/usb/typec/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
4 tristate "USB Type-C Support"
6 USB Type-C Specification defines a cable and connector for USB where
8 be Type-A plug on one end of the cable and Type-B plug on the other.
9 Determination of the host-to-device relationship happens through a
10 specific Configuration Channel (CC) which goes through the USB Type-C
12 Accessory Modes - Analog Audio and Debug - and if USB Power Delivery
22 USB Type-C connector, however it is mostly used together with USB
23 Type-C connectors.
25 USB Type-C and USB Power Delivery Specifications define a set of state
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | ti,sci-inta.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-inta.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lokesh Vutla <lokeshvutla@ti.com>
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
17 which handles the termination of system events to that they can
18 be coherently processed by the host(s) in the system. A maximum
22 +-----------------------------------------+
24 | +--------------+ +------------+ |
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|
| /openbmc/linux/Documentation/devicetree/bindings/sram/ |
| H A D | allwinner,sun4i-a10-system-control.yaml | 1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 System Control
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The SRAM controller found on most Allwinner devices is represented
15 by a regular node for the SRAM controller itself, with sub-nodes
16 representing the SRAM handled by the SRAM controller.
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | ti,sci-clk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/ti,sci-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI clock controller
10 - Nishanth Menon <nm@ti.com>
13 Some TI SoCs contain a system controller (like the Power Management Micro
14 Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
16 between the host processor running an OS and the system controller happens
17 through a protocol called TI System Control Interface (TI-SCI protocol).
[all …]
|
| /openbmc/u-boot/doc/device-tree-bindings/remoteproc/ |
| H A D | k3-system-controller.txt | 1 Texas Instruments' K3 System Controller
10 --------------------
11 - compatible: Shall be: "ti,am654-system-controller"
12 - mbox-names: "tx" for Transfer channel
14 - mboxes: Corresponding phandles to mailbox channels.
18 --------
20 system-controller: system-controller {
21 compatible = "ti,am654-system-controller";
23 mbox-names = "tx", "rx";
|
| /openbmc/linux/drivers/staging/media/atomisp/pci/ |
| H A D | system_local.c | 1 // SPDX-License-Identifier: GPL-2.0
95 /*GP TIMER , all timer registers are inter-twined,
139 /* IBUF_CTRL, part of the Input System 2401 */
141 0x00000000000C1800ULL, /* ibuf controller A */
142 0x00000000000C3800ULL, /* ibuf controller B */
143 0x00000000000C5800ULL /* ibuf controller C */
146 /* ISYS IRQ Controllers, part of the Input System 2401 */
153 /* CSI FE, part of the Input System 2401 */
155 0x00000000000C0400ULL, /* csi fe controller A */
156 0x00000000000C2400ULL, /* csi fe controller B */
[all …]
|
| /openbmc/linux/Documentation/arch/x86/ |
| H A D | earlyprintk.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 Mini-HOWTO for using the earlyprintk=dbgp boot option with a
13 [host/target] <-------> [USB debug key] <-------> [client/console]
18 a) Host/target system needs to have USB debug port capability.
21 the lspci -vvv output::
23 # lspci -vvv
25 …00:1d.7 USB Controller: Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #1 (rev 03) (p…
27 …Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisIN…
28 …Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- I…
31 Region 0: Memory at fe227000 (32-bit, non-prefetchable) [size=1K]
[all …]
|