Lines Matching +full:system +full:- +full:controller
1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2004-2011 Freescale Semiconductor, Inc.
32 * System configuration registers
47 u32 sgprl; /* System General Purpose Register Low */
48 u32 sgprh; /* System General Purpose Register High */
49 u32 spridr; /* System Part and Revision ID Register */
51 u32 spcr; /* System Priority Configuration Register */
52 u32 sicrl; /* System I/O Configuration Register Low */
53 u32 sicrh; /* System I/O Configuration Register High */
55 u32 sidcr0; /* System I/O Delay Configuration Register 0 */
56 u32 sidcr1; /* System I/O Delay Configuration Register 1 */
82 u32 swcrr; /* System watchdog control register */
83 u32 swcnr; /* System watchdog count register */
85 u16 swsrr; /* System watchdog service register */
138 * Integrated Programmable Interrupt Controller
141 u32 sicfr; /* System Global Interrupt Configuration Register */
142 u32 sivcr; /* System Global Interrupt Vector Register */
143 u32 sipnr_h; /* System Internal Interrupt Pending Register - High */
144 u32 sipnr_l; /* System Internal Interrupt Pending Register - Low */
145 u32 siprr_a; /* System Internal Interrupt Group A Priority Register */
146 u32 siprr_b; /* System Internal Interrupt Group B Priority Register */
147 u32 siprr_c; /* System Internal Interrupt Group C Priority Register */
148 u32 siprr_d; /* System Internal Interrupt Group D Priority Register */
149 u32 simsr_h; /* System Internal Interrupt Mask Register - High */
150 u32 simsr_l; /* System Internal Interrupt Mask Register - Low */
151 u32 sicnr; /* System Internal Interrupt Control Register */
152 u32 sepnr; /* System External Interrupt Pending Register */
153 u32 smprr_a; /* System Mixed Interrupt Group A Priority Register */
154 u32 smprr_b; /* System Mixed Interrupt Group B Priority Register */
155 u32 semsr; /* System External Interrupt Mask Register */
156 u32 secnr; /* System External Interrupt Control Register */
157 u32 sersr; /* System Error Status Register */
158 u32 sermr; /* System Error Mask Register */
159 u32 sercr; /* System Error Control Register */
160 u32 sepcr; /* System External Interrupt Polarity Control Register */
161 u32 sifcr_h; /* System Internal Interrupt Force Register - High */
162 u32 sifcr_l; /* System Internal Interrupt Force Register - Low */
163 u32 sefcr; /* System External Interrupt Force Register */
164 u32 serfr; /* System Error Force Register */
165 u32 scvcr; /* System Critical Interrupt Vector Register */
166 u32 smvcr; /* System Management Interrupt Vector Register */
171 * System Arbiter Registers
205 u32 spmr; /* system PLL mode Register */
207 u32 sccr; /* system clock control Register */
268 u32 lbmcsar; /* Local bus memory controller start address */
269 u32 sdmcsar; /* Secondary DDR memory controller start address */
271 u32 lbmcear; /* Local bus memory controller end address */
272 u32 sdmcear; /* Secondary DDR memory controller end address */
274 u32 lbmcar; /* Local bus memory controller attributes */
275 u32 sdmcar; /* Secondary DDR memory controller attributes */
280 * DDR Memory Controller Memory Map for DDR1
328 u32 err_sbe; /* Memory Single-Bit ECC Error Management */
357 u32 res0[0xC]; /* 0x0-0x29 reseverd */
360 u32 res1[0x6]; /* 0x38-0x49 reserved */
366 u32 res2; /* 0x64-0x67 reserved */
368 u32 res3[0x5]; /* 0x6C-0x79 reserved */
371 u32 res4[0x1E]; /* 0x88-0x99 reserved */
410 * PCI Controller Control and Status Registers
630 sysconf83xx_t sysconf; /* System configuration */
635 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
636 arbiter83xx_t arbiter; /* System Arbiter Registers */
638 clk83xx_t clk; /* System Clock Module */
646 struct ccsr_ddr ddr; /* DDR Memory Controller Memory */
648 ddr83xx_t ddr; /* DDR Memory Controller Memory */
654 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
660 pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */
671 #define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 /* use the MPH controller */
675 #define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 /* use the DR controller */
684 sysconf83xx_t sysconf; /* System configuration */
689 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
690 arbiter83xx_t arbiter; /* System Arbiter Registers */
692 clk83xx_t clk; /* System Clock Module */
696 ddr83xx_t ddr; /* DDR Memory Controller Memory */
701 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
708 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
719 sysconf83xx_t sysconf; /* System configuration */
724 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
725 arbiter83xx_t arbiter; /* System Arbiter Registers */
727 clk83xx_t clk; /* System Clock Module */
731 ddr83xx_t ddr; /* DDR Memory Controller Memory */
736 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
743 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
745 pex83xx_t pciexp[2]; /* PCI Express Controller */
747 tdm83xx_t tdm; /* TDM Controller */
749 sata83xx_t sata[2]; /* SATA Controller */
751 usb83xx_t usb[1]; /* USB DR Controller */
764 sysconf83xx_t sysconf; /* System configuration */
769 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
770 arbiter83xx_t arbiter; /* System Arbiter Registers */
772 clk83xx_t clk; /* System Clock Module */
776 ddr83xx_t ddr; /* DDR Memory Controller Memory */
781 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
788 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
790 pex83xx_t pciexp[2]; /* PCI Express Controller */
792 sata83xx_t sata[4]; /* SATA Controller */
794 usb83xx_t usb[1]; /* USB DR Controller */
797 sdhc83xx_t sdhc; /* SDHC Controller */
808 sysconf83xx_t sysconf; /* System configuration */
813 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
814 arbiter83xx_t arbiter; /* System Arbiter Registers */
816 clk83xx_t clk; /* System Clock Module */
826 ddr83xx_t ddr; /* DDR Memory Controller Memory */
831 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
837 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
839 ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */
848 sysconf83xx_t sysconf; /* System configuration */
853 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
854 arbiter83xx_t arbiter; /* System Arbiter Registers */
856 clk83xx_t clk; /* System Clock Module */
865 ddr83xx_t ddr; /* DDR Memory Controller Memory */
870 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
876 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
884 sysconf83xx_t sysconf; /* System configuration */
889 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
890 arbiter83xx_t arbiter; /* System Arbiter Registers */
892 clk83xx_t clk; /* System Clock Module */
899 ddr83xx_t ddr; /* DDR Memory Controller Memory */
906 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
925 sdhc83xx_t sdhc; /* SDHC Controller */
953 #define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)