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/openbmc/linux/drivers/memory/
H A Dmvebu-devbus.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2013-2014 Marvell
14 #include <linux/clk.h>
96 dev_err(devbus->dev, "%pOF has no '%s' property\n", in get_timing_param_ps()
101 *ticks = (time_ps + devbus->tick_ps - 1) / devbus->tick_ps; in get_timing_param_ps()
103 dev_dbg(devbus->dev, "%s: %u ps -> 0x%x\n", in get_timing_param_ps()
115 err = of_property_read_u32(node, "devbus,bus-width", &r->bus_width); in devbus_get_timing_params()
117 dev_err(devbus->dev, in devbus_get_timing_params()
118 "%pOF has no 'devbus,bus-width' property\n", in devbus_get_timing_params()
127 if (r->bus_width == 8) { in devbus_get_timing_params()
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap3-igep.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 /dts-v1/;
19 stdout-path = &uart3;
23 compatible = "ti,omap-twl4030";
28 vdd33: regulator-vdd33 {
29 compatible = "regulator-fixed";
30 regulator-name = "vdd33";
31 regulator-always-on;
37 gpmc_pins: gpmc-pins {
38 pinctrl-single,pins = <
[all …]
H A Domap2420-n8x0-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 stdout-path = &uart3;
16 compatible = "i2c-cbus-gpio";
17 gpios = <&gpio3 2 GPIO_ACTIVE_HIGH /* gpio66 clk */
21 #address-cells = <1>;
22 #size-cells = <0>;
25 interrupt-parent = <&gpio4>;
34 clock-frequency = <400000>;
44 clock-frequency = <400000>;
50 /* gpio-irq for dma: 26 */
[all …]
H A Domap3-gta04a5one.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-18 H. Nikolaus Schaller <hns@goldelico.com>
6 #include "omap3-gta04a5.dts"
13 gpmc_pins: gpmc-pins {
14 pinctrl-single,pins = <
45 pinctrl-names = "default";
46 pinctrl-0 = <&gpmc_pins>;
48 /delete-node/ nand@0,0;
52 #address-cells = <1>;
53 #size-cells = <1>;
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H A Domap2430-sdp.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
11 compatible = "ti,omap2430-sdp", "ti,omap2430", "ti,omap2";
20 clock-frequency = <100000>;
31 vmmc-supply = <&vmmc1>;
32 bus-width = <4>;
39 interrupt-parent = <&gpio5>;
42 bank-width = <2>;
43 gpmc,sync-clk-ps = <0>;
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H A Domap4-duovero-parlor.dts1 // SPDX-License-Identifier: GPL-2.0-only
5 /dts-v1/;
7 #include "omap4-duovero.dtsi"
9 #include <dt-bindings/input/input.h>
13 compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4";
20 compatible = "gpio-leds";
24 linux,default-trigger = "heartbeat";
29 compatible = "gpio-keys";
30 #address-cells = <1>;
31 #size-cells = <0>;
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H A Domap3-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include "omap3-evm-common.dtsi"
9 #include "omap3-evm-processor-common.dtsi"
13 compatible = "ti,omap3-evm", "ti,omap3430", "ti,omap3";
17 pinctrl-names = "default";
18 pinctrl-0 = <&hsusb2_2_pins>;
20 ehci_phy_pins: ehci-phy-pins {
21 pinctrl-single,pins = <
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H A Domap3-evm-37xx.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include "omap3-evm-common.dtsi"
9 #include "omap3-evm-processor-common.dtsi"
13 compatible = "ti,omap3-evm-37xx", "ti,omap3630", "ti,omap3";
17 pinctrl-names = "default";
18 pinctrl-0 = <&hsusb2_2_pins>;
20 ehci_phy_pins: ehci-phy-pins {
21 pinctrl-single,pins = <
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H A Ddm8148-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only
2 /dts-v1/;
5 #include <dt-bindings/interrupt-controller/irq.h>
9 compatible = "ti,dm8148-evm", "ti,dm8148", "ti,dm814";
18 compatible = "regulator-fixed";
19 regulator-name = "vmmcsd_fixed";
20 regulator-min-microvolt = <3300000>;
21 regulator-max-microvolt = <3300000>;
26 phy-handle = <&ethphy0>;
27 phy-mode = "rgmii-id";
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H A Ddra62x-j5eco-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only
2 /dts-v1/;
5 #include <dt-bindings/interrupt-controller/irq.h>
9 compatible = "ti,dra62x-j5eco-evm", "ti,dra62x", "ti,dm8148", "ti,dm814";
18 compatible = "regulator-fixed";
19 regulator-name = "vmmcsd_fixed";
20 regulator-min-microvolt = <3300000>;
21 regulator-max-microvolt = <3300000>;
26 phy-handle = <&ethphy0>;
27 phy-mode = "rgmii-id";
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H A Dam335x-chilisom.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Jablotron s.r.o. -- https://www.jablotron.com/
7 #include <dt-bindings/interrupt-controller/irq.h>
11 compatible = "grinn,am335x-chilisom", "ti,am33xx";
15 cpu0-supply = <&dcdc2_reg>;
26 pinctrl-names = "default";
28 i2c0_pins: i2c0-pins {
29 pinctrl-single,pins = <
35 nandflash_pins: nandflash-pins {
36 pinctrl-single,pins = <
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/openbmc/u-boot/arch/arm/dts/
H A Domap3-igep.dtsi11 /dts-v1/;
22 stdout-path = &uart3;
26 compatible = "ti,omap-twl4030";
31 vdd33: regulator-vdd33 {
32 compatible = "regulator-fixed";
33 regulator-name = "vdd33";
34 regulator-always-on;
41 pinctrl-single,pins = <
48 pinctrl-single,pins = <
55 pinctrl-single,pins = <
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H A Domap3-evm.dts2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
8 /dts-v1/;
11 #include "omap3-evm-common.dtsi"
12 #include "omap3-evm-processor-common.dtsi"
16 compatible = "ti,omap3-evm", "ti,omap3430", "ti,omap3";
20 pinctrl-names = "default";
21 pinctrl-0 = <&hsusb2_2_pins>;
24 pinctrl-single,pins = <
36 pinctrl-single,pins = <
61 compatible = "ti,omap2-nand";
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H A Domap3-evm-37xx.dts2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
8 /dts-v1/;
11 #include "omap3-evm-common.dtsi"
12 #include "omap3-evm-processor-common.dtsi"
16 compatible = "ti,omap3-evm-37xx", "ti,omap3630", "ti,omap3";
20 pinctrl-names = "default";
21 pinctrl-0 = <&hsusb2_2_pins>;
24 pinctrl-single,pins = <
36 pinctrl-single,pins = <
61 compatible = "ti,omap2-nand";
[all …]
H A Dam335x-draco.dtsi4 * Copyright (C) 2013,2014 - Stefan Roese <sr@denx.de>
13 stdout-path = &uart0;
14 tick-timer = &timer2;
24 pinctrl-names = "default";
25 pinctrl-0 = <&uart0_pins>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&i2c0_pins>;
34 clock-frequency = <400000>;
50 usb-phy@47401300 {
54 usb-phy@47401b00 {
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H A Dam335x-brppt1-nand.dts1 // SPDX-License-Identifier: GPL-2.0+
4 * http://www.br-automation.com
7 /dts-v1/;
15 fset: factory-settings {
16 bl-version = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890";
18 order-no = "6PPT30 (NAND)";
19 hw-revision = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890";
20 serial-no = "0";
21 device-id = <0x0>;
22 parent-id = <0x0>;
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H A Dam335x-chilisom.dtsi2 * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
10 #include <dt-bindings/interrupt-controller/irq.h>
14 compatible = "grinn,am335x-chilisom", "ti,am33xx";
18 cpu0-supply = <&dcdc2_reg>;
29 pinctrl-names = "default";
32 pinctrl-single,pins = <
39 pinctrl-single,pins = <
60 pinctrl-names = "default";
61 pinctrl-0 = <&i2c0_pins>;
64 clock-frequency = <400000>;
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H A Ddm8168-evm.dts6 /dts-v1/;
9 #include <dt-bindings/interrupt-controller/irq.h>
13 compatible = "ti,dm8168-evm", "ti,dm8168";
23 compatible = "regulator-fixed";
24 regulator-name = "vmmcsd_fixed";
25 regulator-min-microvolt = <3300000>;
26 regulator-max-microvolt = <3300000>;
32 pinctrl-single,pins = <
41 pinctrl-single,pins = <
55 pinctrl-single,pins = <
[all …]
/openbmc/linux/drivers/fpga/
H A Dzynq-fpga.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2011-2015 Xilinx Inc.
10 #include <linux/clk.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/fpga/fpga-mgr.h>
113 /* Enable Level shifters from PS to PL */
115 /* Enable Level shifters from PL to PS */
124 struct clk *clk; member
140 writel(val, priv->io_base + offset); in zynq_fpga_write()
146 return readl(priv->io_base + offset); in zynq_fpga_read()
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/openbmc/linux/drivers/video/fbdev/omap/
H A Dhwa742.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2004-2005 Nokia Corporation
14 #include <linux/clk.h>
86 struct completion *sync; member
130 struct clk *sys_ck;
139 hwa742.extif->set_bits_per_cycle(8); in hwa742_read_reg()
140 hwa742.extif->write_command(&reg, 1); in hwa742_read_reg()
141 hwa742.extif->read_data(&data, 1); in hwa742_read_reg()
148 hwa742.extif->set_bits_per_cycle(8); in hwa742_write_reg()
149 hwa742.extif->write_command(&reg, 1); in hwa742_write_reg()
[all …]
H A Dsossi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2004-2005 Nokia Corporation
10 #include <linux/clk.h>
15 #include <linux/omap-dma.h>
16 #include <linux/soc/ti/omap1-io.h>
22 #define MODULE_NAME "omapfb-sossi"
49 struct clk *fck;
114 static u32 ps_to_sossi_ticks(u32 ps, int div) in ps_to_sossi_ticks() argument
117 return (clk_period + ps - 1) / clk_period; in ps_to_sossi_ticks()
124 int div = t->clk_div; in calc_rd_timings()
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti,gpmc-child.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
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/openbmc/linux/drivers/net/ethernet/marvell/
H A Dmvneta.c7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
14 #include <linux/clk.h>
156 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
158 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
270 * to cover all rate-limit values from 10Kbps up to 5Gbps
296 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
374 #define MVNETA_MAX_RX_BUF_SIZE (PAGE_SIZE - MVNETA_SKB_PAD)
377 (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT)
469 struct mvneta_stats ps; member
486 /* Pointer to the CPU-local NAPI struct */
[all …]
/openbmc/linux/drivers/phy/amlogic/
H A Dphy-meson-axg-mipi-dphy.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/clk.h>
33 * [11] mipi divider clk selection.
46 * [1] write 1 to sync the txclkesc input. the internal logic have to
52 /* [31] clk lane tx_hs_en control selection.
53 * 1: from register. 0: use clk lane state machine.
55 * [29] clk lane tx_lp_en contrl selection.
56 * 1: from register. 0: from clk lane state machine.
88 * [4] clk chan power down. this bit is also used as the power down
101 * [20:17] clk lane state. {mbias_ready, tx_stop, tx_ulps, tx_hs_active}
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dspd_sdram.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2006-2007 Freescale Semiconductor, Inc.
8 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
28 volatile ddr83xx_t *ddr = &immap->ddr; in board_add_ram_info()
31 printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) in board_add_ram_info()
32 >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1); in board_add_ram_info()
35 if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16) in board_add_ram_info()
36 puts(", 16-bit"); in board_add_ram_info()
37 else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32) in board_add_ram_info()
38 puts(", 32-bit"); in board_add_ram_info()
[all …]

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