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/openbmc/u-boot/board/xes/xpedite537x/
H A Dddr.c26 * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
145 * exactly WL (CAS latency minus one cycle) after the CAS strobe.
148 * the CAS strobe. (due to the fact that the "delay" is referenced
150 * which the CAS strobe is latched on.
/openbmc/u-boot/arch/arm/dts/
H A Dkeystone-k2l-evm.dts57 ti,cs-read-strobe-ns = <23>;
60 ti,cs-write-strobe-ns = <23>;
H A Dkeystone-k2e-evm.dts80 ti,cs-read-strobe-ns = <23>;
83 ti,cs-write-strobe-ns = <23>;
H A Dkeystone-k2hk-evm.dts101 ti,cs-read-strobe-ns = <23>;
104 ti,cs-write-strobe-ns = <23>;
H A Dmeson-gxl-s905x-khadas-vim.dts149 "", "BOOT_MODE", "", "", "eMMC Data Strobe",
H A Drk3399-evb.dts166 mmc-hs400-enhanced-strobe;
H A Dmeson-gxl-s905x-libretech-cc.dts199 "ALT BOOT MODE", "", "", "", "eMMC Data Strobe",
/openbmc/u-boot/arch/arm/mach-imx/
H A Dddrmc-vf610-calibration.c50 * - 0x2 (b'10) - RDLVL_DL_0/1 - refers to adjusting the DQS strobe in relation
51 * to the DQ signals so that the strobe edge is
55 * the Read DQS strobe pad from the time that the
56 * PHY enables the pad to input the strobe signal.
/openbmc/u-boot/board/keymile/kmp204x/
H A Dddr.c30 /* 1/2 clk delay between wr command and data strobe */ in fsl_ddr_board_options()
/openbmc/u-boot/doc/device-tree-bindings/gpio/
H A Dmscc_sgpio.txt5 strobe pin. By attaching a number of (external) shift registers, the
/openbmc/u-boot/board/aristainetos/
H A Dddr-setup2.cfg32 /* Data Strobe */
H A Dddr-setup.cfg34 /* Data Strobe */
/openbmc/u-boot/board/samtec/vining_2000/
H A Dimximage.cfg62 /* Data Strobe */
/openbmc/u-boot/board/freescale/mx6sxsabreauto/
H A Dimximage.cfg62 /* Data Strobe */
/openbmc/u-boot/board/xes/xpedite517x/
H A Dddr.c25 * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
/openbmc/u-boot/board/freescale/mx6sxsabresd/
H A Dimximage.cfg62 /* Data Strobe */
/openbmc/u-boot/drivers/misc/
H A Drockchip-efuse.c37 /* 0x14 efuse strobe finish control register */
/openbmc/u-boot/include/
H A Dddr_spd.h49 unsigned char data_setup; /* 34 Data Input Setup Time Before Strobe */
50 unsigned char data_hold; /* 35 Data Input Hold Time After Strobe */
112 Before Strobe (tDS) */
114 After Strobe (tDH) */
H A Dfsl_esdhc.h192 /* strobe dll register */
/openbmc/u-boot/board/seco/mx6quq7/
H A Dmx6quq7-2g.cfg30 /* DATA STROBE */
/openbmc/u-boot/drivers/pci/
H A Dpci-aardvark.c354 * pcie_calc_datastrobe() - Calculate data strobe
359 * Calculate data strobe according to offset and size
438 /* Program the data strobe */ in pcie_advk_write_config()
/openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Inventory/Item/
H A DDimm.interface.yaml46 strobe signal are presented to the memory module and the time at which
/openbmc/qemu/hw/sh4/
H A Dsh7750_regs.h761 #define SH7750_WCR3_A6S 0x04000000 /* Area 6 Write Strobe Setup time */
764 #define SH7750_WCR3_A5S 0x00400000 /* Area 5 Write Strobe Setup time */
767 #define SH7750_WCR3_A4S 0x00040000 /* Area 4 Write Strobe Setup time */
770 #define SH7750_WCR3_A3S 0x00004000 /* Area 3 Write Strobe Setup time */
773 #define SH7750_WCR3_A2S 0x00000400 /* Area 2 Write Strobe Setup time */
776 #define SH7750_WCR3_A1S 0x00000040 /* Area 1 Write Strobe Setup time */
779 #define SH7750_WCR3_A0S 0x00000004 /* Area 0 Write Strobe Setup time */
/openbmc/u-boot/drivers/mmc/
H A Dfsl_esdhc.c734 * enable strobe dll ctrl and adjust the delay target in esdhc_set_strobe_dll()
741 /* wait 1us to make sure strobe dll status register stable */ in esdhc_set_strobe_dll()
745 pr_warn("HS400 strobe DLL status REF not lock!\n"); in esdhc_set_strobe_dll()
747 pr_warn("HS400 strobe DLL status SLV not lock!\n"); in esdhc_set_strobe_dll()
1478 val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target", in fsl_esdhc_probe()
H A Dsdhci-cadence.c83 { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },

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