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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dst,stm32mp1-rcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/st,stm32mp1-rcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32MP1 Reset Clock Controller
10 - Gabriel Fernandez <gabriel.fernandez@foss.st.com>
13 The RCC IP is both a reset and a clock controller.
14 RCC makes also power management (resume/supend and wakeup interrupt).
18 Documentation/devicetree/bindings/clock/clock-bindings.txt
24 dt-bindings/clock/stm32mp1-clks.h header and can be used in device
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/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Dst,stm32mp1.txt1 STMicroelectronics STM32MP1 clock tree initialization
5 for RCC IP and on fixed clocks.
7 -------------------------------
8 RCC CLOCK = st,stm32mp1-rcc-clk
9 -------------------------------
11 The RCC IP is both a reset and a clock controller but this documentation only
15 Please refer to ../mfd/st,stm32-rcc.txt for all the other properties common
20 - compatible: Should be "st,stm32mp1-rcc-clk"
22 - st,clksrc : The clock source in this order
27 with value equals to RCC clock specifier as defined in
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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dstm32-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/stm32-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre Torgue <alexandre.torgue@foss.st.com>
12 - Christophe Roullier <christophe.roullier@foss.st.com>
23 - st,stm32-dwmac
24 - st,stm32mp1-dwmac
26 - compatible
29 - $ref: snps,dwmac.yaml#
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/openbmc/u-boot/arch/arm/dts/
H A Dstm32mp157c.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
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H A Dstm32mp15-ddr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
9 u-boot,dm-pre-reloc;
11 compatible = "st,stm32mp1-ddr";
16 clocks = <&rcc AXIDCG>,
17 <&rcc DDRC1>,
18 <&rcc DDRC2>,
19 <&rcc DDRPHYC>,
20 <&rcc DDRCAPB>,
21 <&rcc DDRPHYCAPB>;
23 clock-names = "axidcg",
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/openbmc/linux/Documentation/devicetree/bindings/rtc/
H A Dst,stm32-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/st,stm32-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gabriel Fernandez <gabriel.fernandez@foss.st.com>
15 - st,stm32-rtc
16 - st,stm32h7-rtc
17 - st,stm32mp1-rtc
26 clock-names:
28 - const: pclk
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/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32mp151.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
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/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Dst,stm32-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/st,stm32-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Pierre-Yves MORDRET <pierre-yves.mordret@foss.st.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
14 - if:
19 - st,stm32f7-i2c
20 - st,stm32mp13-i2c
21 - st,stm32mp15-i2c
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/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dst,stm32-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 STM32 ADC is a successive approximation analog-to-digital converter.
13 stored in a left-aligned or right-aligned 32-bit data register.
17 voltage goes beyond the user-defined, higher or lower thresholds.
22 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
27 - st,stm32f4-adc-core
28 - st,stm32h7-adc-core
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H A Dst,stm32-dfsdm-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-dfsdm-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
11 - Olivier Moysan <olivier.moysan@foss.st.com>
14 STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to
17 - Sigma delta modulators (motor control, metering...)
18 - PDM microphones (audio digital microphone)
21 up to 4 filters on stm32h7 or 6 filters on stm32mp1.
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/openbmc/linux/Documentation/devicetree/bindings/crypto/
H A Dst,stm32-cryp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/st,stm32-cryp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Lionel Debieve <lionel.debieve@foss.st.com>
19 - st,stn8820-cryp
20 - stericsson,ux500-cryp
21 - st,stm32f756-cryp
22 - st,stm32mp1-cryp
38 - description: mem2cryp DMA channel
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H A Dst,stm32-hash.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/st,stm32-hash.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Lionel Debieve <lionel.debieve@foss.st.com>
19 - st,stn8820-hash
20 - stericsson,ux500-hash
21 - st,stm32f456-hash
22 - st,stm32f756-hash
23 - st,stm32mp13-hash
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/openbmc/u-boot/drivers/misc/
H A Dstm32_rcc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
11 #include <dm/device-internal.h>
35 .soc = STM32MP1,
47 drv = lists_driver_lookup_name(rcc_clk->drv_name); in stm32_rcc_bind()
49 debug("Cannot find driver '%s'\n", rcc_clk->drv_name); in stm32_rcc_bind()
50 return -ENOENT; in stm32_rcc_bind()
53 ret = device_bind_with_driver_data(dev, drv, rcc_clk->drv_name, in stm32_rcc_bind()
54 rcc_clk->soc, in stm32_rcc_bind()
63 return -ENOENT; in stm32_rcc_bind()
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/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dst,stm32-iwdg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/st,stm32-iwdg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yannick Fertre <yannick.fertre@foss.st.com>
11 - Christophe Roullier <christophe.roullier@foss.st.com>
14 - $ref: watchdog.yaml#
19 - st,stm32-iwdg
20 - st,stm32mp1-iwdg
27 - description: Low speed clock
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/openbmc/linux/Documentation/devicetree/bindings/reset/
H A Dst,stm32mp1-rcc.txt1 STMicroelectronics STM32MP1 Peripheral Reset Controller
4 The RCC IP is both a reset and a clock controller.
6 Please see Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dst,stm32-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/st,stm32-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Fabien Dessenne <fabien.dessenne@foss.st.com>
15 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
19 const: st,stm32mp1-m4
31 reset-names:
33 - const: mcu_rst
34 - const: hold_boot
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/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dst,stm32-fmc2-nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/st,stm32-fmc2-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
15 - st,stm32mp15-fmc2
16 - st,stm32mp1-fmc2-nfc
27 - description: tx DMA channel
28 - description: rx DMA channel
29 - description: ecc DMA channel
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dst,stm32-fmc2-ebi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
14 - to translate AXI transactions into the appropriate external device
16 - to meet the access time requirements of the external devices
22 - Christophe Kerello <christophe.kerello@foss.st.com>
26 const: st,stm32mp1-fmc2-ebi
37 "#address-cells":
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/openbmc/u-boot/drivers/reset/
H A Dstm32-reset.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
10 #include <reset-uclass.h>
14 /* reset clear offset for STM32MP RCC */
33 struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev); in stm32_reset_assert()
34 int bank = (reset_ctl->id / BITS_PER_LONG) * 4; in stm32_reset_assert()
35 int offset = reset_ctl->id % BITS_PER_LONG; in stm32_reset_assert()
37 reset_ctl->id, bank, offset); in stm32_reset_assert()
39 if (dev_get_driver_data(reset_ctl->dev) == STM32MP1) in stm32_reset_assert()
40 /* reset assert is done in rcc set register */ in stm32_reset_assert()
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/openbmc/linux/Documentation/devicetree/bindings/display/
H A Dst,stm32-ltdc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/st,stm32-ltdc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 lcd-tft display controller
10 - Philippe Cornu <philippe.cornu@foss.st.com>
11 - Yannick Fertre <yannick.fertre@foss.st.com>
15 const: st,stm32-ltdc
22 - description: events interrupt line.
23 - description: errors interrupt line.
[all …]
H A Dst,stm32-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/st,stm32-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Philippe Cornu <philippe.cornu@foss.st.com>
11 - Yannick Fertre <yannick.fertre@foss.st.com>
14 The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller.
17 - $ref: dsi-controller.yaml#
21 const: st,stm32-dsi
28 - description: Module Clock
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/openbmc/u-boot/include/
H A Dstm32_rcc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
46 STM32MP1, enumerator
60 u32 cr; /* RCC clock control */
61 u32 pllcfgr; /* RCC PLL configuration */
62 u32 cfgr; /* RCC clock configuration */
63 u32 cir; /* RCC clock interrupt */
64 u32 ahb1rstr; /* RCC AHB1 peripheral reset */
65 u32 ahb2rstr; /* RCC AHB2 peripheral reset */
66 u32 ahb3rstr; /* RCC AHB3 peripheral reset */
68 u32 apb1rstr; /* RCC APB1 peripheral reset */
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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dst,stm32-qspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/st,stm32-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
11 - Patrice Chotard <patrice.chotard@foss.st.com>
14 - $ref: spi-controller.yaml#
18 const: st,stm32f469-qspi
22 - description: registers
23 - description: memory mapping
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/openbmc/u-boot/drivers/clk/
H A DKconfig21 used as U-Boot proper.
31 used as U-Boot proper.
54 This clock driver adds support for RCC clock management
94 bool "Enable RCC clock driver for STM32MP1"
98 Enable the STM32 clock (RCC) driver. Enable support for
99 manipulating STM32MP1's on-SoC clocks.
116 Support for the ICS8N3QV01 Quad-Frequency VCXO (Voltage-Controlled
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dst,stm32-dcmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/st,stm32-dcmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hugues Fruchet <hugues.fruchet@foss.st.com>
14 const: st,stm32-dcmi
25 clock-names:
27 - const: mclk
32 dma-names:
34 - const: tx
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