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/openbmc/linux/Documentation/arch/arm/stm32/
H A Dstm32-dma-mdma-chaining.rst1 .. SPDX-License-Identifier: GPL-2.0
4 STM32 DMA-MDMA chaining
9 ------------
11 This document describes the STM32 DMA-MDMA chaining feature. But before going
14 To offload data transfers from the CPU, STM32 microprocessors (MPUs) embed
15 direct memory access controllers (DMA).
17 STM32MP1 SoCs embed both STM32 DMA and STM32 MDMA controllers. STM32 DMA
18 request routing capabilities are enhanced by a DMA request multiplexer
19 (STM32 DMAMUX).
21 **STM32 DMAMUX**
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/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32mp131.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp13-clks.h>
8 #include <dt-bindings/reset/stm32mp13-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
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H A Dstm32mp151.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
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H A Dstm32f429.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
22 * MA 02110-1301 USA
48 #include "../armv7-m.dtsi"
49 #include <dt-bindings/clock/stm32fx-clock.h>
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
53 #address-cells = <1>;
54 #size-cells = <1>;
57 clk_hse: clk-hse {
58 #clock-cells = <0>;
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H A Dstm32h743.dtsi2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include "../armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32h7-clks.h>
45 #include <dt-bindings/mfd/stm32h7-rcc.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
49 #address-cells = <1>;
50 #size-cells = <1>;
53 clk_hse: clk-hse {
54 #clock-cells = <0>;
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H A Dstm32f746.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include "../armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32fx-clock.h>
45 #include <dt-bindings/mfd/stm32f7-rcc.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
52 clk_hse: clk-hse {
53 #clock-cells = <0>;
54 compatible = "fixed-clock";
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/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dst,stm32-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 DMA Controller
10 The STM32 DMA is a general-purpose direct memory access controller capable of
11 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
12 DMA clients connected to the STM32 DMA controller must use the format
13 described in the dma.txt file, using a four-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
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H A Dst,stm32-mdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-mdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 MDMA Controller
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
11 supporting 64 independent DMA channels with 256 HW requests.
12 DMA clients connected to the STM32 MDMA controller must use the format
13 described in the dma.txt file, using a five-cell specifier for each channel:
21 3. A 32bit mask specifying the DMA channel configuration
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H A Dst,stm32-dmamux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-dmamux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 DMA MUX (DMA request router)
10 - Amelie Delaunay <amelie.delaunay@foss.st.com>
13 - $ref: dma-router.yaml#
16 "#dma-cells":
20 const: st,stm32h7-dmamux
32 - compatible
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/openbmc/u-boot/arch/arm/dts/
H A Dstm32f429.dtsi2 * Copyright (C) 2015, STMicroelectronics - All Rights Reserved
3 * Author(s): Maxime Coquelin <mcoquelin.stm32@gmail.com> for STMicroelectronics.
5 * This file is dual-licensed: you can use it either under the terms
45 #include "armv7-m.dtsi"
46 #include <dt-bindings/clock/stm32fx-clock.h>
47 #include <dt-bindings/mfd/stm32f4-rcc.h>
51 clk_hse: clk-hse {
52 #clock-cells = <0>;
53 compatible = "fixed-clock";
54 clock-frequency = <0>;
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H A Dstm32mp157c.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dst,stm32-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/st,stm32-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 SPI Controller
10 The STM32 SPI controller is used to communicate with external devices using
11 the Serial Peripheral Interface. It supports full-duplex, half-duplex and
13 from 4 to 32-bit data size.
16 - Erwan Leray <erwan.leray@foss.st.com>
17 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
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/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dst,stm32-dfsdm-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-dfsdm-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 DFSDM ADC device driver
10 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
11 - Olivier Moysan <olivier.moysan@foss.st.com>
14 STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to
15 interface external sigma delta modulators to STM32 micro controllers.
17 - Sigma delta modulators (motor control, metering...)
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/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dst,stm32-timers.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-timers.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Timers
11 - advanced-control timers consist of a 16-bit auto-reload counter driven
14 - general-purpose timers consist of a 16-bit or 32-bit auto-reload counter
16 - basic timers consist of a 16-bit auto-reload counter driven by a
20 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
24 const: st,stm32-timers
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/openbmc/linux/Documentation/devicetree/bindings/crypto/
H A Dst,stm32-hash.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/st,stm32-hash.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 HASH
9 description: The STM32 HASH block is built on the HASH block found in
14 - Lionel Debieve <lionel.debieve@foss.st.com>
19 - st,stn8820-hash
20 - stericsson,ux500-hash
21 - st,stm32f456-hash
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H A Dst,stm32-cryp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/st,stm32-cryp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 CRYP
9 description: The STM32 CRYP block is built on the CRYP block found in
14 - Lionel Debieve <lionel.debieve@foss.st.com>
19 - st,stn8820-cryp
20 - stericsson,ux500-cryp
21 - st,stm32f756-cryp
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/openbmc/linux/Documentation/arch/arm/
H A Dindex.rst1 .. SPDX-License-Identifier: GPL-2.0
12 cluster-pm-race-avoidance
28 SoC-specific documents
34 google/chromebook-boot-flow
45 keystone/knav-qmss
54 stm32/stm32f746-overview
55 stm32/overview
56 stm32/stm32h743-overview
57 stm32/stm32h750-overview
58 stm32/stm32f769-overview
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/openbmc/linux/drivers/mfd/
H A Dstm32-timers.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/mfd/stm32-timers.h>
16 /* DIER register DMA enable bits */
29 struct stm32_timers_dma *dma = p; in stm32_timers_dma_done() local
33 status = dmaengine_tx_status(dma->chan, dma->chan->cookie, &state); in stm32_timers_dma_done()
35 complete(&dma->completion); in stm32_timers_dma_done()
39 * stm32_timers_dma_burst_read - Read from timers registers using DMA.
41 * Read from STM32 timers registers using DMA on a single event.
43 * @buf: DMA'able destination buffer
45 * @reg: registers start offset for DMA to read from (like CCRx for capture)
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/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dst,stm32-dcmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/st,stm32-dcmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Digital Camera Memory Interface (DCMI)
10 - Hugues Fruchet <hugues.fruchet@foss.st.com>
14 const: st,stm32-dcmi
25 clock-names:
27 - const: mclk
32 dma-names:
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/openbmc/linux/drivers/media/platform/st/stm32/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
5 tristate "STM32 Digital Camera Memory Interface (DCMI) support"
13 This module makes the STM32 Digital Camera Memory Interface (DCMI)
17 will be called stm32-dcmi.
21 tristate "STM32 Chrom-Art Accelerator (DMA2D)"
28 Enables DMA2D hardware support on stm32.
30 The STM32 DMA2D is a memory-to-memory engine for pixel conversion
31 and specialized DMA dedicated to image manipulation.
/openbmc/linux/drivers/dma/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # DMA engine configuration
7 bool "DMA Engine support"
10 DMA engines can do asynchronous data transfers without
14 DMA Device drivers supported by the configured arch, it may
18 bool "DMA Engine debugging"
22 say N here. This enables DMA engine core and driver debugging.
25 bool "DMA Engine verbose debugging"
30 the DMA engine core and drivers.
35 comment "DMA Devices"
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 subdir-ccflags-$(CONFIG_DMADEVICES_DEBUG) := -DDEBUG
4 subdir-ccflags-$(CONFIG_DMADEVICES_VDEBUG) += -DVERBOSE_DEBUG
7 obj-$(CONFIG_DMA_ENGINE) += dmaengine.o
8 obj-$(CONFIG_DMA_VIRTUAL_CHANNELS) += virt-dma.o
9 obj-$(CONFIG_DMA_ACPI) += acpi-dma.o
10 obj-$(CONFIG_DMA_OF) += of-dma.o
13 obj-$(CONFIG_DMATEST) += dmatest.o
16 obj-$(CONFIG_ALTERA_MSGDMA) += altera-msgdma.o
17 obj-$(CONFIG_AMBA_PL08X) += amba-pl08x.o
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/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Dst,stm32-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/st,stm32-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Erwan Le Ray <erwan.leray@foss.st.com>
10 title: STMicroelectronics STM32 USART
15 - st,stm32-uart
16 - st,stm32f7-uart
17 - st,stm32h7-uart
34 st,hw-flow-ctrl:
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/openbmc/u-boot/doc/device-tree-bindings/adc/
H A Dst,stm32-adc.txt1 STMicroelectronics STM32 ADC device
3 STM32 ADC is a successive approximation analog-to-digital converter.
6 stored in a left-aligned or right-aligned 32-bit data register.
10 voltage goes beyond the user-defined, higher or lower thresholds.
12 Each STM32 ADC block can have up to 3 ADC instances.
16 - regular conversion can be done in sequence, running in background
17 - injected conversions have higher priority, and so have the ability to
21 Contents of a stm32 adc root node:
22 -----------------------------------
24 - compatible: Should be one of:
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/openbmc/linux/Documentation/devicetree/bindings/arm/stm32/
H A Dst,mlahb.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/stm32/st,mlahb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 ML-AHB interconnect
10 - Fabien Dessenne <fabien.dessenne@foss.st.com>
11 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
14 These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects
15 a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory
17 using different buses (see [2]): balancing the Cortex-M firmware accesses
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