171021f3fSBenjamin Gaignard# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 271021f3fSBenjamin Gaignard%YAML 1.2 371021f3fSBenjamin Gaignard--- 471021f3fSBenjamin Gaignard$id: http://devicetree.org/schemas/dma/st,stm32-mdma.yaml# 571021f3fSBenjamin Gaignard$schema: http://devicetree.org/meta-schemas/core.yaml# 671021f3fSBenjamin Gaignard 784e85359SKrzysztof Kozlowskititle: STMicroelectronics STM32 MDMA Controller 871021f3fSBenjamin Gaignard 971021f3fSBenjamin Gaignarddescription: | 1071021f3fSBenjamin Gaignard The STM32 MDMA is a general-purpose direct memory access controller capable of 1171021f3fSBenjamin Gaignard supporting 64 independent DMA channels with 256 HW requests. 1271021f3fSBenjamin Gaignard DMA clients connected to the STM32 MDMA controller must use the format 1371021f3fSBenjamin Gaignard described in the dma.txt file, using a five-cell specifier for each channel: 1471021f3fSBenjamin Gaignard a phandle to the MDMA controller plus the following five integer cells: 1571021f3fSBenjamin Gaignard 1. The request line number 1671021f3fSBenjamin Gaignard 2. The priority level 1771021f3fSBenjamin Gaignard 0x0: Low 1871021f3fSBenjamin Gaignard 0x1: Medium 1971021f3fSBenjamin Gaignard 0x2: High 2071021f3fSBenjamin Gaignard 0x3: Very high 2171021f3fSBenjamin Gaignard 3. A 32bit mask specifying the DMA channel configuration 2271021f3fSBenjamin Gaignard -bit 0-1: Source increment mode 2371021f3fSBenjamin Gaignard 0x0: Source address pointer is fixed 2471021f3fSBenjamin Gaignard 0x2: Source address pointer is incremented after each data transfer 2571021f3fSBenjamin Gaignard 0x3: Source address pointer is decremented after each data transfer 2671021f3fSBenjamin Gaignard -bit 2-3: Destination increment mode 2771021f3fSBenjamin Gaignard 0x0: Destination address pointer is fixed 2871021f3fSBenjamin Gaignard 0x2: Destination address pointer is incremented after each data transfer 2971021f3fSBenjamin Gaignard 0x3: Destination address pointer is decremented after each data transfer 3071021f3fSBenjamin Gaignard -bit 8-9: Source increment offset size 3171021f3fSBenjamin Gaignard 0x0: byte (8bit) 3271021f3fSBenjamin Gaignard 0x1: half-word (16bit) 3371021f3fSBenjamin Gaignard 0x2: word (32bit) 3471021f3fSBenjamin Gaignard 0x3: double-word (64bit) 3571021f3fSBenjamin Gaignard -bit 10-11: Destination increment offset size 3671021f3fSBenjamin Gaignard 0x0: byte (8bit) 3771021f3fSBenjamin Gaignard 0x1: half-word (16bit) 3871021f3fSBenjamin Gaignard 0x2: word (32bit) 3971021f3fSBenjamin Gaignard 0x3: double-word (64bit) 4071021f3fSBenjamin Gaignard -bit 25-18: The number of bytes to be transferred in a single transfer 4171021f3fSBenjamin Gaignard (min = 1 byte, max = 128 bytes) 4271021f3fSBenjamin Gaignard -bit 29:28: Trigger Mode 4371021f3fSBenjamin Gaignard 0x00: Each MDMA request triggers a buffer transfer (max 128 bytes) 4471021f3fSBenjamin Gaignard 0x1: Each MDMA request triggers a block transfer (max 64K bytes) 4571021f3fSBenjamin Gaignard 0x2: Each MDMA request triggers a repeated block transfer 4671021f3fSBenjamin Gaignard 0x3: Each MDMA request triggers a linked list transfer 4771021f3fSBenjamin Gaignard 4. A 32bit value specifying the register to be used to acknowledge the request 4871021f3fSBenjamin Gaignard if no HW ack signal is used by the MDMA client 4971021f3fSBenjamin Gaignard 5. A 32bit mask specifying the value to be written to acknowledge the request 5071021f3fSBenjamin Gaignard if no HW ack signal is used by the MDMA client 5171021f3fSBenjamin Gaignard 5271021f3fSBenjamin Gaignardmaintainers: 53f4eedebdSPatrice Chotard - Amelie Delaunay <amelie.delaunay@foss.st.com> 5471021f3fSBenjamin Gaignard 5571021f3fSBenjamin GaignardallOf: 56*10cafa2dSKrzysztof Kozlowski - $ref: dma-controller.yaml# 5771021f3fSBenjamin Gaignard 5871021f3fSBenjamin Gaignardproperties: 5971021f3fSBenjamin Gaignard "#dma-cells": 6071021f3fSBenjamin Gaignard const: 5 6171021f3fSBenjamin Gaignard 6271021f3fSBenjamin Gaignard compatible: 6371021f3fSBenjamin Gaignard const: st,stm32h7-mdma 6471021f3fSBenjamin Gaignard 6571021f3fSBenjamin Gaignard reg: 6671021f3fSBenjamin Gaignard maxItems: 1 6771021f3fSBenjamin Gaignard 6871021f3fSBenjamin Gaignard clocks: 6971021f3fSBenjamin Gaignard maxItems: 1 7071021f3fSBenjamin Gaignard 7171021f3fSBenjamin Gaignard interrupts: 7271021f3fSBenjamin Gaignard maxItems: 1 7371021f3fSBenjamin Gaignard 7471021f3fSBenjamin Gaignard resets: 7571021f3fSBenjamin Gaignard maxItems: 1 7671021f3fSBenjamin Gaignard 7771021f3fSBenjamin Gaignard st,ahb-addr-masks: 7871021f3fSBenjamin Gaignard $ref: /schemas/types.yaml#/definitions/uint32-array 7971021f3fSBenjamin Gaignard description: Array of u32 mask to list memory devices addressed via AHB bus. 8071021f3fSBenjamin Gaignard 8171021f3fSBenjamin Gaignardrequired: 8271021f3fSBenjamin Gaignard - compatible 8371021f3fSBenjamin Gaignard - reg 8471021f3fSBenjamin Gaignard - clocks 8571021f3fSBenjamin Gaignard - interrupts 8671021f3fSBenjamin Gaignard 876fdc6e23SRob HerringunevaluatedProperties: false 886fdc6e23SRob Herring 8971021f3fSBenjamin Gaignardexamples: 9071021f3fSBenjamin Gaignard - | 9171021f3fSBenjamin Gaignard #include <dt-bindings/interrupt-controller/arm-gic.h> 9271021f3fSBenjamin Gaignard #include <dt-bindings/clock/stm32mp1-clks.h> 9371021f3fSBenjamin Gaignard #include <dt-bindings/reset/stm32mp1-resets.h> 9471021f3fSBenjamin Gaignard dma-controller@52000000 { 9571021f3fSBenjamin Gaignard compatible = "st,stm32h7-mdma"; 9671021f3fSBenjamin Gaignard reg = <0x52000000 0x1000>; 9771021f3fSBenjamin Gaignard interrupts = <122>; 9871021f3fSBenjamin Gaignard clocks = <&timer_clk>; 9971021f3fSBenjamin Gaignard resets = <&rcc 992>; 10071021f3fSBenjamin Gaignard #dma-cells = <5>; 10171021f3fSBenjamin Gaignard dma-channels = <16>; 10271021f3fSBenjamin Gaignard dma-requests = <32>; 10371021f3fSBenjamin Gaignard st,ahb-addr-masks = <0x20000000>, <0x00000000>; 10471021f3fSBenjamin Gaignard }; 10571021f3fSBenjamin Gaignard 10671021f3fSBenjamin Gaignard... 107