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/openbmc/linux/Documentation/devicetree/bindings/sram/
H A Dallwinner,sun4i-a10-system-control.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The SRAM controller found on most Allwinner devices is represented
15 by a regular node for the SRAM controller itself, with sub-nodes
16 representing the SRAM handled by the SRAM controller.
19 "#address-cells":
[all …]
H A Dsram.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sram/sram.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic on-chip SRAM
10 - Rob Herring <robh@kernel.org>
15 Each child of the sram node specifies a region of reserved memory. Each
19 Following the generic-names recommended practice, node names should
25 pattern: "^sram(@.*)?"
30 - mmio-sram
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/openbmc/linux/Documentation/devicetree/bindings/firmware/
H A Darm,scmi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sudeep Holla <sudeep.holla@arm.com>
31 - description: SCMI compliant firmware with mailbox transport
33 - const: arm,scmi
34 - description: SCMI compliant firmware with ARM SMC/HVC transport
36 - const: arm,scmi-smc
37 - description: SCMI compliant firmware with ARM SMC/HVC transport
38 with shmem address(4KB-page, offset) as parameters
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H A Darm,scpi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sudeep Holla <sudeep.holla@arm.com>
33 - const: arm,scpi # SCPI v1.0 and above
34 - const: arm,scpi-pre-1.0 # Unversioned SCPI before v1.0
35 - items:
36 - enum:
37 - amlogic,meson-gxbb-scpi
38 - const: arm,scpi-pre-1.0
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/openbmc/u-boot/tools/binman/etype/
H A Du_boot_ucode.py1 # SPDX-License-Identifier: GPL-2.0+
5 # Entry-type module for a U-Boot binary with an embedded microcode pointer
13 """U-Boot microcode block
21 U-Boot on x86 needs a single block of microcode. This is collected from
25 microcode is supplied before there is any SRAM available to use (i.e.
26 the FSP sets up the SRAM / cache-as-RAM but does so in the call that
28 microcode the same way in U-Boot (even non-FSP platforms). This is that
31 platforms), or used to set up the microcode (for non-FSP platforms).
33 the microcode into a single blob and accessible without SRAM.
37 entry (u-boot-ucode) is empty. If there is more than one update, then
[all …]
H A Du_boot_spl.py1 # SPDX-License-Identifier: GPL-2.0+
5 # Entry-type module for spl/u-boot-spl.bin
14 """U-Boot SPL binary
17 - filename: Filename of u-boot-spl.bin (default 'spl/u-boot-spl.bin')
19 This is the U-Boot SPL (Secondary Program Loader) binary. This is a small
20 binary which loads before U-Boot proper, typically into on-chip SRAM. It is
21 responsible for locating, loading and jumping to U-Boot. Note that SPL is
22 not relocatable so must be loaded to the correct address in SRAM, or written
32 The ELF file 'spl/u-boot-spl' must also be available for this to work, since
35 def __init__(self, section, etype, node): argument
[all …]
H A Du_boot_tpl.py1 # SPDX-License-Identifier: GPL-2.0+
5 # Entry-type module for tpl/u-boot-tpl.bin
14 """U-Boot TPL binary
17 - filename: Filename of u-boot-tpl.bin (default 'tpl/u-boot-tpl.bin')
19 This is the U-Boot TPL (Tertiary Program Loader) binary. This is a small
20 binary which loads before SPL, typically into on-chip SRAM. It is
21 responsible for locating, loading and jumping to SPL, the next-stage
23 address in SRAM, or written to run from the correct address if direct
32 The ELF file 'tpl/u-boot-tpl' must also be available for this to work, since
35 def __init__(self, section, etype, node): argument
[all …]
/openbmc/u-boot/arch/arm/mach-zynq/
H A Du-boot-spl.lds1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright (c) 2004-2008 Texas Instruments
10 MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
15 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
27 } > .sram
32 } > .sram
37 } > .sram
42 } > .sram
50 /* Move BSS section to RAM because of FAT */
/openbmc/linux/arch/arm/boot/dts/allwinner/
H A Dsun5i.dtsi2 * Copyright 2012-2015 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/clock/sun5i-ccu.h>
46 #include <dt-bindings/dma/sun4i-a10.h>
47 #include <dt-bindings/reset/sun5i-ccu.h>
50 interrupt-parent = <&intc>;
51 #address-cells = <1>;
52 #size-cells = <1>;
55 #address-cells = <1>;
[all …]
H A Dsuniv-f1c100s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
7 #include <dt-bindings/clock/suniv-ccu-f1c100s.h>
8 #include <dt-bindings/reset/suniv-ccu-f1c100s.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&intc>;
16 osc24M: clk-24M {
17 #clock-cells = <0>;
18 compatible = "fixed-clock";
19 clock-frequency = <24000000>;
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H A Dsun8i-h3.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include "sunxi-h3-h5.dtsi"
44 #include <dt-bindings/thermal/thermal.h>
47 cpu0_opp_table: opp-table-cpu {
48 compatible = "operating-points-v2";
49 opp-shared;
51 opp-648000000 {
52 opp-hz = /bits/ 64 <648000000>;
53 opp-microvolt = <1040000 1040000 1300000>;
54 clock-latency-ns = <244144>; /* 8 32k periods */
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H A Dsun4i-a10.dtsi5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/thermal/thermal.h>
45 #include <dt-bindings/dma/sun4i-a10.h>
46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50 #address-cells = <1>;
51 #size-cells = <1>;
52 interrupt-parent = <&intc>;
59 #address-cells = <1>;
60 #size-cells = <1>;
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/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dxlnx,zynqmp-r5fss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
17 floating-point unit that implements the Arm VFPv3 instruction set.
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/openbmc/u-boot/drivers/rtc/
H A DKconfig11 Enable drver model for real-time-clock drivers. The RTC uclass
20 Enable drver model for real-time-clock drivers. The RTC uclass
29 Enable drver model for real-time-clock drivers. The RTC uclass
41 has a selectable I2C-bus or SPI-bus, a backup battery switch-over circuit, a
56 calendar with automatic leap year correction, 2-byte battery backed SRAM,
57 automatic power switch-over, alarm function and 15 selectable frequency
67 The MicroCrystal RV3029 is a I2C Real Time Clock (RTC) with 8-byte
68 battery-backed SRAM.
71 battery-baced SRAM section.
102 This is a widely used real-time clock chip originally by Motorola
[all …]
/openbmc/linux/drivers/memory/
H A Dti-emif-pm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI AM33XX SRAM EMIF Driver
5 * Copyright (C) 2016-2017 Texas Instruments Inc.
17 #include <linux/sram.h>
18 #include <linux/ti-emif-sram.h>
22 #define TI_EMIF_SRAM_SYMBOL_OFFSET(sym) ((unsigned long)(sym) - \
43 return (emif_data->ti_emif_sram_virt + in sram_suspend_address()
50 return ((unsigned long)emif_data->ti_emif_sram_phys + in sram_resume_address()
56 gen_pool_free(emif_data->sram_pool_code, emif_data->ti_emif_sram_virt, in ti_emif_free_sram()
58 gen_pool_free(emif_data->sram_pool_data, in ti_emif_free_sram()
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/
H A Dhwinit-common.c1 // SPDX-License-Identifier: GPL-2.0+
33 writew(pad->val, base + pad->offset); in do_set_mux()
107 printf("%x-%s ES%x.%x", omap_variant, sec_s, major_rev, minor_rev); in omap_rev_string()
126 * do_board_detect() - Detect board description
136 * vcores_init() - Assign omap_vcores based on board
150 * init_package_revision() - Initialize package revision
160 * early_system_init - Does Early system initialization.
165 * 1. SPL running from SRAM
166 * 2. U-Boot running from FLASH
167 * 3. U-Boot loaded to SDRAM by SPL
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/openbmc/u-boot/board/cadence/xtfpga/
H A DREADME8 - XT-AV60 / LX60
9 - XT-AV110 / LX110
10 - XT-AV200 / LX200
11 - ML605
12 - KC705
16 - An Xtensa or Diamond processor core.
17 - An on-chip-debug (OCD) JTAG interface.
18 - A 16550 compatible UART and serial port.
19 - An OpenCores Wishbone 10/100-base-T ethernet interface.
20 - A 32 char two line LCD display. (except for the LX200)
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Du-boot-spl.lds1 /* SPDX-License-Identifier: GPL-2.0+ */
34 __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
35 __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
70 /* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */
72 .bootpg ADDR(.text) - 0x1000 :
86 #define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
89 #define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */
/openbmc/u-boot/arch/arm/dts/
H A Dsun8i-h3.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include "sunxi-h3-h5.dtsi"
47 compatible = "operating-points-v2";
48 opp-shared;
51 opp-hz = /bits/ 64 <648000000>;
52 opp-microvolt = <1040000 1040000 1300000>;
53 clock-latency-ns = <244144>; /* 8 32k periods */
57 opp-hz = /bits/ 64 <816000000>;
58 opp-microvolt = <1100000 1100000 1300000>;
59 clock-latency-ns = <244144>; /* 8 32k periods */
[all …]
H A Dsun5i.dtsi2 * Copyright 2012-2015 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/clock/sun5i-ccu.h>
48 #include <dt-bindings/dma/sun4i-a10.h>
49 #include <dt-bindings/reset/sun5i-ccu.h>
52 interrupt-parent = <&intc>;
55 #address-cells = <1>;
56 #size-cells = <0>;
60 compatible = "arm,cortex-a8";
[all …]
/openbmc/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <arm/allwinner/sunxi-h3-h5.dtsi>
6 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <0>;
14 compatible = "arm,cortex-a53";
17 enable-method = "psci";
19 clock-latency-ns = <244144>; /* 8 32k periods */
20 #cooling-cells = <2>;
24 compatible = "arm,cortex-a53";
[all …]
/openbmc/linux/drivers/input/touchscreen/
H A Dgoodix_fwupload.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Copyright (c) 2010 - 2012 Goodix Technology.
54 if (fw->size != expected_size) { in goodix_firmware_verify()
56 expected_size, fw->size); in goodix_firmware_verify()
57 return -EINVAL; in goodix_firmware_verify()
60 data = fw->data + GOODIX_FW_HEADER_LENGTH; in goodix_firmware_verify()
64 return -EINVAL; in goodix_firmware_verify()
71 return -EINVAL; in goodix_firmware_verify()
74 fw_header = (const struct goodix_fw_header *)fw->data; in goodix_firmware_verify()
76 fw_header->hw_info[0], fw_header->hw_info[1], in goodix_firmware_verify()
[all …]
/openbmc/linux/arch/arm/mach-rockchip/
H A Dsleep.S1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Author: Tony Xie <tony.xie@rock-chips.com>
14 * ddr to sram for system resumeing.
15 * so it is ".data section".
64 .word . - rockchip_slp_cpu_resume
/openbmc/linux/Documentation/driver-api/memory-devices/
H A Dti-gpmc.rst1 .. SPDX-License-Identifier: GPL-2.0
10 * Asynchronous SRAM like memories and application specific integrated
14 * Pseudo-SRAM devices
17 IP details: https://www.ti.com/lit/pdf/spruh73 section 7.1
85 4. read async non-muxed
107 6. read sync non-muxed
131 8. write async non-muxed
157 10. write sync non-muxed
/openbmc/u-boot/arch/arm/cpu/
H A Du-boot.lds1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (c) 2004-2008 Texas Instruments
12 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
23 * bundle with u-boot, and code offsets are fixed. Secure zone
29 * be included in u-boot address space, and some absolute address
31 * code also needs to be relocated along with the accompanying u-boot
70 /* Align the secure section only if we're going to use it in situ */
109 /* Align end of stack section to page boundary */
116 * We are not checking (__secure_end - __secure_start) here,
118 * stack section. Instead, use the end of the stack section
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