161b8ac9bSSudeep Holla# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 261b8ac9bSSudeep Holla# Copyright 2021 ARM Ltd. 361b8ac9bSSudeep Holla%YAML 1.2 461b8ac9bSSudeep Holla--- 561b8ac9bSSudeep Holla$id: http://devicetree.org/schemas/firmware/arm,scmi.yaml# 661b8ac9bSSudeep Holla$schema: http://devicetree.org/meta-schemas/core.yaml# 761b8ac9bSSudeep Holla 884e85359SKrzysztof Kozlowskititle: System Control and Management Interface (SCMI) Message Protocol 961b8ac9bSSudeep Holla 1061b8ac9bSSudeep Hollamaintainers: 1161b8ac9bSSudeep Holla - Sudeep Holla <sudeep.holla@arm.com> 1261b8ac9bSSudeep Holla 1361b8ac9bSSudeep Holladescription: | 1461b8ac9bSSudeep Holla The SCMI is intended to allow agents such as OSPM to manage various functions 1561b8ac9bSSudeep Holla that are provided by the hardware platform it is running on, including power 1661b8ac9bSSudeep Holla and performance functions. 1761b8ac9bSSudeep Holla 1861b8ac9bSSudeep Holla This binding is intended to define the interface the firmware implementing 1961b8ac9bSSudeep Holla the SCMI as described in ARM document number ARM DEN 0056 ("ARM System Control 2061b8ac9bSSudeep Holla and Management Interface Platform Design Document")[0] provide for OSPM in 2161b8ac9bSSudeep Holla the device tree. 2261b8ac9bSSudeep Holla 2361b8ac9bSSudeep Holla [0] https://developer.arm.com/documentation/den0056/latest 2461b8ac9bSSudeep Holla 2561b8ac9bSSudeep Hollaproperties: 2661b8ac9bSSudeep Holla $nodename: 2761b8ac9bSSudeep Holla const: scmi 2861b8ac9bSSudeep Holla 2961b8ac9bSSudeep Holla compatible: 3061b8ac9bSSudeep Holla oneOf: 3161b8ac9bSSudeep Holla - description: SCMI compliant firmware with mailbox transport 3261b8ac9bSSudeep Holla items: 3361b8ac9bSSudeep Holla - const: arm,scmi 3461b8ac9bSSudeep Holla - description: SCMI compliant firmware with ARM SMC/HVC transport 3561b8ac9bSSudeep Holla items: 3661b8ac9bSSudeep Holla - const: arm,scmi-smc 3760625667SIgor Skalkin - description: SCMI compliant firmware with ARM SMC/HVC transport 3860625667SIgor Skalkin with shmem address(4KB-page, offset) as parameters 3960625667SIgor Skalkin items: 4060625667SIgor Skalkin - const: arm,scmi-smc-param 41b7d2cf7cSEtienne Carriere - description: SCMI compliant firmware with SCMI Virtio transport. 42b7d2cf7cSEtienne Carriere The virtio transport only supports a single device. 43b7d2cf7cSEtienne Carriere items: 4461b8ac9bSSudeep Holla - const: arm,scmi-virtio 4561b8ac9bSSudeep Holla - description: SCMI compliant firmware with OP-TEE transport 4661b8ac9bSSudeep Holla items: 4761b8ac9bSSudeep Holla - const: linaro,scmi-optee 4861b8ac9bSSudeep Holla 4961b8ac9bSSudeep Holla interrupts: 5061b8ac9bSSudeep Holla description: 5161b8ac9bSSudeep Holla The interrupt that indicates message completion by the platform 5261b8ac9bSSudeep Holla rather than by the return of the smc call. This should not be used 5361b8ac9bSSudeep Holla except when the platform requires such behavior. 5461b8ac9bSSudeep Holla maxItems: 1 5561b8ac9bSSudeep Holla 5661b8ac9bSSudeep Holla interrupt-names: 5761b8ac9bSSudeep Holla const: a2p 5861b8ac9bSSudeep Holla 5992ac94f7SCristian Marussi mbox-names: 6092ac94f7SCristian Marussi description: 6161b8ac9bSSudeep Holla Specifies the mailboxes used to communicate with SCMI compliant 6261b8ac9bSSudeep Holla firmware. 6392ac94f7SCristian Marussi oneOf: 6492ac94f7SCristian Marussi - items: 6592ac94f7SCristian Marussi - const: tx 6692ac94f7SCristian Marussi - const: rx 6792ac94f7SCristian Marussi minItems: 1 6892ac94f7SCristian Marussi - items: 6961b8ac9bSSudeep Holla - const: tx 7061b8ac9bSSudeep Holla - const: tx_reply 7161b8ac9bSSudeep Holla - const: rx 7261b8ac9bSSudeep Holla minItems: 2 7392ac94f7SCristian Marussi 7492ac94f7SCristian Marussi mboxes: 7592ac94f7SCristian Marussi description: 7692ac94f7SCristian Marussi List of phandle and mailbox channel specifiers. It should contain 7792ac94f7SCristian Marussi exactly one, two or three mailboxes; the first one or two for transmitting 7892ac94f7SCristian Marussi messages ("tx") and another optional ("rx") for receiving notifications 7992ac94f7SCristian Marussi and delayed responses, if supported by the platform. 8092ac94f7SCristian Marussi The number of mailboxes needed for transmitting messages depends on the 8192ac94f7SCristian Marussi type of channels exposed by the specific underlying mailbox controller; 8292ac94f7SCristian Marussi one single channel descriptor is enough if such channel is bidirectional, 8392ac94f7SCristian Marussi while two channel descriptors are needed to represent the SCMI ("tx") 8492ac94f7SCristian Marussi channel if the underlying mailbox channels are of unidirectional type. 8592ac94f7SCristian Marussi The effective combination in numbers of mboxes and shmem descriptors let 8692ac94f7SCristian Marussi the SCMI subsystem determine unambiguosly which type of SCMI channels are 8792ac94f7SCristian Marussi made available by the underlying mailbox controller and how to use them. 8892ac94f7SCristian Marussi 1 mbox / 1 shmem => SCMI TX over 1 mailbox bidirectional channel 8961b8ac9bSSudeep Holla 2 mbox / 2 shmem => SCMI TX and RX over 2 mailbox bidirectional channels 9092ac94f7SCristian Marussi 2 mbox / 1 shmem => SCMI TX over 2 mailbox unidirectional channels 9161b8ac9bSSudeep Holla 3 mbox / 2 shmem => SCMI TX and RX over 3 mailbox unidirectional channels 9261b8ac9bSSudeep Holla Any other combination of mboxes and shmem is invalid. 9361b8ac9bSSudeep Holla minItems: 1 9461b8ac9bSSudeep Holla maxItems: 3 9561b8ac9bSSudeep Holla 9661b8ac9bSSudeep Holla shmem: 9761b8ac9bSSudeep Holla description: 9861b8ac9bSSudeep Holla List of phandle pointing to the shared memory(SHM) area, for each 9961b8ac9bSSudeep Holla transport channel specified. 10061b8ac9bSSudeep Holla minItems: 1 10161b8ac9bSSudeep Holla maxItems: 2 10261b8ac9bSSudeep Holla 10361b8ac9bSSudeep Holla '#address-cells': 10461b8ac9bSSudeep Holla const: 1 1050539884cSCristian Marussi 1060539884cSCristian Marussi '#size-cells': 1070539884cSCristian Marussi const: 0 1080539884cSCristian Marussi 1090539884cSCristian Marussi atomic-threshold-us: 1100539884cSCristian Marussi description: 1110539884cSCristian Marussi An optional time value, expressed in microseconds, representing, on this 1120539884cSCristian Marussi platform, the threshold above which any SCMI command, advertised to have 11361b8ac9bSSudeep Holla an higher-than-threshold execution latency, should not be considered for 11461b8ac9bSSudeep Holla atomic mode of operation, even if requested. 11561b8ac9bSSudeep Holla default: 0 11661b8ac9bSSudeep Holla 11761b8ac9bSSudeep Holla arm,smc-id: 118b7d2cf7cSEtienne Carriere $ref: /schemas/types.yaml#/definitions/uint32 119b7d2cf7cSEtienne Carriere description: 120b7d2cf7cSEtienne Carriere SMC id required when using smc or hvc transports 121b7d2cf7cSEtienne Carriere 122b7d2cf7cSEtienne Carriere linaro,optee-channel-id: 12361b8ac9bSSudeep Holla $ref: /schemas/types.yaml#/definitions/uint32 124df4fdd0dSRob Herring description: 125df4fdd0dSRob Herring Channel specifier required when using OP-TEE transport. 126df4fdd0dSRob Herring 12761b8ac9bSSudeep Holla protocol@11: 12861b8ac9bSSudeep Holla $ref: '#/$defs/protocol-node' 12961b8ac9bSSudeep Holla unevaluatedProperties: false 13061b8ac9bSSudeep Holla 13161b8ac9bSSudeep Holla properties: 13261b8ac9bSSudeep Holla reg: 13361b8ac9bSSudeep Holla const: 0x11 13461b8ac9bSSudeep Holla 13561b8ac9bSSudeep Holla '#power-domain-cells': 13661b8ac9bSSudeep Holla const: 1 13761b8ac9bSSudeep Holla 138df4fdd0dSRob Herring required: 139df4fdd0dSRob Herring - '#power-domain-cells' 140df4fdd0dSRob Herring 14161b8ac9bSSudeep Holla protocol@13: 14261b8ac9bSSudeep Holla $ref: '#/$defs/protocol-node' 14361b8ac9bSSudeep Holla unevaluatedProperties: false 14461b8ac9bSSudeep Holla 14561b8ac9bSSudeep Holla properties: 14661b8ac9bSSudeep Holla reg: 14761b8ac9bSSudeep Holla const: 0x13 14861b8ac9bSSudeep Holla 14961b8ac9bSSudeep Holla '#clock-cells': 15061b8ac9bSSudeep Holla const: 1 15161b8ac9bSSudeep Holla 152df4fdd0dSRob Herring required: 153df4fdd0dSRob Herring - '#clock-cells' 154df4fdd0dSRob Herring 15561b8ac9bSSudeep Holla protocol@14: 15661b8ac9bSSudeep Holla $ref: '#/$defs/protocol-node' 15761b8ac9bSSudeep Holla unevaluatedProperties: false 15861b8ac9bSSudeep Holla 15961b8ac9bSSudeep Holla properties: 16061b8ac9bSSudeep Holla reg: 16161b8ac9bSSudeep Holla const: 0x14 16261b8ac9bSSudeep Holla 16361b8ac9bSSudeep Holla '#clock-cells': 16461b8ac9bSSudeep Holla const: 1 16561b8ac9bSSudeep Holla 166df4fdd0dSRob Herring required: 167df4fdd0dSRob Herring - '#clock-cells' 168df4fdd0dSRob Herring 16961b8ac9bSSudeep Holla protocol@15: 17061b8ac9bSSudeep Holla $ref: '#/$defs/protocol-node' 17161b8ac9bSSudeep Holla unevaluatedProperties: false 17261b8ac9bSSudeep Holla 17361b8ac9bSSudeep Holla properties: 17461b8ac9bSSudeep Holla reg: 17561b8ac9bSSudeep Holla const: 0x15 17661b8ac9bSSudeep Holla 17761b8ac9bSSudeep Holla '#thermal-sensor-cells': 17861b8ac9bSSudeep Holla const: 1 17961b8ac9bSSudeep Holla 180df4fdd0dSRob Herring required: 181df4fdd0dSRob Herring - '#thermal-sensor-cells' 182df4fdd0dSRob Herring 18361b8ac9bSSudeep Holla protocol@16: 18461b8ac9bSSudeep Holla $ref: '#/$defs/protocol-node' 18561b8ac9bSSudeep Holla unevaluatedProperties: false 18661b8ac9bSSudeep Holla 18761b8ac9bSSudeep Holla properties: 18861b8ac9bSSudeep Holla reg: 18961b8ac9bSSudeep Holla const: 0x16 19061b8ac9bSSudeep Holla 19161b8ac9bSSudeep Holla '#reset-cells': 19261b8ac9bSSudeep Holla const: 1 19361b8ac9bSSudeep Holla 194df4fdd0dSRob Herring required: 195df4fdd0dSRob Herring - '#reset-cells' 196df4fdd0dSRob Herring 19761b8ac9bSSudeep Holla protocol@17: 19861b8ac9bSSudeep Holla $ref: '#/$defs/protocol-node' 19961b8ac9bSSudeep Holla unevaluatedProperties: false 20061b8ac9bSSudeep Holla 20161b8ac9bSSudeep Holla properties: 20261b8ac9bSSudeep Holla reg: 203df4fdd0dSRob Herring const: 0x17 20461b8ac9bSSudeep Holla 20561b8ac9bSSudeep Holla regulators: 20661b8ac9bSSudeep Holla type: object 207df4fdd0dSRob Herring additionalProperties: false 208df4fdd0dSRob Herring description: 209df4fdd0dSRob Herring The list of all regulators provided by this SCMI controller. 210df4fdd0dSRob Herring 211df4fdd0dSRob Herring properties: 212df4fdd0dSRob Herring '#address-cells': 213df4fdd0dSRob Herring const: 1 21461b8ac9bSSudeep Holla 215df4fdd0dSRob Herring '#size-cells': 21661b8ac9bSSudeep Holla const: 0 217*7123c05cSKrzysztof Kozlowski 218df4fdd0dSRob Herring patternProperties: 21961b8ac9bSSudeep Holla '^regulator@[0-9a-f]+$': 22061b8ac9bSSudeep Holla type: object 22161b8ac9bSSudeep Holla $ref: /schemas/regulator/regulator.yaml# 22261b8ac9bSSudeep Holla unevaluatedProperties: false 22361b8ac9bSSudeep Holla 22461b8ac9bSSudeep Holla properties: 22561b8ac9bSSudeep Holla reg: 22661b8ac9bSSudeep Holla maxItems: 1 22761b8ac9bSSudeep Holla description: Identifier for the voltage regulator. 228451d8457SCristian Marussi 229df4fdd0dSRob Herring required: 230df4fdd0dSRob Herring - reg 231df4fdd0dSRob Herring 232451d8457SCristian Marussi protocol@18: 233451d8457SCristian Marussi $ref: '#/$defs/protocol-node' 234451d8457SCristian Marussi unevaluatedProperties: false 235451d8457SCristian Marussi 23661b8ac9bSSudeep Holla properties: 23761b8ac9bSSudeep Holla reg: 238df4fdd0dSRob Herring const: 0x18 239df4fdd0dSRob Herring 24061b8ac9bSSudeep HollaadditionalProperties: false 24161b8ac9bSSudeep Holla 24261b8ac9bSSudeep Holla$defs: 24361b8ac9bSSudeep Holla protocol-node: 24461b8ac9bSSudeep Holla type: object 24560625667SIgor Skalkin description: 24661b8ac9bSSudeep Holla Each sub-node represents a protocol supported. If the platform 24761b8ac9bSSudeep Holla supports a dedicated communication channel for a particular protocol, 24861b8ac9bSSudeep Holla then the corresponding transport properties must be present. 24961b8ac9bSSudeep Holla The virtio transport does not support a dedicated communication channel. 25061b8ac9bSSudeep Holla 25161b8ac9bSSudeep Holla properties: 25292ac94f7SCristian Marussi reg: 25392ac94f7SCristian Marussi maxItems: 1 25461b8ac9bSSudeep Holla 25561b8ac9bSSudeep Holla mbox-names: 25692ac94f7SCristian Marussi oneOf: 25792ac94f7SCristian Marussi - items: 25892ac94f7SCristian Marussi - const: tx 25992ac94f7SCristian Marussi - const: rx 26092ac94f7SCristian Marussi minItems: 1 26192ac94f7SCristian Marussi - items: 26261b8ac9bSSudeep Holla - const: tx 26361b8ac9bSSudeep Holla - const: tx_reply 26461b8ac9bSSudeep Holla - const: rx 26592ac94f7SCristian Marussi minItems: 2 26661b8ac9bSSudeep Holla 26761b8ac9bSSudeep Holla mboxes: 26861b8ac9bSSudeep Holla minItems: 1 26961b8ac9bSSudeep Holla maxItems: 3 27061b8ac9bSSudeep Holla 271b7d2cf7cSEtienne Carriere shmem: 272b7d2cf7cSEtienne Carriere minItems: 1 273b7d2cf7cSEtienne Carriere maxItems: 2 274b7d2cf7cSEtienne Carriere 275b7d2cf7cSEtienne Carriere linaro,optee-channel-id: 276b7d2cf7cSEtienne Carriere $ref: /schemas/types.yaml#/definitions/uint32 27761b8ac9bSSudeep Holla description: 27861b8ac9bSSudeep Holla Channel specifier required when using OP-TEE transport and 27961b8ac9bSSudeep Holla protocol has a dedicated communication channel. 28061b8ac9bSSudeep Holla 28161b8ac9bSSudeep Holla required: 28261b8ac9bSSudeep Holla - reg 28361b8ac9bSSudeep Holla 28461b8ac9bSSudeep Hollarequired: 28561b8ac9bSSudeep Holla - compatible 28661b8ac9bSSudeep Holla 28761b8ac9bSSudeep Hollaif: 28861b8ac9bSSudeep Holla properties: 28961b8ac9bSSudeep Holla compatible: 29061b8ac9bSSudeep Holla contains: 29161b8ac9bSSudeep Holla const: arm,scmi 29261b8ac9bSSudeep Hollathen: 29361b8ac9bSSudeep Holla properties: 29461b8ac9bSSudeep Holla interrupts: false 29560625667SIgor Skalkin interrupt-names: false 29661b8ac9bSSudeep Holla 29761b8ac9bSSudeep Holla required: 29861b8ac9bSSudeep Holla - mboxes 29961b8ac9bSSudeep Holla - shmem 30061b8ac9bSSudeep Holla 30161b8ac9bSSudeep Hollaelse: 30261b8ac9bSSudeep Holla if: 30361b8ac9bSSudeep Holla properties: 30461b8ac9bSSudeep Holla compatible: 30561b8ac9bSSudeep Holla contains: 30660625667SIgor Skalkin enum: 30761b8ac9bSSudeep Holla - arm,scmi-smc 308b7d2cf7cSEtienne Carriere - arm,scmi-smc-param 309b7d2cf7cSEtienne Carriere then: 310b7d2cf7cSEtienne Carriere required: 311b7d2cf7cSEtienne Carriere - arm,smc-id 312b7d2cf7cSEtienne Carriere - shmem 313b7d2cf7cSEtienne Carriere 314b7d2cf7cSEtienne Carriere else: 315b7d2cf7cSEtienne Carriere if: 316b7d2cf7cSEtienne Carriere properties: 317b7d2cf7cSEtienne Carriere compatible: 31861b8ac9bSSudeep Holla contains: 31961b8ac9bSSudeep Holla const: linaro,scmi-optee 32061b8ac9bSSudeep Holla then: 32161b8ac9bSSudeep Holla required: 32261b8ac9bSSudeep Holla - linaro,optee-channel-id 32361b8ac9bSSudeep Holla 32461b8ac9bSSudeep Hollaexamples: 32561b8ac9bSSudeep Holla - | 32661b8ac9bSSudeep Holla firmware { 32761b8ac9bSSudeep Holla scmi { 32861b8ac9bSSudeep Holla compatible = "arm,scmi"; 32961b8ac9bSSudeep Holla mboxes = <&mhuB 0 0>, 33061b8ac9bSSudeep Holla <&mhuB 0 1>; 33161b8ac9bSSudeep Holla mbox-names = "tx", "rx"; 3320539884cSCristian Marussi shmem = <&cpu_scp_lpri0>, 3330539884cSCristian Marussi <&cpu_scp_lpri1>; 33461b8ac9bSSudeep Holla 33561b8ac9bSSudeep Holla #address-cells = <1>; 33661b8ac9bSSudeep Holla #size-cells = <0>; 33761b8ac9bSSudeep Holla 33861b8ac9bSSudeep Holla atomic-threshold-us = <10000>; 33961b8ac9bSSudeep Holla 34061b8ac9bSSudeep Holla scmi_devpd: protocol@11 { 34161b8ac9bSSudeep Holla reg = <0x11>; 34261b8ac9bSSudeep Holla #power-domain-cells = <1>; 34361b8ac9bSSudeep Holla }; 34461b8ac9bSSudeep Holla 34561b8ac9bSSudeep Holla scmi_dvfs: protocol@13 { 34661b8ac9bSSudeep Holla reg = <0x13>; 34761b8ac9bSSudeep Holla #clock-cells = <1>; 34861b8ac9bSSudeep Holla 34961b8ac9bSSudeep Holla mboxes = <&mhuB 1 0>, 35061b8ac9bSSudeep Holla <&mhuB 1 1>; 35161b8ac9bSSudeep Holla mbox-names = "tx", "rx"; 35261b8ac9bSSudeep Holla shmem = <&cpu_scp_hpri0>, 35361b8ac9bSSudeep Holla <&cpu_scp_hpri1>; 35461b8ac9bSSudeep Holla }; 35561b8ac9bSSudeep Holla 35661b8ac9bSSudeep Holla scmi_clk: protocol@14 { 35761b8ac9bSSudeep Holla reg = <0x14>; 35861b8ac9bSSudeep Holla #clock-cells = <1>; 35961b8ac9bSSudeep Holla }; 36061b8ac9bSSudeep Holla 36161b8ac9bSSudeep Holla scmi_sensors: protocol@15 { 36261b8ac9bSSudeep Holla reg = <0x15>; 36361b8ac9bSSudeep Holla #thermal-sensor-cells = <1>; 36461b8ac9bSSudeep Holla }; 36561b8ac9bSSudeep Holla 36661b8ac9bSSudeep Holla scmi_reset: protocol@16 { 36761b8ac9bSSudeep Holla reg = <0x16>; 36861b8ac9bSSudeep Holla #reset-cells = <1>; 36961b8ac9bSSudeep Holla }; 37061b8ac9bSSudeep Holla 37161b8ac9bSSudeep Holla scmi_voltage: protocol@17 { 37261b8ac9bSSudeep Holla reg = <0x17>; 37361b8ac9bSSudeep Holla regulators { 37461b8ac9bSSudeep Holla #address-cells = <1>; 37561b8ac9bSSudeep Holla #size-cells = <0>; 37661b8ac9bSSudeep Holla 37761b8ac9bSSudeep Holla regulator_devX: regulator@0 { 37861b8ac9bSSudeep Holla reg = <0x0>; 37961b8ac9bSSudeep Holla regulator-max-microvolt = <3300000>; 38061b8ac9bSSudeep Holla }; 38161b8ac9bSSudeep Holla 38261b8ac9bSSudeep Holla regulator_devY: regulator@9 { 383451d8457SCristian Marussi reg = <0x9>; 384451d8457SCristian Marussi regulator-min-microvolt = <500000>; 385451d8457SCristian Marussi regulator-max-microvolt = <4200000>; 386451d8457SCristian Marussi }; 38761b8ac9bSSudeep Holla }; 38861b8ac9bSSudeep Holla }; 38961b8ac9bSSudeep Holla 39061b8ac9bSSudeep Holla scmi_powercap: protocol@18 { 39161b8ac9bSSudeep Holla reg = <0x18>; 39261b8ac9bSSudeep Holla }; 39361b8ac9bSSudeep Holla }; 39461b8ac9bSSudeep Holla }; 39561b8ac9bSSudeep Holla 39661b8ac9bSSudeep Holla soc { 39761b8ac9bSSudeep Holla #address-cells = <2>; 39861b8ac9bSSudeep Holla #size-cells = <2>; 39961b8ac9bSSudeep Holla 40061b8ac9bSSudeep Holla sram@50000000 { 40161b8ac9bSSudeep Holla compatible = "mmio-sram"; 40261b8ac9bSSudeep Holla reg = <0x0 0x50000000 0x0 0x10000>; 40361b8ac9bSSudeep Holla 40461b8ac9bSSudeep Holla #address-cells = <1>; 40561b8ac9bSSudeep Holla #size-cells = <1>; 40661b8ac9bSSudeep Holla ranges = <0 0x0 0x50000000 0x10000>; 40761b8ac9bSSudeep Holla 40861b8ac9bSSudeep Holla cpu_scp_lpri0: scp-sram-section@0 { 40961b8ac9bSSudeep Holla compatible = "arm,scmi-shmem"; 41061b8ac9bSSudeep Holla reg = <0x0 0x80>; 41161b8ac9bSSudeep Holla }; 41261b8ac9bSSudeep Holla 41361b8ac9bSSudeep Holla cpu_scp_lpri1: scp-sram-section@80 { 41461b8ac9bSSudeep Holla compatible = "arm,scmi-shmem"; 41561b8ac9bSSudeep Holla reg = <0x80 0x80>; 41661b8ac9bSSudeep Holla }; 41761b8ac9bSSudeep Holla 41861b8ac9bSSudeep Holla cpu_scp_hpri0: scp-sram-section@100 { 41961b8ac9bSSudeep Holla compatible = "arm,scmi-shmem"; 42061b8ac9bSSudeep Holla reg = <0x100 0x80>; 42161b8ac9bSSudeep Holla }; 42261b8ac9bSSudeep Holla 42361b8ac9bSSudeep Holla cpu_scp_hpri2: scp-sram-section@180 { 42461b8ac9bSSudeep Holla compatible = "arm,scmi-shmem"; 42561b8ac9bSSudeep Holla reg = <0x180 0x80>; 42661b8ac9bSSudeep Holla }; 42761b8ac9bSSudeep Holla }; 42839bd2b6aSRob Herring }; 42961b8ac9bSSudeep Holla 43061b8ac9bSSudeep Holla - | 43161b8ac9bSSudeep Holla firmware { 43261b8ac9bSSudeep Holla scmi { 43361b8ac9bSSudeep Holla compatible = "arm,scmi-smc"; 43461b8ac9bSSudeep Holla shmem = <&cpu_scp_lpri0>, <&cpu_scp_lpri1>; 43561b8ac9bSSudeep Holla arm,smc-id = <0xc3000001>; 43661b8ac9bSSudeep Holla 43761b8ac9bSSudeep Holla #address-cells = <1>; 438b7d2cf7cSEtienne Carriere #size-cells = <0>; 439b7d2cf7cSEtienne Carriere 44061b8ac9bSSudeep Holla scmi_devpd1: protocol@11 { 441b7d2cf7cSEtienne Carriere reg = <0x11>; 442b7d2cf7cSEtienne Carriere #power-domain-cells = <1>; 443b7d2cf7cSEtienne Carriere }; 444b7d2cf7cSEtienne Carriere }; 445b7d2cf7cSEtienne Carriere }; 446b7d2cf7cSEtienne Carriere 447b7d2cf7cSEtienne Carriere - | 448b7d2cf7cSEtienne Carriere firmware { 449b7d2cf7cSEtienne Carriere scmi { 450b7d2cf7cSEtienne Carriere compatible = "linaro,scmi-optee"; 451b7d2cf7cSEtienne Carriere linaro,optee-channel-id = <0>; 452b7d2cf7cSEtienne Carriere 453b7d2cf7cSEtienne Carriere #address-cells = <1>; 454b7d2cf7cSEtienne Carriere #size-cells = <0>; 455b7d2cf7cSEtienne Carriere 456b7d2cf7cSEtienne Carriere scmi_dvfs1: protocol@13 { 457b7d2cf7cSEtienne Carriere reg = <0x13>; 458b7d2cf7cSEtienne Carriere linaro,optee-channel-id = <1>; 459b7d2cf7cSEtienne Carriere shmem = <&cpu_optee_lpri0>; 460b7d2cf7cSEtienne Carriere #clock-cells = <1>; 461b7d2cf7cSEtienne Carriere }; 462b7d2cf7cSEtienne Carriere 463b7d2cf7cSEtienne Carriere scmi_clk0: protocol@14 { 464b7d2cf7cSEtienne Carriere reg = <0x14>; 465b7d2cf7cSEtienne Carriere #clock-cells = <1>; 466b7d2cf7cSEtienne Carriere }; 467b7d2cf7cSEtienne Carriere }; 468b7d2cf7cSEtienne Carriere }; 469b7d2cf7cSEtienne Carriere 470b7d2cf7cSEtienne Carriere soc { 471b7d2cf7cSEtienne Carriere #address-cells = <2>; 472b7d2cf7cSEtienne Carriere #size-cells = <2>; 473b7d2cf7cSEtienne Carriere 474b7d2cf7cSEtienne Carriere sram@51000000 { 475b7d2cf7cSEtienne Carriere compatible = "mmio-sram"; 476b7d2cf7cSEtienne Carriere reg = <0x0 0x51000000 0x0 0x10000>; 477b7d2cf7cSEtienne Carriere 478b7d2cf7cSEtienne Carriere #address-cells = <1>; 479b7d2cf7cSEtienne Carriere #size-cells = <1>; 48061b8ac9bSSudeep Holla ranges = <0 0x0 0x51000000 0x10000>; 48161b8ac9bSSudeep Holla 48261b8ac9bSSudeep Holla cpu_optee_lpri0: optee-sram-section@0 { 48361b8ac9bSSudeep Holla compatible = "arm,scmi-shmem"; 484 reg = <0x0 0x80>; 485 }; 486 }; 487 }; 488 489... 490