1*7e270ec3SChris Zankel Tensilica 'xtfpga' Evaluation Boards 2*7e270ec3SChris Zankel ==================================== 3*7e270ec3SChris Zankel 4*7e270ec3SChris ZankelTensilica's 'xtfpga' evaluation boards are actually a set of different 5*7e270ec3SChris Zankelboards that share configurations. The following is a list of supported 6*7e270ec3SChris Zankelhardware by this board type: 7*7e270ec3SChris Zankel 8*7e270ec3SChris Zankel- XT-AV60 / LX60 9*7e270ec3SChris Zankel- XT-AV110 / LX110 10*7e270ec3SChris Zankel- XT-AV200 / LX200 11*7e270ec3SChris Zankel- ML605 12*7e270ec3SChris Zankel- KC705 13*7e270ec3SChris Zankel 14*7e270ec3SChris ZankelAll boards provide the following common configurations: 15*7e270ec3SChris Zankel 16*7e270ec3SChris Zankel- An Xtensa or Diamond processor core. 17*7e270ec3SChris Zankel- An on-chip-debug (OCD) JTAG interface. 18*7e270ec3SChris Zankel- A 16550 compatible UART and serial port. 19*7e270ec3SChris Zankel- An OpenCores Wishbone 10/100-base-T ethernet interface. 20*7e270ec3SChris Zankel- A 32 char two line LCD display. (except for the LX200) 21*7e270ec3SChris Zankel 22*7e270ec3SChris ZankelLX60/LX110/LX200: 23*7e270ec3SChris Zankel 24*7e270ec3SChris Zankel- Virtex-4 (XC4VLX60 / XCV4LX200) / Virtext-5 (XC5VLX110) 25*7e270ec3SChris Zankel- 128MB / 64MB (LX60) memory 26*7e270ec3SChris Zankel- 16MB / 4MB (LX60) Linear Flash 27*7e270ec3SChris Zankel 28*7e270ec3SChris ZankelML605 29*7e270ec3SChris Zankel 30*7e270ec3SChris Zankel- Virtex-6 (XC6VLX240T) 31*7e270ec3SChris Zankel- 512MB DDR3 memory 32*7e270ec3SChris Zankel- 16MB Linear BPI Flash 33*7e270ec3SChris Zankel 34*7e270ec3SChris ZankelKC705 (Xilinx) 35*7e270ec3SChris Zankel 36*7e270ec3SChris Zankel- Kintex-7 XC7K325T FPGA 37*7e270ec3SChris Zankel- 1GB DDR3 memory 38*7e270ec3SChris Zankel- 128MB Linear BPI Flash 39*7e270ec3SChris Zankel 40*7e270ec3SChris Zankel 41*7e270ec3SChris ZankelSetting up the Board 42*7e270ec3SChris Zankel-------------------- 43*7e270ec3SChris Zankel 44*7e270ec3SChris ZankelThe serial port defaults to 115200 baud, no parity and 1 stop bit. 45*7e270ec3SChris ZankelA terminal emulator must be set accordingly to see the U-Boot prompt. 46*7e270ec3SChris Zankel 47*7e270ec3SChris Zankel 48*7e270ec3SChris ZankelBoard Configurations LX60/LX110/LX200/ML605/KC705 49*7e270ec3SChris Zankel------------------------------------------------- 50*7e270ec3SChris Zankel 51*7e270ec3SChris ZankelThe LX60/LX110/LX200/ML605 contain an 8-way DIP switch that controls 52*7e270ec3SChris Zankelthe boot mapping and selects from a range of default ethernet MAC 53*7e270ec3SChris Zankeladdresses. 54*7e270ec3SChris Zankel 55*7e270ec3SChris ZankelBoot Mapping (DIP switch 8): 56*7e270ec3SChris Zankel 57*7e270ec3SChris Zankel DIP switch 8 maps the system ROM address space (in which the 58*7e270ec3SChris Zankel reset vector resides) to either SRAM (off, 0, down) or Flash 59*7e270ec3SChris Zankel (on, 1, up). This mapping is implemented in the FPGA bitstream 60*7e270ec3SChris Zankel and cannot be disabled by software, therefore DIP switch 8 is no 61*7e270ec3SChris Zankel available for application use. Note DIP switch 7 is reserved by 62*7e270ec3SChris Zankel Tensilica for future possible hardware use. 63*7e270ec3SChris Zankel 64*7e270ec3SChris Zankel Mapping to SRAM allows U-Boot to be debugged with an OCD/JTAG 65*7e270ec3SChris Zankel tool such as the Xtensa OCD Daemon connected via a suppored probe. 66*7e270ec3SChris Zankel See the tools documentation for supported probes and how to 67*7e270ec3SChris Zankel connect them. Be aware that the board has only 128 KB of SRAM, 68*7e270ec3SChris Zankel therefore U-Boot must fit within this space to debug an image 69*7e270ec3SChris Zankel intended for the Flash. This issues is discussed in a separate 70*7e270ec3SChris Zankel section toward the end. 71*7e270ec3SChris Zankel 72*7e270ec3SChris Zankel Mapping to flash allows U-Boot to start on reset, provided it 73*7e270ec3SChris Zankel has been programmed into the first two 64 KB sectors of the Flash. 74*7e270ec3SChris Zankel 75*7e270ec3SChris Zankel The Flash is always mapped at a device (memory mapped I/O) address 76*7e270ec3SChris Zankel (the address is board specific and is expressed as CFG_FLASH_BASE). 77*7e270ec3SChris Zankel The device address is used by U-Boot to program the flash, and may 78*7e270ec3SChris Zankel be used to specify an application to run or U-Boot image to boot. 79*7e270ec3SChris Zankel 80*7e270ec3SChris ZankelDefault MAC Address (DIP switches 1-6): 81*7e270ec3SChris Zankel 82*7e270ec3SChris Zankel When the board is first powered on, or after the environment has 83*7e270ec3SChris Zankel been reinitialized, the ethernet MAC address receives a default 84*7e270ec3SChris Zankel value whose least significant 6 bits come from DIP switches 1-6. 85*7e270ec3SChris Zankel The default is 00:50:C2:13:6F:xx where xx ranges from 0..3F 86*7e270ec3SChris Zankel according to the DIP switches, where "on"==1 and "off"==0, and 87*7e270ec3SChris Zankel switch 1 is the least-significant bit. 88*7e270ec3SChris Zankel 89*7e270ec3SChris Zankel After initial startup, the MAC address is stored in the U-Boot 90*7e270ec3SChris Zankel environment variable 'ethaddr'. The user may change this to any 91*7e270ec3SChris Zankel other address with the "setenv" comamnd. After the environment 92*7e270ec3SChris Zankel has been saved to Flash by the "saveenv" command, this will be 93*7e270ec3SChris Zankel used and the DIP switches no longer consulted. DIP swithes 1-6 94*7e270ec3SChris Zankel may then be used for application purposes. 95*7e270ec3SChris Zankel 96*7e270ec3SChris ZankelThe KC705 board contains 4-way DIP switch, way 1 is the boot mapping 97*7e270ec3SChris Zankelswitch and ways 2-4 control the low three bits of the MAC address. 98*7e270ec3SChris Zankel 99*7e270ec3SChris Zankel 100*7e270ec3SChris ZankelLimitation of SDRAM Size for OCD Debugging on the LX60 101*7e270ec3SChris Zankel------------------------------------------------------ 102*7e270ec3SChris Zankel 103*7e270ec3SChris ZankelThe XT-AV60 board has only 128 KB of SDRAM that can be mapped 104*7e270ec3SChris Zankelto the system ROM address space for debugging a ROM image under 105*7e270ec3SChris ZankelOCD/JTAG. This limits the useful size of U-Boot to 128 KB (0x20000) 106*7e270ec3SChris Zankelor the first 2 sectors of the flash. 107*7e270ec3SChris Zankel 108*7e270ec3SChris ZankelThis can pose a problem if all the sources are compiled with -O0 109*7e270ec3SChris Zankelfor debugging. The code size is then too large, in which case it 110*7e270ec3SChris Zankelwould be necessary to temporarily alter the linker script to place 111*7e270ec3SChris Zankelthe load addresses (LMA) in the RAM (VMA) so that OCD loads U-Boot 112*7e270ec3SChris Zankeldirectly there and does not unpack. In practice this is not really 113*7e270ec3SChris Zankelnecessary as long as only a limited set of sources need to be 114*7e270ec3SChris Zankeldebugged, because the image can still fit into the 128 KB SRAM. 115*7e270ec3SChris Zankel 116*7e270ec3SChris ZankelThe recommended procedure for debugging is to first build U-Boot 117*7e270ec3SChris Zankelwith the default optimization level (-Os), and then touch and 118*7e270ec3SChris Zankelrebuild incrementally with -O0 so that only the touched sources 119*7e270ec3SChris Zankelare recompiled with -O0. To build with -O0, pass it in the KCFLAGS 120*7e270ec3SChris Zankelvariable to make. 121*7e270ec3SChris Zankel 122*7e270ec3SChris ZankelBecause this problem is easy to fall into and difficult to debug 123*7e270ec3SChris Zankelif one doesn't expect it, the linker script provides a link-time 124*7e270ec3SChris Zankelcheck and fatal error message if the image size exceeds 128 KB. 125*7e270ec3SChris Zankel 126