Home
last modified time | relevance | path

Searched +full:spi +full:- +full:max +full:- +full:frequency (Results 1 – 25 of 1022) sorted by relevance

12345678910>>...41

/openbmc/u-boot/arch/arm/dts/
H A Dast2600-bletchley.dts1 // SPDX-License-Identifier: GPL-2.0+
3 /dts-v1/;
5 #include "ast2600-u-boot.dtsi"
9 compatible = "facebook,bletchley-bmc", "aspeed,ast2600";
17 stdout-path = &uart5;
35 clock-frequency = <800000000>;
38 clock-frequency = <800000000>;
44 u-boot,dm-pre-reloc;
49 clock-frequency = <400000000>;
66 pinctrl-names = "default";
[all …]
H A Dast2600-slt.dts1 /dts-v1/;
3 #include "ast2600-u-boot.dtsi"
12 stdout-path = &uart5;
30 clock-frequency = <800000000>;
33 clock-frequency = <800000000>;
39 u-boot,dm-pre-reloc;
44 clock-frequency = <400000000>;
48 u-boot,dm-pre-reloc;
53 u-boot,dm-pre-reloc;
58 u-boot,dm-pre-reloc;
[all …]
H A Dast2600-pfr.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /dts-v1/;
4 #include "ast2600-u-boot.dtsi"
8 compatible = "aspeed,ast2600-evb", "aspeed,ast2600";
16 stdout-path = &uart5;
34 clock-frequency = <800000000>;
37 clock-frequency = <800000000>;
43 u-boot,dm-pre-reloc;
48 clock-frequency = <400000000>;
65 pinctrl-names = "default";
[all …]
H A Dast2600-intel.dts1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
4 #include "ast2600-u-boot.dtsi"
8 compatible = "aspeed,ast2600-intel", "aspeed,ast2600";
16 stdout-path = &uart5;
34 clock-frequency = <1200000000>;
37 clock-frequency = <1200000000>;
43 u-boot,dm-pre-reloc;
48 clock-frequency = <400000000>;
65 pinctrl-names = "default";
[all …]
H A Dast2600-evb.dts1 /dts-v1/;
3 #include "ast2600-u-boot.dtsi"
7 compatible = "aspeed,ast2600-evb", "aspeed,ast2600";
15 stdout-path = &uart5;
33 clock-frequency = <800000000>;
36 clock-frequency = <800000000>;
42 u-boot,dm-pre-reloc;
47 clock-frequency = <400000000>;
64 pinctrl-names = "default";
65 pinctrl-0 = < &pinctrl_mdio1_default &pinctrl_mdio2_default
[all …]
H A Dfsl-ls2080a-qds.dts1 // SPDX-License-Identifier: GPL-2.0+ OR X11
5 * Copyright 2013-2015 Freescale Semiconductor, Inc.
8 /dts-v1/;
10 #include "fsl-ls2080a.dtsi"
14 compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
23 bus-num = <0>;
27 #address-cells = <1>;
28 #size-cells = <1>;
29 compatible = "spi-flash";
30 spi-max-frequency = <3000000>;
[all …]
H A Dfsl-ls1046a-qds.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
10 /include/ "fsl-ls1046a.dtsi"
21 bus-num = <0>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "spi-flash";
28 spi-max-frequency = <1000000>; /* input clock */
29 spi-cpol;
30 spi-cpha;
[all …]
H A Dast2400-evb.dts1 /dts-v1/;
3 #include "ast2400-u-boot.dtsi"
7 compatible = "aspeed,ast2400-evb", "aspeed,ast2400";
15 stdout-path = &uart5;
27 u-boot,dm-pre-reloc;
32 clock-frequency = <200000000>;
36 u-boot,dm-pre-reloc;
41 u-boot,dm-pre-reloc;
47 phy-mode = "rgmii";
49 pinctrl-names = "default";
[all …]
H A Dtegra30-apalis.dts1 /dts-v1/;
10 stdout-path = &uarta;
21 spi0 = "/spi@7000d400";
22 spi1 = "/spi@7000dc00";
23 spi2 = "/spi@7000de00";
24 spi3 = "/spi@7000da00";
35 pcie-controller@00003000 {
37 avdd-pexa-supply = <&vdd2_reg>;
38 vdd-pexa-supply = <&vdd2_reg>;
39 avdd-pexb-supply = <&vdd2_reg>;
[all …]
H A Dtegra210-p2571.dts1 /dts-v1/;
10 stdout-path = &uarta;
22 spi0 = "/spi@7000d400";
23 spi1 = "/spi@7000da00";
24 spi2 = "/spi@70410000";
34 clock-frequency = <100000>;
39 clock-frequency = <100000>;
44 clock-frequency = <100000>;
49 clock-frequency = <100000>;
54 clock-frequency = <400000>;
[all …]
H A Dast2500-evb.dts1 /dts-v1/;
3 #include "ast2500-u-boot.dtsi"
7 compatible = "aspeed,ast2500-evb", "aspeed,ast2500";
15 stdout-path = &uart5;
27 u-boot,dm-pre-reloc;
32 clock-frequency = <400000000>;
36 u-boot,dm-pre-reloc;
41 u-boot,dm-pre-reloc;
46 u-boot,dm-pre-reloc;
52 phy-mode = "rgmii";
[all …]
H A Dfsl-ls1088a-qds.dts1 // SPDX-License-Identifier: GPL-2.0+ OR X11
8 /dts-v1/;
10 #include "fsl-ls1088a.dtsi"
14 compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
22 #address-cells = <2>;
23 #size-cells = <1>;
31 #address-cells = <1>;
32 #size-cells = <1>;
33 compatible = "cfi-flash";
35 bank-width = <2>;
[all …]
H A Dfsl-ls1012a-qds.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
6 /include/ "fsl-ls1012a.dtsi"
17 bus-num = <0>;
21 #address-cells = <1>;
22 #size-cells = <1>;
23 compatible = "spi-flash";
25 spi-max-frequency = <1000000>; /* input clock */
29 #address-cells = <1>;
30 #size-cells = <1>;
31 compatible = "spi-flash";
[all …]
H A Dfsl-ls2081a-rdb.dts1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * NXP LS2081A RDB board device tree source for QSPI-boot
10 /dts-v1/;
12 #include "fsl-ls2080a.dtsi"
16 compatible = "fsl,ls2081a-rdb", "fsl,ls2080a";
25 bus-num = <0>;
29 #address-cells = <1>;
30 #size-cells = <1>;
31 compatible = "spi-flash";
32 spi-max-frequency = <3000000>;
[all …]
/openbmc/u-boot/doc/device-tree-bindings/spi/
H A Dspi-stm32-qspi.txt2 --------------------------------------------
5 - compatible : should be "st,stm32-qspi".
6 - reg : 1. Physical base address and size of SPI registers map.
8 - spi-max-frequency : Max supported spi frequency.
9 - status : enable in requried dts.
12 --------------------------
13 - spi-max-frequency : Max supported spi frequency.
14 - spi-tx-bus-width : Bus width (number of lines) for writing (1-4)
15 - spi-rx-bus-width : Bus width (number of lines) for reading (1-4)
16 - memory-map : Address and size for memory-mapping the flash
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1028a.dtsi"
17 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
32 stdout-path = "serial0:115200n8";
40 sys_mclk: clock-mclk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <25000000>;
46 reg_1p8v: regulator-1p8v {
[all …]
H A Dfsl-ls1012a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "fsl-ls1012a.dtsi"
14 compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
21 sys_mclk: clock-mclk {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <24576000>;
27 reg_3p3v: regulator-3p3v {
28 compatible = "regulator-fixed";
[all …]
H A Dfsl-ls1088a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
21 bus-num = <0>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "jedec,spi-nor";
29 spi-max-frequency = <1000000>;
33 #address-cells = <1>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/resolver/
H A Dadi,ad2s90.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD2S90 Resolver-to-Digital Converter
10 - Matheus Tavares <matheus.bernardino@usp.br>
22 spi-max-frequency:
25 Chip's max frequency, as specified in its datasheet, is 2Mhz. But a 600ns
28 implemented in the spi code, to satisfy it, SCLK's period should be at
29 most 2 * 600ns, so the max frequency should be 1 / (2 * 6e-7), which gives
32 spi-cpol: true
[all …]
/openbmc/linux/arch/riscv/boot/dts/sifive/
H A Dhifive-unleashed-a00.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 #include "fu540-c000.dtsi"
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/pwm/pwm.h>
9 /* Clock frequency (in Hz) of the PCB crystal for rtcclk */
14 compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000",
18 stdout-path = "serial0";
22 timebase-frequency = <RTCCLK_FREQ>;
[all …]
/openbmc/u-boot/doc/device-tree-bindings/misc/
H A Dcros-ec.txt8 - compatible = "google,cros-ec"
11 - spi-max-frequency : Sets the maximum frequency (in Hz) for SPI bus
13 - i2c-max-frequency : Sets the maximum frequency (in Hz) for I2C bus
15 - ec-interrupt : Selects the EC interrupt, defined as a GPIO according
17 - optimise-flash-write : Boolean property - if present then flash blocks
22 to the EC (e.g. i2c, spi, lpc). The reg property (as usual) will indicate
29 spi@131b0000 {
30 cros-ec@0 {
32 compatible = "google,cros-ec";
33 spi-max-frequency = <5000000>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dmaxim,max11205.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ramona Bolboaca <ramona.bolboaca@analog.com>
13 The MAX11205 is an ultra-low-power (< 300FA max active current),
14 high-resolution, serial-output ADC.
19 - $ref: /schemas/spi/spi-peripheral-props.yaml#
24 - maxim,max11205a
25 - maxim,max11205b
33 spi-max-frequency:
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/gyroscope/
H A Dadi,adxrs290.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Analog Devices ADXRS290 Dual-Axis MEMS Gyroscope
11 - Nishant Malpani <nish.malpani25@gmail.com>
14 Bindings for the Analog Devices ADXRS290 dual-axis MEMS gyroscope device.
15 https://www.analog.com/media/en/technical-documentation/data-sheets/ADXRS290.pdf
24 spi-max-frequency:
27 spi-cpol: true
29 spi-cpha: true
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dvertexcom-mse102x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/vertexcom-mse102x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: The Vertexcom MSE102x (SPI)
10 - Stefan Wahren <stefan.wahren@chargebyte.com>
14 They can be connected either via RGMII, RMII or SPI to a host CPU.
16 In order to use a MSE102x chip as SPI device, it must be defined as
17 a child of an SPI master device in the device tree.
23 - $ref: ethernet-controller.yaml#
[all …]
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dnvidia,tegra114-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/nvidia,tegra114-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra114 SPI controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - const: nvidia,tegra114-spi
17 - items:
18 - enum:
[all …]

12345678910>>...41