Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12 |
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#
b025b4f5 |
| 02-Dec-2022 |
Geert Uytterhoeven <geert+renesas@glider.be> |
arm64: dts: freescale: Fix pca954x i2c-mux node names
"make dtbs_check":
arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dtb: pca9547@77: $nodename:0: 'pca9547@77' does not match '^(i2c-?)?mux'
arm64: dts: freescale: Fix pca954x i2c-mux node names
"make dtbs_check":
arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dtb: pca9547@77: $nodename:0: 'pca9547@77' does not match '^(i2c-?)?mux' From schema: Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.yaml arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dtb: pca9547@77: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'i2c@4' were unexpected) From schema: Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.yaml ...
Fix this by renaming PCA954x nodes to "i2c-mux", to match the I2C bus multiplexer/switch DT bindings and the Generic Names Recommendation in the Devicetree Specification.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Revision tags: v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18 |
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#
8c91374b |
| 21-May-2022 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: fsl: ls1012a: fix Micron SPI NOR compatible
The proper compatible for Micron n25q128a11 SPI NOR flash should include vendor-prefix.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlows
arm64: dts: fsl: ls1012a: fix Micron SPI NOR compatible
The proper compatible for Micron n25q128a11 SPI NOR flash should include vendor-prefix.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Revision tags: v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14 |
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#
9c2eb8b7 |
| 04-Jan-2021 |
Yangbo Lu <yangbo.lu@nxp.com> |
arm64: dts: freescale: use fixed index mmcN for NXP layerscape reference boards
The eSDHC driver has converted to use asynchronous probe. Let's use fixed index mmcN for eSDHC controllers, so that we
arm64: dts: freescale: use fixed index mmcN for NXP layerscape reference boards
The eSDHC driver has converted to use asynchronous probe. Let's use fixed index mmcN for eSDHC controllers, so that we can ignore the effect on usage, and avoid problem on previous use cases with fixed index mmcblkN.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Revision tags: v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29 |
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#
f5ac5ac1 |
| 30-Mar-2020 |
Kuldeep Singh <kuldeep.singh@nxp.com> |
arm64: dts: ls1012a: Add QSPI node properties
Add support for QSPI on NXP layerscape LS1012A-RDB, LS1012A-QDS, LS1012A-FRDM and LS1012A-FRWY boards.
LS1012A-RDB has 2 Spansion "s25fs512s" flashes o
arm64: dts: ls1012a: Add QSPI node properties
Add support for QSPI on NXP layerscape LS1012A-RDB, LS1012A-QDS, LS1012A-FRDM and LS1012A-FRWY boards.
LS1012A-RDB has 2 Spansion "s25fs512s" flashes of size 64M each and only one can be accessed at a time. LS1012A-QDS/FRDM has 1 spansion "s25fs512s" flash of size 64M. LS1012A-FRWY has one winbond "w25q16dw" flash of size 2M.
Use generic compatibles as "jedec,spi-nor" for automatic detection of flash. Configure RX and TX buswidth values as 2 as only two I/O lines are available for data transfer.
Add ls1012a(si) node alongwith flash nodes.
Signed-off-by: Ashish Kumar <Ashish.kumar@nxp.com> Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Revision tags: v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3, v5.3.2, v5.3.1, v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12, v5.2.11, v5.2.10, v5.2.9, v5.2.8, v5.2.7, v5.2.6, v5.2.5, v5.2.4, v5.2.3, v5.2.2, v5.2.1, v5.2, v5.1.16, v5.1.15, v5.1.14, v5.1.13, v5.1.12, v5.1.11, v5.1.10, v5.1.9, v5.1.8, v5.1.7, v5.1.6, v5.1.5, v5.1.4, v5.1.3, v5.1.2, v5.1.1, v5.0.14, v5.1, v5.0.13, v5.0.12, v5.0.11, v5.0.10, v5.0.9, v5.0.8, v5.0.7, v5.0.6, v5.0.5, v5.0.4, v5.0.3, v4.19.29, v5.0.2, v4.19.28, v5.0.1, v4.19.27, v5.0, v4.19.26, v4.19.25, v4.19.24, v4.19.23, v4.19.22, v4.19.21, v4.19.20, v4.19.19, v4.19.18, v4.19.17, v4.19.16, v4.19.15, v4.19.14, v4.19.13, v4.19.12, v4.19.11, v4.19.10, v4.19.9, v4.19.8, v4.19.7, v4.19.6, v4.19.5, v4.19.4, v4.18.20, v4.19.3, v4.18.19, v4.19.2, v4.18.18, v4.18.17, v4.19.1, v4.19, v4.18.16, v4.18.15, v4.18.14, v4.18.13, v4.18.12, v4.18.11, v4.18.10, v4.18.9, v4.18.7, v4.18.6, v4.18.5, v4.17.18, v4.18.4, v4.18.3, v4.17.17, v4.18.2, v4.17.16, v4.17.15, v4.18.1, v4.18, v4.17.14, v4.17.13, v4.17.12, v4.17.11, v4.17.10, v4.17.9, v4.17.8, v4.17.7, v4.17.6, v4.17.5, v4.17.4, v4.17.3, v4.17.2 |
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#
7a2aeb91 |
| 12-Jun-2018 |
Li Yang <leoyang.li@nxp.com> |
arm64: dts: freescale: Update to use SPDX identifiers
Replace license text with corresponding SPDX identifiers and update the format of existing SPDX identifiers to follow the new guideline Document
arm64: dts: freescale: Update to use SPDX identifiers
Replace license text with corresponding SPDX identifiers and update the format of existing SPDX identifiers to follow the new guideline Documentation/process/license-rules.rst.
Note that some of the files mentioned X11 license previously but the license text actually matches MIT license.
Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Revision tags: v4.17.1, v4.17, v4.16, v4.15, v4.13.16, v4.14, v4.13.5, v4.13 |
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#
519de51c |
| 30-Aug-2017 |
Yuan Yao <yao.yuan@nxp.com> |
arm64: dts: ls1012a: add the DTS node for DSPI support
Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Revision tags: v4.12, v4.10.17, v4.10.16 |
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#
0f098701 |
| 08-May-2017 |
Yangbo Lu <yangbo.lu@nxp.com> |
arm64: dts: ls1012a: add eSDHC nodes
There are two eSDHC controllers in LS1012A. This patch is to add eSDHC nodes for ls1012a dts. Also enable eSDHC for RDB/QDS boards.
Signed-off-by: Yangbo Lu <ya
arm64: dts: ls1012a: add eSDHC nodes
There are two eSDHC controllers in LS1012A. This patch is to add eSDHC nodes for ls1012a dts. Also enable eSDHC for RDB/QDS boards.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Revision tags: v4.10.15, v4.10.14 |
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#
8637f58b |
| 27-Apr-2017 |
Li Yang <leoyang.li@nxp.com> |
arm64: dts: freescale: update the copyright claims
Update the copyright claims to comply with company policy.
Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.o
arm64: dts: freescale: update the copyright claims
Update the copyright claims to comply with company policy.
Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Revision tags: v4.10.13, v4.10.12, v4.10.11, v4.10.10, v4.10.9, v4.10.8, v4.10.7, v4.10.6, v4.10.5, v4.10.4, v4.10.3 |
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#
427700a7 |
| 13-Mar-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm64: dts: updated sata node on ls1012a platform
Updated sata node to add ecc register address and dma coherence property. Enable sata on ls1012a platforms as well.
Signed-off-by: Tang Yuantian <a
arm64: dts: updated sata node on ls1012a platform
Updated sata node to add ecc register address and dma coherence property. Enable sata on ls1012a platforms as well.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Revision tags: v4.10.2, v4.10.1, v4.10 |
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#
ba321360 |
| 03-Jan-2017 |
Harninder Rai <harninder.rai@nxp.com> |
arm64: dts: Add support for FSL's LS1012A SoC
LS1012A features an advanced 64-bit ARM v8 CortexA53 processor with 32 KB of parity protected L1-I cache, 32 KB of ECC protected L1-D cache, as well as
arm64: dts: Add support for FSL's LS1012A SoC
LS1012A features an advanced 64-bit ARM v8 CortexA53 processor with 32 KB of parity protected L1-I cache, 32 KB of ECC protected L1-D cache, as well as 256 KB of ECC protected L2 cache.
Features summary One 64-bit ARM-v8 Cortex-A53 core with the following capabilities - Arranged as a cluster of one core supporting a 256 KB L2 cache with ECC protection - Speed up to 800 MHz - Parity-protected 32 KB L1 instruction cache and 32 KB L1 data cache - Neon SIMD engine - ARM v8 cryptography extensions One 16-bit DDR3L SDRAM memory controller ARM core-link CCI-400 cache coherent interconnect Cryptography acceleration (SEC) One Configurable x3 SerDes One PCI Express Gen2 controller, supporting x1 operation One serial ATA (SATA Gen 3.0) controller One USB 3.0/2.0 controller with integrated PHY
Following levels of DTSI/DTS files have been created for the LS1012A SoC family:
- fsl-ls1012a.dtsi: DTS-Include file for FSL LS1012A SoC.
- fsl-ls1012a-frdm.dts: DTS file for FSL LS1012A FRDM board.
- fsl-ls1012a-qds.dts: DTS file for FSL LS1012A QDS board.
- fsl-ls1012a-rdb.dts: DTS file for FSL LS1012A RDB board.
Signed-off-by: Harninder Rai <harninder.rai@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Revision tags: v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29 |
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#
f5ac5ac1 |
| 30-Mar-2020 |
Kuldeep Singh <kuldeep.singh@nxp.com> |
arm64: dts: ls1012a: Add QSPI node properties Add support for QSPI on NXP layerscape LS1012A-RDB, LS1012A-QDS, LS1012A-FRDM and LS1012A-FRWY boards. LS1012A-RDB has 2 Spansion "
arm64: dts: ls1012a: Add QSPI node properties Add support for QSPI on NXP layerscape LS1012A-RDB, LS1012A-QDS, LS1012A-FRDM and LS1012A-FRWY boards. LS1012A-RDB has 2 Spansion "s25fs512s" flashes of size 64M each and only one can be accessed at a time. LS1012A-QDS/FRDM has 1 spansion "s25fs512s" flash of size 64M. LS1012A-FRWY has one winbond "w25q16dw" flash of size 2M. Use generic compatibles as "jedec,spi-nor" for automatic detection of flash. Configure RX and TX buswidth values as 2 as only two I/O lines are available for data transfer. Add ls1012a(si) node alongwith flash nodes. Signed-off-by: Ashish Kumar <Ashish.kumar@nxp.com> Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Revision tags: v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3, v5.3.2, v5.3.1, v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12, v5.2.11, v5.2.10, v5.2.9, v5.2.8, v5.2.7, v5.2.6, v5.2.5, v5.2.4, v5.2.3, v5.2.2, v5.2.1, v5.2, v5.1.16, v5.1.15, v5.1.14, v5.1.13, v5.1.12, v5.1.11, v5.1.10, v5.1.9, v5.1.8, v5.1.7, v5.1.6, v5.1.5, v5.1.4, v5.1.3, v5.1.2, v5.1.1, v5.0.14, v5.1, v5.0.13, v5.0.12, v5.0.11, v5.0.10, v5.0.9, v5.0.8, v5.0.7, v5.0.6, v5.0.5, v5.0.4, v5.0.3, v4.19.29, v5.0.2, v4.19.28, v5.0.1, v4.19.27, v5.0, v4.19.26, v4.19.25, v4.19.24, v4.19.23, v4.19.22, v4.19.21, v4.19.20, v4.19.19, v4.19.18, v4.19.17, v4.19.16, v4.19.15, v4.19.14, v4.19.13, v4.19.12, v4.19.11, v4.19.10, v4.19.9, v4.19.8, v4.19.7, v4.19.6, v4.19.5, v4.19.4, v4.18.20, v4.19.3, v4.18.19, v4.19.2, v4.18.18, v4.18.17, v4.19.1, v4.19, v4.18.16, v4.18.15, v4.18.14, v4.18.13, v4.18.12, v4.18.11, v4.18.10, v4.18.9, v4.18.7, v4.18.6, v4.18.5, v4.17.18, v4.18.4, v4.18.3, v4.17.17, v4.18.2, v4.17.16, v4.17.15, v4.18.1, v4.18, v4.17.14, v4.17.13, v4.17.12, v4.17.11, v4.17.10, v4.17.9, v4.17.8, v4.17.7, v4.17.6, v4.17.5, v4.17.4, v4.17.3, v4.17.2 |
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7a2aeb91 |
| 12-Jun-2018 |
Li Yang <leoyang.li@nxp.com> |
arm64: dts: freescale: Update to use SPDX identifiers Replace license text with corresponding SPDX identifiers and update the format of existing SPDX identifiers to follow the new guidel
arm64: dts: freescale: Update to use SPDX identifiers Replace license text with corresponding SPDX identifiers and update the format of existing SPDX identifiers to follow the new guideline Documentation/process/license-rules.rst. Note that some of the files mentioned X11 license previously but the license text actually matches MIT license. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Revision tags: v4.17.1, v4.17, v4.16, v4.15, v4.13.16, v4.14, v4.13.5, v4.13 |
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519de51c |
| 30-Aug-2017 |
Yuan Yao <yao.yuan@nxp.com> |
arm64: dts: ls1012a: add the DTS node for DSPI support Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Shawn Guo <shawngu
arm64: dts: ls1012a: add the DTS node for DSPI support Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Revision tags: v4.12, v4.10.17, v4.10.16 |
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#
0f098701 |
| 08-May-2017 |
Yangbo Lu <yangbo.lu@nxp.com> |
arm64: dts: ls1012a: add eSDHC nodes There are two eSDHC controllers in LS1012A. This patch is to add eSDHC nodes for ls1012a dts. Also enable eSDHC for RDB/QDS boards. Signed-o
arm64: dts: ls1012a: add eSDHC nodes There are two eSDHC controllers in LS1012A. This patch is to add eSDHC nodes for ls1012a dts. Also enable eSDHC for RDB/QDS boards. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Revision tags: v4.10.15, v4.10.14 |
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#
8637f58b |
| 27-Apr-2017 |
Li Yang <leoyang.li@nxp.com> |
arm64: dts: freescale: update the copyright claims Update the copyright claims to comply with company policy. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Gu
arm64: dts: freescale: update the copyright claims Update the copyright claims to comply with company policy. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Revision tags: v4.10.13, v4.10.12, v4.10.11, v4.10.10, v4.10.9, v4.10.8, v4.10.7, v4.10.6, v4.10.5, v4.10.4, v4.10.3 |
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#
427700a7 |
| 13-Mar-2017 |
Yuantian Tang <andy.tang@nxp.com> |
arm64: dts: updated sata node on ls1012a platform Updated sata node to add ecc register address and dma coherence property. Enable sata on ls1012a platforms as well. Signed-
arm64: dts: updated sata node on ls1012a platform Updated sata node to add ecc register address and dma coherence property. Enable sata on ls1012a platforms as well. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Revision tags: v4.10.2, v4.10.1, v4.10 |
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#
ba321360 |
| 03-Jan-2017 |
Harninder Rai <harninder.rai@nxp.com> |
arm64: dts: Add support for FSL's LS1012A SoC LS1012A features an advanced 64-bit ARM v8 CortexA53 processor with 32 KB of parity protected L1-I cache, 32 KB of ECC protected L1-D ca
arm64: dts: Add support for FSL's LS1012A SoC LS1012A features an advanced 64-bit ARM v8 CortexA53 processor with 32 KB of parity protected L1-I cache, 32 KB of ECC protected L1-D cache, as well as 256 KB of ECC protected L2 cache. Features summary One 64-bit ARM-v8 Cortex-A53 core with the following capabilities - Arranged as a cluster of one core supporting a 256 KB L2 cache with ECC protection - Speed up to 800 MHz - Parity-protected 32 KB L1 instruction cache and 32 KB L1 data cache - Neon SIMD engine - ARM v8 cryptography extensions One 16-bit DDR3L SDRAM memory controller ARM core-link CCI-400 cache coherent interconnect Cryptography acceleration (SEC) One Configurable x3 SerDes One PCI Express Gen2 controller, supporting x1 operation One serial ATA (SATA Gen 3.0) controller One USB 3.0/2.0 controller with integrated PHY Following levels of DTSI/DTS files have been created for the LS1012A SoC family: - fsl-ls1012a.dtsi: DTS-Include file for FSL LS1012A SoC. - fsl-ls1012a-frdm.dts: DTS file for FSL LS1012A FRDM board. - fsl-ls1012a-qds.dts: DTS file for FSL LS1012A QDS board. - fsl-ls1012a-rdb.dts: DTS file for FSL LS1012A RDB board. Signed-off-by: Harninder Rai <harninder.rai@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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