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Searched full:speedbin (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/cpufreq/
H A Dqcom-cpufreq-nvmem.c11 * and speedbin blown in the efuse combination.
140 u8 *speedbin; in qcom_cpufreq_kryo_name_version() local
148 speedbin = nvmem_cell_read(speedbin_nvmem, &len); in qcom_cpufreq_kryo_name_version()
149 if (IS_ERR(speedbin)) in qcom_cpufreq_kryo_name_version()
150 return PTR_ERR(speedbin); in qcom_cpufreq_kryo_name_version()
155 drv->versions = 1 << (unsigned int)(*speedbin); in qcom_cpufreq_kryo_name_version()
159 drv->versions = 1 << ((unsigned int)(*speedbin) + 4); in qcom_cpufreq_kryo_name_version()
166 kfree(speedbin); in qcom_cpufreq_kryo_name_version()
176 u8 *speedbin; in qcom_cpufreq_krait_name_version() local
180 speedbin = nvmem_cell_read(speedbin_nvmem, &len); in qcom_cpufreq_krait_name_version()
[all …]
H A Dsun50i-cpufreq-nvmem.c39 u32 *speedbin, efuse_value; in sun50i_cpufreq_get_efuse() local
64 speedbin = nvmem_cell_read(speedbin_nvmem, &len); in sun50i_cpufreq_get_efuse()
66 if (IS_ERR(speedbin)) in sun50i_cpufreq_get_efuse()
67 return PTR_ERR(speedbin); in sun50i_cpufreq_get_efuse()
69 efuse_value = (*speedbin >> NVMEM_SHIFT) & NVMEM_MASK; in sun50i_cpufreq_get_efuse()
81 kfree(speedbin); in sun50i_cpufreq_get_efuse()
/openbmc/linux/Documentation/devicetree/bindings/opp/
H A Dopp-v2-kryo-cpu.yaml20 defines the voltage and frequency value based on the speedbin blown in
35 speedbin that is used to select the right frequency/voltage
54 0: MSM8996, speedbin 0
55 1: MSM8996, speedbin 1
56 2: MSM8996, speedbin 2
57 3: MSM8996, speedbin 3
60 Bitmap for MSM8996SG format (speedbin shifted of 4 left):
62 4: MSM8996SG, speedbin 0
63 5: MSM8996SG, speedbin 1
64 6: MSM8996SG, speedbin 2
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H A Dallwinner,sun50i-h6-operating-points.yaml17 on the speedbin blown in the efuse combination. The
31 registers that has information about the speedbin that is used
/openbmc/linux/drivers/nvmem/
H A Dmtk-efuse.c55 * On some SoCs, the GPU speedbin is not read as bitmask but as in mtk_efuse_fixup_cell_info()
60 strncmp(cell->name, "gpu-speedbin", min(sz, strlen("gpu-speedbin"))) == 0) in mtk_efuse_fixup_cell_info()
/openbmc/linux/drivers/gpu/drm/msm/adreno/
H A Dadreno_gpu.h82 uint16_t speedbin; member
104 * @speedbins: Optional table of fuse to speedbin mappings
115 * Helper to build a speedbin table, ie. the table:
116 * fuse | speedbin
136 uint16_t speedbin; member
460 int adreno_read_speedbin(struct device *dev, u32 *speedbin);
H A Dadreno_gpu.c331 *value |= ((uint64_t) adreno_gpu->speedbin) << 32; in adreno_get_param()
1052 int adreno_read_speedbin(struct device *dev, u32 *speedbin) in adreno_read_speedbin() argument
1054 return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); in adreno_read_speedbin()
1066 u32 speedbin; in adreno_gpu_init() local
1094 if (adreno_read_speedbin(dev, &speedbin) || !speedbin) in adreno_gpu_init()
1095 speedbin = 0xffff; in adreno_gpu_init()
1096 adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); in adreno_gpu_init()
H A Da6xx_gpu.c2210 return BIT(info->speedbins[i].speedbin); in fuse_to_supp_hw()
2218 u32 speedbin; in a6xx_set_supported_hw() local
2221 ret = adreno_read_speedbin(dev, &speedbin); in a6xx_set_supported_hw()
2223 * -ENOENT means that the platform doesn't support speedbin which is in a6xx_set_supported_hw()
2234 supp_hw = fuse_to_supp_hw(info, speedbin); in a6xx_set_supported_hw()
2239 speedbin); in a6xx_set_supported_hw()
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-ipq8064.dtsi380 speedbin_efuse: speedbin@c0 {
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dqcs404.dtsi376 cpr_efuse_speedbin: speedbin@13c {
H A Dmsm8996.dtsi768 speedbin_efuse: speedbin@133 {
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8186.dtsi1679 gpu_speedbin: gpu-speedbin@59c {