17d127095SSricharan R // SPDX-License-Identifier: GPL-2.0
27d127095SSricharan R /*
37d127095SSricharan R * Copyright (c) 2018, The Linux Foundation. All rights reserved.
47d127095SSricharan R */
57d127095SSricharan R
67d127095SSricharan R /*
77d127095SSricharan R * In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors,
87d127095SSricharan R * the CPU frequency subset and voltage value of each OPP varies
97d127095SSricharan R * based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
107d127095SSricharan R * defines the voltage and frequency value based on the msm-id in SMEM
117d127095SSricharan R * and speedbin blown in the efuse combination.
127d127095SSricharan R * The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
137d127095SSricharan R * to provide the OPP framework with required information.
147d127095SSricharan R * This is used to determine the voltage and frequency value for each OPP of
157d127095SSricharan R * operating-points-v2 table when it is parsed by the OPP framework.
167d127095SSricharan R */
177d127095SSricharan R
187d127095SSricharan R #include <linux/cpu.h>
197d127095SSricharan R #include <linux/err.h>
207d127095SSricharan R #include <linux/init.h>
217d127095SSricharan R #include <linux/kernel.h>
227d127095SSricharan R #include <linux/module.h>
237d127095SSricharan R #include <linux/nvmem-consumer.h>
247d127095SSricharan R #include <linux/of.h>
257d127095SSricharan R #include <linux/platform_device.h>
261cb8339cSNiklas Cassel #include <linux/pm_domain.h>
277d127095SSricharan R #include <linux/pm_opp.h>
287d127095SSricharan R #include <linux/slab.h>
297d127095SSricharan R #include <linux/soc/qcom/smem.h>
307d127095SSricharan R
31865d7e71SRobert Marko #include <dt-bindings/arm/qcom,ids.h>
327d127095SSricharan R
3357f2f8b4SNiklas Cassel struct qcom_cpufreq_drv;
3457f2f8b4SNiklas Cassel
3557f2f8b4SNiklas Cassel struct qcom_cpufreq_match_data {
3657f2f8b4SNiklas Cassel int (*get_version)(struct device *cpu_dev,
3757f2f8b4SNiklas Cassel struct nvmem_cell *speedbin_nvmem,
38a8811ec7SAnsuel Smith char **pvs_name,
3957f2f8b4SNiklas Cassel struct qcom_cpufreq_drv *drv);
401cb8339cSNiklas Cassel const char **genpd_names;
4157f2f8b4SNiklas Cassel };
4257f2f8b4SNiklas Cassel
4357f2f8b4SNiklas Cassel struct qcom_cpufreq_drv {
4449cd000dSViresh Kumar int *opp_tokens;
4557f2f8b4SNiklas Cassel u32 versions;
4657f2f8b4SNiklas Cassel const struct qcom_cpufreq_match_data *data;
4757f2f8b4SNiklas Cassel };
4857f2f8b4SNiklas Cassel
497d127095SSricharan R static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
507d127095SSricharan R
get_krait_bin_format_a(struct device * cpu_dev,int * speed,int * pvs,int * pvs_ver,u8 * buf)51a8811ec7SAnsuel Smith static void get_krait_bin_format_a(struct device *cpu_dev,
52a8811ec7SAnsuel Smith int *speed, int *pvs, int *pvs_ver,
53a05887f0SFabien Parent u8 *buf)
54a8811ec7SAnsuel Smith {
55a8811ec7SAnsuel Smith u32 pte_efuse;
56a8811ec7SAnsuel Smith
57a8811ec7SAnsuel Smith pte_efuse = *((u32 *)buf);
58a8811ec7SAnsuel Smith
59a8811ec7SAnsuel Smith *speed = pte_efuse & 0xf;
60a8811ec7SAnsuel Smith if (*speed == 0xf)
61a8811ec7SAnsuel Smith *speed = (pte_efuse >> 4) & 0xf;
62a8811ec7SAnsuel Smith
63a8811ec7SAnsuel Smith if (*speed == 0xf) {
64a8811ec7SAnsuel Smith *speed = 0;
65a8811ec7SAnsuel Smith dev_warn(cpu_dev, "Speed bin: Defaulting to %d\n", *speed);
66a8811ec7SAnsuel Smith } else {
67a8811ec7SAnsuel Smith dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
68a8811ec7SAnsuel Smith }
69a8811ec7SAnsuel Smith
70a8811ec7SAnsuel Smith *pvs = (pte_efuse >> 10) & 0x7;
71a8811ec7SAnsuel Smith if (*pvs == 0x7)
72a8811ec7SAnsuel Smith *pvs = (pte_efuse >> 13) & 0x7;
73a8811ec7SAnsuel Smith
74a8811ec7SAnsuel Smith if (*pvs == 0x7) {
75a8811ec7SAnsuel Smith *pvs = 0;
76a8811ec7SAnsuel Smith dev_warn(cpu_dev, "PVS bin: Defaulting to %d\n", *pvs);
77a8811ec7SAnsuel Smith } else {
78a8811ec7SAnsuel Smith dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
79a8811ec7SAnsuel Smith }
80a8811ec7SAnsuel Smith }
81a8811ec7SAnsuel Smith
get_krait_bin_format_b(struct device * cpu_dev,int * speed,int * pvs,int * pvs_ver,u8 * buf)82a8811ec7SAnsuel Smith static void get_krait_bin_format_b(struct device *cpu_dev,
83a8811ec7SAnsuel Smith int *speed, int *pvs, int *pvs_ver,
84a05887f0SFabien Parent u8 *buf)
85a8811ec7SAnsuel Smith {
86a8811ec7SAnsuel Smith u32 pte_efuse, redundant_sel;
87a8811ec7SAnsuel Smith
88a8811ec7SAnsuel Smith pte_efuse = *((u32 *)buf);
89a8811ec7SAnsuel Smith redundant_sel = (pte_efuse >> 24) & 0x7;
90a8811ec7SAnsuel Smith
91a8811ec7SAnsuel Smith *pvs_ver = (pte_efuse >> 4) & 0x3;
92a8811ec7SAnsuel Smith
93a8811ec7SAnsuel Smith switch (redundant_sel) {
94a8811ec7SAnsuel Smith case 1:
95a8811ec7SAnsuel Smith *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
96a8811ec7SAnsuel Smith *speed = (pte_efuse >> 27) & 0xf;
97a8811ec7SAnsuel Smith break;
98a8811ec7SAnsuel Smith case 2:
99a8811ec7SAnsuel Smith *pvs = (pte_efuse >> 27) & 0xf;
100a8811ec7SAnsuel Smith *speed = pte_efuse & 0x7;
101a8811ec7SAnsuel Smith break;
102a8811ec7SAnsuel Smith default:
103a8811ec7SAnsuel Smith /* 4 bits of PVS are in efuse register bits 31, 8-6. */
104a8811ec7SAnsuel Smith *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
105a8811ec7SAnsuel Smith *speed = pte_efuse & 0x7;
106a8811ec7SAnsuel Smith }
107a8811ec7SAnsuel Smith
108a8811ec7SAnsuel Smith /* Check SPEED_BIN_BLOW_STATUS */
109a8811ec7SAnsuel Smith if (pte_efuse & BIT(3)) {
110a8811ec7SAnsuel Smith dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
111a8811ec7SAnsuel Smith } else {
112a8811ec7SAnsuel Smith dev_warn(cpu_dev, "Speed bin not set. Defaulting to 0!\n");
113a8811ec7SAnsuel Smith *speed = 0;
114a8811ec7SAnsuel Smith }
115a8811ec7SAnsuel Smith
116a8811ec7SAnsuel Smith /* Check PVS_BLOW_STATUS */
1174a8a77abSLuca Weiss pte_efuse = *(((u32 *)buf) + 1);
118a8811ec7SAnsuel Smith pte_efuse &= BIT(21);
119a8811ec7SAnsuel Smith if (pte_efuse) {
120a8811ec7SAnsuel Smith dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
121a8811ec7SAnsuel Smith } else {
122a8811ec7SAnsuel Smith dev_warn(cpu_dev, "PVS bin not set. Defaulting to 0!\n");
123a8811ec7SAnsuel Smith *pvs = 0;
124a8811ec7SAnsuel Smith }
125a8811ec7SAnsuel Smith
126a8811ec7SAnsuel Smith dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver);
127a8811ec7SAnsuel Smith }
128a8811ec7SAnsuel Smith
qcom_cpufreq_kryo_name_version(struct device * cpu_dev,struct nvmem_cell * speedbin_nvmem,char ** pvs_name,struct qcom_cpufreq_drv * drv)1297d127095SSricharan R static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
1307d127095SSricharan R struct nvmem_cell *speedbin_nvmem,
131a8811ec7SAnsuel Smith char **pvs_name,
13257f2f8b4SNiklas Cassel struct qcom_cpufreq_drv *drv)
1337d127095SSricharan R {
1347d127095SSricharan R size_t len;
1357d0f03d1SRobert Marko u32 msm_id;
1367d127095SSricharan R u8 *speedbin;
1377d0f03d1SRobert Marko int ret;
138a8811ec7SAnsuel Smith *pvs_name = NULL;
1397d127095SSricharan R
1407d0f03d1SRobert Marko ret = qcom_smem_get_soc_id(&msm_id);
1417d0f03d1SRobert Marko if (ret)
1427d0f03d1SRobert Marko return ret;
1437d127095SSricharan R
1447d127095SSricharan R speedbin = nvmem_cell_read(speedbin_nvmem, &len);
1457d127095SSricharan R if (IS_ERR(speedbin))
1467d127095SSricharan R return PTR_ERR(speedbin);
1477d127095SSricharan R
1487d0f03d1SRobert Marko switch (msm_id) {
1497d0f03d1SRobert Marko case QCOM_ID_MSM8996:
1507d0f03d1SRobert Marko case QCOM_ID_APQ8096:
15157f2f8b4SNiklas Cassel drv->versions = 1 << (unsigned int)(*speedbin);
1527d127095SSricharan R break;
1537d0f03d1SRobert Marko case QCOM_ID_MSM8996SG:
1547d0f03d1SRobert Marko case QCOM_ID_APQ8096SG:
15557f2f8b4SNiklas Cassel drv->versions = 1 << ((unsigned int)(*speedbin) + 4);
1567d127095SSricharan R break;
1577d127095SSricharan R default:
1587d127095SSricharan R BUG();
1597d127095SSricharan R break;
1607d127095SSricharan R }
1617d127095SSricharan R
1627d127095SSricharan R kfree(speedbin);
1637d127095SSricharan R return 0;
1647d127095SSricharan R }
1657d127095SSricharan R
qcom_cpufreq_krait_name_version(struct device * cpu_dev,struct nvmem_cell * speedbin_nvmem,char ** pvs_name,struct qcom_cpufreq_drv * drv)166a8811ec7SAnsuel Smith static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
167a8811ec7SAnsuel Smith struct nvmem_cell *speedbin_nvmem,
168a8811ec7SAnsuel Smith char **pvs_name,
169a8811ec7SAnsuel Smith struct qcom_cpufreq_drv *drv)
170a8811ec7SAnsuel Smith {
171a8811ec7SAnsuel Smith int speed = 0, pvs = 0, pvs_ver = 0;
172a8811ec7SAnsuel Smith u8 *speedbin;
173a8811ec7SAnsuel Smith size_t len;
1749f42cf54SFabien Parent int ret = 0;
175a8811ec7SAnsuel Smith
176a8811ec7SAnsuel Smith speedbin = nvmem_cell_read(speedbin_nvmem, &len);
177a8811ec7SAnsuel Smith
178a8811ec7SAnsuel Smith if (IS_ERR(speedbin))
179a8811ec7SAnsuel Smith return PTR_ERR(speedbin);
180a8811ec7SAnsuel Smith
181a8811ec7SAnsuel Smith switch (len) {
182a8811ec7SAnsuel Smith case 4:
183a8811ec7SAnsuel Smith get_krait_bin_format_a(cpu_dev, &speed, &pvs, &pvs_ver,
184a05887f0SFabien Parent speedbin);
185a8811ec7SAnsuel Smith break;
186a8811ec7SAnsuel Smith case 8:
187a8811ec7SAnsuel Smith get_krait_bin_format_b(cpu_dev, &speed, &pvs, &pvs_ver,
188a05887f0SFabien Parent speedbin);
189a8811ec7SAnsuel Smith break;
190a8811ec7SAnsuel Smith default:
191a8811ec7SAnsuel Smith dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
1929f42cf54SFabien Parent ret = -ENODEV;
1939f42cf54SFabien Parent goto len_error;
194a8811ec7SAnsuel Smith }
195a8811ec7SAnsuel Smith
196a8811ec7SAnsuel Smith snprintf(*pvs_name, sizeof("speedXX-pvsXX-vXX"), "speed%d-pvs%d-v%d",
197a8811ec7SAnsuel Smith speed, pvs, pvs_ver);
198a8811ec7SAnsuel Smith
199a8811ec7SAnsuel Smith drv->versions = (1 << speed);
200a8811ec7SAnsuel Smith
2019f42cf54SFabien Parent len_error:
202a8811ec7SAnsuel Smith kfree(speedbin);
2039f42cf54SFabien Parent return ret;
204a8811ec7SAnsuel Smith }
205a8811ec7SAnsuel Smith
20657f2f8b4SNiklas Cassel static const struct qcom_cpufreq_match_data match_data_kryo = {
20757f2f8b4SNiklas Cassel .get_version = qcom_cpufreq_kryo_name_version,
20857f2f8b4SNiklas Cassel };
20957f2f8b4SNiklas Cassel
210a8811ec7SAnsuel Smith static const struct qcom_cpufreq_match_data match_data_krait = {
211a8811ec7SAnsuel Smith .get_version = qcom_cpufreq_krait_name_version,
212a8811ec7SAnsuel Smith };
213a8811ec7SAnsuel Smith
2141cb8339cSNiklas Cassel static const char *qcs404_genpd_names[] = { "cpr", NULL };
2151cb8339cSNiklas Cassel
2161cb8339cSNiklas Cassel static const struct qcom_cpufreq_match_data match_data_qcs404 = {
2171cb8339cSNiklas Cassel .genpd_names = qcs404_genpd_names,
2181cb8339cSNiklas Cassel };
2191cb8339cSNiklas Cassel
qcom_cpufreq_probe(struct platform_device * pdev)2207d127095SSricharan R static int qcom_cpufreq_probe(struct platform_device *pdev)
2217d127095SSricharan R {
22257f2f8b4SNiklas Cassel struct qcom_cpufreq_drv *drv;
2237d127095SSricharan R struct nvmem_cell *speedbin_nvmem;
2247d127095SSricharan R struct device_node *np;
2257d127095SSricharan R struct device *cpu_dev;
22601039fb8SFabien Parent char pvs_name_buffer[] = "speedXX-pvsXX-vXX";
22701039fb8SFabien Parent char *pvs_name = pvs_name_buffer;
2287d127095SSricharan R unsigned cpu;
2297d127095SSricharan R const struct of_device_id *match;
2307d127095SSricharan R int ret;
2317d127095SSricharan R
2327d127095SSricharan R cpu_dev = get_cpu_device(0);
2337d127095SSricharan R if (!cpu_dev)
2347d127095SSricharan R return -ENODEV;
2357d127095SSricharan R
2367d127095SSricharan R np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
2377d127095SSricharan R if (!np)
2387d127095SSricharan R return -ENOENT;
2397d127095SSricharan R
2402dea6516SAnsuel Smith ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu");
2417d127095SSricharan R if (!ret) {
2427d127095SSricharan R of_node_put(np);
2437d127095SSricharan R return -ENOENT;
2447d127095SSricharan R }
2457d127095SSricharan R
24657f2f8b4SNiklas Cassel drv = kzalloc(sizeof(*drv), GFP_KERNEL);
24757f2f8b4SNiklas Cassel if (!drv)
24857f2f8b4SNiklas Cassel return -ENOMEM;
24957f2f8b4SNiklas Cassel
25057f2f8b4SNiklas Cassel match = pdev->dev.platform_data;
25157f2f8b4SNiklas Cassel drv->data = match->data;
25257f2f8b4SNiklas Cassel if (!drv->data) {
25357f2f8b4SNiklas Cassel ret = -ENODEV;
25457f2f8b4SNiklas Cassel goto free_drv;
2557d127095SSricharan R }
2567d127095SSricharan R
25757f2f8b4SNiklas Cassel if (drv->data->get_version) {
25857f2f8b4SNiklas Cassel speedbin_nvmem = of_nvmem_cell_get(np, NULL);
25957f2f8b4SNiklas Cassel if (IS_ERR(speedbin_nvmem)) {
260d78be404SYang Yingliang ret = dev_err_probe(cpu_dev, PTR_ERR(speedbin_nvmem),
261d78be404SYang Yingliang "Could not get nvmem cell\n");
26257f2f8b4SNiklas Cassel goto free_drv;
26357f2f8b4SNiklas Cassel }
2647d127095SSricharan R
265a8811ec7SAnsuel Smith ret = drv->data->get_version(cpu_dev,
266a8811ec7SAnsuel Smith speedbin_nvmem, &pvs_name, drv);
26757f2f8b4SNiklas Cassel if (ret) {
26857f2f8b4SNiklas Cassel nvmem_cell_put(speedbin_nvmem);
26957f2f8b4SNiklas Cassel goto free_drv;
27057f2f8b4SNiklas Cassel }
27157f2f8b4SNiklas Cassel nvmem_cell_put(speedbin_nvmem);
27257f2f8b4SNiklas Cassel }
27357f2f8b4SNiklas Cassel of_node_put(np);
27457f2f8b4SNiklas Cassel
27549cd000dSViresh Kumar drv->opp_tokens = kcalloc(num_possible_cpus(), sizeof(*drv->opp_tokens),
27657f2f8b4SNiklas Cassel GFP_KERNEL);
27749cd000dSViresh Kumar if (!drv->opp_tokens) {
27857f2f8b4SNiklas Cassel ret = -ENOMEM;
27957f2f8b4SNiklas Cassel goto free_drv;
28057f2f8b4SNiklas Cassel }
2811cb8339cSNiklas Cassel
2827d127095SSricharan R for_each_possible_cpu(cpu) {
28349cd000dSViresh Kumar struct dev_pm_opp_config config = {
28449cd000dSViresh Kumar .supported_hw = NULL,
28549cd000dSViresh Kumar };
28649cd000dSViresh Kumar
2877d127095SSricharan R cpu_dev = get_cpu_device(cpu);
2887d127095SSricharan R if (NULL == cpu_dev) {
2897d127095SSricharan R ret = -ENODEV;
29049cd000dSViresh Kumar goto free_opp;
2917d127095SSricharan R }
2927d127095SSricharan R
29357f2f8b4SNiklas Cassel if (drv->data->get_version) {
29449cd000dSViresh Kumar config.supported_hw = &drv->versions;
29549cd000dSViresh Kumar config.supported_hw_count = 1;
296a8811ec7SAnsuel Smith
29749cd000dSViresh Kumar if (pvs_name)
29849cd000dSViresh Kumar config.prop_name = pvs_name;
2991cb8339cSNiklas Cassel }
3001cb8339cSNiklas Cassel
3011cb8339cSNiklas Cassel if (drv->data->genpd_names) {
30249cd000dSViresh Kumar config.genpd_names = drv->data->genpd_names;
30349cd000dSViresh Kumar config.virt_devs = NULL;
30449cd000dSViresh Kumar }
30549cd000dSViresh Kumar
30649cd000dSViresh Kumar if (config.supported_hw || config.genpd_names) {
30749cd000dSViresh Kumar drv->opp_tokens[cpu] = dev_pm_opp_set_config(cpu_dev, &config);
30849cd000dSViresh Kumar if (drv->opp_tokens[cpu] < 0) {
30949cd000dSViresh Kumar ret = drv->opp_tokens[cpu];
31049cd000dSViresh Kumar dev_err(cpu_dev, "Failed to set OPP config\n");
31149cd000dSViresh Kumar goto free_opp;
3127d127095SSricharan R }
3137d127095SSricharan R }
31457f2f8b4SNiklas Cassel }
3157d127095SSricharan R
3167d127095SSricharan R cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1,
3177d127095SSricharan R NULL, 0);
3187d127095SSricharan R if (!IS_ERR(cpufreq_dt_pdev)) {
31957f2f8b4SNiklas Cassel platform_set_drvdata(pdev, drv);
3207d127095SSricharan R return 0;
3217d127095SSricharan R }
3227d127095SSricharan R
3237d127095SSricharan R ret = PTR_ERR(cpufreq_dt_pdev);
3247d127095SSricharan R dev_err(cpu_dev, "Failed to register platform device\n");
3257d127095SSricharan R
3267d127095SSricharan R free_opp:
32749cd000dSViresh Kumar for_each_possible_cpu(cpu)
32849cd000dSViresh Kumar dev_pm_opp_clear_config(drv->opp_tokens[cpu]);
32949cd000dSViresh Kumar kfree(drv->opp_tokens);
33057f2f8b4SNiklas Cassel free_drv:
33157f2f8b4SNiklas Cassel kfree(drv);
3327d127095SSricharan R
3337d127095SSricharan R return ret;
3347d127095SSricharan R }
3357d127095SSricharan R
qcom_cpufreq_remove(struct platform_device * pdev)336*40273232SYangtao Li static void qcom_cpufreq_remove(struct platform_device *pdev)
3377d127095SSricharan R {
33857f2f8b4SNiklas Cassel struct qcom_cpufreq_drv *drv = platform_get_drvdata(pdev);
3397d127095SSricharan R unsigned int cpu;
3407d127095SSricharan R
3417d127095SSricharan R platform_device_unregister(cpufreq_dt_pdev);
3427d127095SSricharan R
34349cd000dSViresh Kumar for_each_possible_cpu(cpu)
34449cd000dSViresh Kumar dev_pm_opp_clear_config(drv->opp_tokens[cpu]);
3457d127095SSricharan R
34649cd000dSViresh Kumar kfree(drv->opp_tokens);
34757f2f8b4SNiklas Cassel kfree(drv);
3487d127095SSricharan R }
3497d127095SSricharan R
3507d127095SSricharan R static struct platform_driver qcom_cpufreq_driver = {
3517d127095SSricharan R .probe = qcom_cpufreq_probe,
352*40273232SYangtao Li .remove_new = qcom_cpufreq_remove,
3537d127095SSricharan R .driver = {
3547d127095SSricharan R .name = "qcom-cpufreq-nvmem",
3557d127095SSricharan R },
3567d127095SSricharan R };
3577d127095SSricharan R
3587d127095SSricharan R static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
35957f2f8b4SNiklas Cassel { .compatible = "qcom,apq8096", .data = &match_data_kryo },
36057f2f8b4SNiklas Cassel { .compatible = "qcom,msm8996", .data = &match_data_kryo },
3611cb8339cSNiklas Cassel { .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
362a8811ec7SAnsuel Smith { .compatible = "qcom,ipq8064", .data = &match_data_krait },
363a8811ec7SAnsuel Smith { .compatible = "qcom,apq8064", .data = &match_data_krait },
364a8811ec7SAnsuel Smith { .compatible = "qcom,msm8974", .data = &match_data_krait },
365a8811ec7SAnsuel Smith { .compatible = "qcom,msm8960", .data = &match_data_krait },
3667d127095SSricharan R {},
3677d127095SSricharan R };
368a5a60316SPali Rohár MODULE_DEVICE_TABLE(of, qcom_cpufreq_match_list);
3697d127095SSricharan R
3707d127095SSricharan R /*
3717d127095SSricharan R * Since the driver depends on smem and nvmem drivers, which may
3727d127095SSricharan R * return EPROBE_DEFER, all the real activity is done in the probe,
3737d127095SSricharan R * which may be defered as well. The init here is only registering
3747d127095SSricharan R * the driver and the platform device.
3757d127095SSricharan R */
qcom_cpufreq_init(void)3767d127095SSricharan R static int __init qcom_cpufreq_init(void)
3777d127095SSricharan R {
3787d127095SSricharan R struct device_node *np = of_find_node_by_path("/");
3797d127095SSricharan R const struct of_device_id *match;
3807d127095SSricharan R int ret;
3817d127095SSricharan R
3827d127095SSricharan R if (!np)
3837d127095SSricharan R return -ENODEV;
3847d127095SSricharan R
3857d127095SSricharan R match = of_match_node(qcom_cpufreq_match_list, np);
3867d127095SSricharan R of_node_put(np);
3877d127095SSricharan R if (!match)
3887d127095SSricharan R return -ENODEV;
3897d127095SSricharan R
3907d127095SSricharan R ret = platform_driver_register(&qcom_cpufreq_driver);
3917d127095SSricharan R if (unlikely(ret < 0))
3927d127095SSricharan R return ret;
3937d127095SSricharan R
3947d127095SSricharan R cpufreq_pdev = platform_device_register_data(NULL, "qcom-cpufreq-nvmem",
3957d127095SSricharan R -1, match, sizeof(*match));
3967d127095SSricharan R ret = PTR_ERR_OR_ZERO(cpufreq_pdev);
3977d127095SSricharan R if (0 == ret)
3987d127095SSricharan R return 0;
3997d127095SSricharan R
4007d127095SSricharan R platform_driver_unregister(&qcom_cpufreq_driver);
4017d127095SSricharan R return ret;
4027d127095SSricharan R }
4037d127095SSricharan R module_init(qcom_cpufreq_init);
4047d127095SSricharan R
qcom_cpufreq_exit(void)4057d127095SSricharan R static void __exit qcom_cpufreq_exit(void)
4067d127095SSricharan R {
4077d127095SSricharan R platform_device_unregister(cpufreq_pdev);
4087d127095SSricharan R platform_driver_unregister(&qcom_cpufreq_driver);
4097d127095SSricharan R }
4107d127095SSricharan R module_exit(qcom_cpufreq_exit);
4117d127095SSricharan R
4127d127095SSricharan R MODULE_DESCRIPTION("Qualcomm Technologies, Inc. CPUfreq driver");
4137d127095SSricharan R MODULE_LICENSE("GPL v2");
414