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/openbmc/u-boot/arch/arm/dts/
H A Dsocfpga.dtsi24 enable-method = "altr,socfpga-smp";
146 compatible = "altr,socfpga-pll-clock";
152 compatible = "altr,socfpga-perip-clk";
160 compatible = "altr,socfpga-perip-clk";
168 compatible = "altr,socfpga-perip-clk";
176 compatible = "altr,socfpga-perip-clk";
183 compatible = "altr,socfpga-perip-clk";
190 compatible = "altr,socfpga-perip-clk";
200 compatible = "altr,socfpga-pll-clock";
206 compatible = "altr,socfpga-perip-clk";
[all …]
H A Dsocfpga_arria10.dtsi32 enable-method = "altr,socfpga-a10-smp";
137 compatible = "altr,socfpga-a10-pll-clock";
145 compatible = "altr,socfpga-a10-perip-clk";
152 compatible = "altr,socfpga-a10-perip-clk";
160 compatible = "altr,socfpga-a10-perip-clk";
167 compatible = "altr,socfpga-a10-perip-clk";
174 compatible = "altr,socfpga-a10-perip-clk";
181 compatible = "altr,socfpga-a10-perip-clk";
188 compatible = "altr,socfpga-a10-perip-clk"
196 compatible = "altr,socfpga-a10-perip-clk";
[all …]
H A Dsocfpga_cyclone5_sr1500.dts9 model = "SoCFPGA Cyclone V SR1500";
10 compatible = "anonymous,socfpga-sr1500", "altr,socfpga-cyclone5", "altr,socfpga";
H A Dsocfpga_cyclone5_is1.dts9 model = "SoCFPGA Cyclone V IS1";
10 compatible = "anonymous,socfpga-is1", "altr,socfpga-cyclone5", "altr,socfpga";
H A Dsocfpga_cyclone5_socdk.dts9 model = "Altera SOCFPGA Cyclone V SoC Development Kit";
10 compatible = "altr,socfpga-cyclone5-socdk", "altr,socfpga-cyclone5", "altr,socfpga";
H A Dsocfpga_arria10_socdk_sdmmc_handoff.dtsi19 model = "SOCFPGA Arria10 Dev Kit"; /* Bootloader setting: uboot.model */
22 cff-file = "socfpga.rbf"; /* Bootloader setting: uboot.rbf_filename */
66 compatible = "altr,socfpga-a10-clk-init";
287 compatible = "altr,socfpga-a10-noc";
322 compatible = "altr,socfpga-hps2fpga-bridge";
327 compatible = "altr,socfpga-lwhps2fpga-bridge";
332 compatible = "altr,socfpga-fpga2hps-bridge";
337 compatible = "altr,socfpga-fpga2sdram0-bridge";
342 compatible = "altr,socfpga-fpga2sdram1-bridge";
347 compatible = "altr,socfpga-fpga2sdram2-bridge";
H A Dsocfpga_cyclone5_dbm_soc1.dts10 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
H A Dsocfpga_arria5_socdk.dts9 model = "Altera SOCFPGA Arria V SoC Development Kit";
10 compatible = "altr,socfpga-arria5", "altr,socfpga";
H A Dsocfpga_cyclone5_de10_nano.dts12 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
H A Dsocfpga_cyclone5_de1_soc.dts10 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
H A Dsocfpga_cyclone5_socrates.dts10 compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga";
H A Dsocfpga_arria10_socdk.dtsi20 model = "Altera SOCFPGA Arria 10";
21 compatible = "altr,socfpga-arria10", "altr,socfpga";
H A Dsocfpga_cyclone5_sockit.dts10 compatible = "terasic,socfpga-cyclone5-sockit", "altr,socfpga-cyclone5", "altr,socfpga";
H A Dsocfpga_cyclone5_de0_nano_soc.dts10 compatible = "terasic,de0-atlas", "altr,socfpga-cyclone5", "altr,socfpga";
/openbmc/u-boot/arch/arm/mach-socfpga/
H A DKconfig41 prompt "Altera SOCFPGA board select"
45 bool "Altera SOCFPGA SoCDK (Arria 10)"
49 bool "Altera SOCFPGA SoCDK (Arria V)"
53 bool "Altera SOCFPGA SoCDK (Cyclone V)"
78 bool "Intel SOCFPGA SoCDK (Stratix 10)"
128 default "socfpga"
H A Dfpga_manager.c6 * This file contains only support functions used also by the SoCFPGA
7 * platform code, the real meat is located in drivers/fpga/socfpga.c .
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dboot0.h3 * Specialty padding for the Altera SoCFPGA preloader image
15 .word 0x1337c0d3; /* SoCFPGA preloader validation word */
20 b reset; /* SoCFPGA Gen5 jumps here */
21 b reset; /* SoCFPGA Gen10 trampoline */
/openbmc/u-boot/doc/device-tree-bindings/fpga/
H A Daltera-socfpga-a10-fpga-mgr.txt1 Altera SOCFPGA Arria10 FPGA Manager
4 - compatible : should contain "altr,socfpga-a10-fpga-mgr"
14 compatible = "altr,socfpga-a10-fpga-mgr";
/openbmc/u-boot/drivers/ddr/altera/
H A DKconfig2 bool "SoCFPGA DDR SDRAM driver"
5 Enable DDR SDRAM controller for the SoCFPGA devices.
/openbmc/u-boot/tools/
H A Dsocfpgaimage.c10 * Bootable SoCFPGA image requires a structure of the following format
13 * There are two versions of the SoCFPGA header format, v0 and v1.
47 * only possible to make the SoCFPGA jump forward. The U-Boot bootloader
49 * start of the SoCFPGA header, which jumps to the reset vector.
272 printf("Looks like a sane SOCFPGA preloader\n"); in socfpgaimage_print_header()
274 printf("Not a sane SOCFPGA preloader\n"); in socfpgaimage_print_header()
376 "Altera SoCFPGA Cyclone V / Arria V image support",
391 "Altera SoCFPGA Arria10 image support",
/openbmc/u-boot/drivers/clk/altera/
H A Dclk-arria10.c249 "altr,socfpga-a10-pll-clock") && in socfpga_a10_clk_bind()
251 "altr,socfpga-a10-perip-clk") && in socfpga_a10_clk_bind()
253 "altr,socfpga-a10-gate-clk") && in socfpga_a10_clk_bind()
281 "altr,socfpga-a10-pll-clock")) { in socfpga_a10_clk_probe()
288 "altr,socfpga-a10-perip-clk")) { in socfpga_a10_clk_probe()
291 "altr,socfpga-a10-gate-clk")) { in socfpga_a10_clk_probe()
/openbmc/u-boot/doc/
H A DREADME.socfpga2 SOCFPGA Documentation for U-Boot and SPL
6 based SOCFPGA. To know more about the hardware itself, please refer to
14 controller support within SOCFPGA
111 $ ./arch/arm/mach-socfpga/qts-filter.sh \
/openbmc/u-boot/drivers/mmc/
H A Dsocfpga_dw_mmc.c31 /* socfpga implmentation specific driver private data */
122 * We only have one dwmmc block on gen5 SoCFPGA. in socfpga_dwmmc_ofdata_to_platdata()
183 { .compatible = "altr,socfpga-dw-mshc" },
/openbmc/u-boot/drivers/reset/
H A DKconfig95 bool "Reset controller driver for SoCFPGA"
99 Support for reset controller on SoCFPGA platform.
/openbmc/u-boot/board/terasic/de10-nano/
H A DMakefile6 obj-y := socfpga.o

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