183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2beee6a30SMarek Vasut /* 3beee6a30SMarek Vasut * Specialty padding for the Altera SoCFPGA preloader image 4beee6a30SMarek Vasut */ 5beee6a30SMarek Vasut 6beee6a30SMarek Vasut #ifndef __BOOT0_H 7beee6a30SMarek Vasut #define __BOOT0_H 8beee6a30SMarek Vasut 9a002077dSPhilipp Tomsich _start: 10a002077dSPhilipp Tomsich ARM_VECTORS 11a002077dSPhilipp Tomsich 12beee6a30SMarek Vasut #ifdef CONFIG_SPL_BUILD 134c0f3e7fSChee, Tien Fong .balignl 64,0xf33db33f; 14beee6a30SMarek Vasut 154c0f3e7fSChee, Tien Fong .word 0x1337c0d3; /* SoCFPGA preloader validation word */ 164c0f3e7fSChee, Tien Fong .word 0xc01df00d; /* Version, flags, length */ 174c0f3e7fSChee, Tien Fong .word 0xcafec0d3; /* Checksum, zero-pad */ 184c0f3e7fSChee, Tien Fong nop; 194c0f3e7fSChee, Tien Fong 20*34fc2a6eSMarek Vasut b reset; /* SoCFPGA Gen5 jumps here */ 21*34fc2a6eSMarek Vasut b reset; /* SoCFPGA Gen10 trampoline */ 224c0f3e7fSChee, Tien Fong nop; 234c0f3e7fSChee, Tien Fong nop; 244c0f3e7fSChee, Tien Fong #endif 25beee6a30SMarek Vasut 26beee6a30SMarek Vasut #endif /* __BOOT0_H */ 27